Changeset 396 for trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h
- Timestamp:
- May 28, 2013, 11:02:08 AM (11 years ago)
- File:
-
- 1 edited
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trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h
r389 r396 1 1 ////////////////////////////////////////////////////////////////////////////// 2 // File: tsar_xbar_cluster _mmu.h2 // File: tsar_xbar_cluster.h 3 3 // Author: Alain Greiner 4 4 // Copyright: UPMC/LIP6 5 // Date : march 201 15 // Date : march 2013 6 6 // This program is released under the GNU public license 7 7 ////////////////////////////////////////////////////////////////////////////// … … 34 34 #include "vci_cc_vcache_wrapper.h" 35 35 36 ///////////////////////////////////////////////////////////37 // VCI parameters for DIRECT network38 ///////////////////////////////////////////////////////////39 #define cell_width 440 #define address_width 3241 #define plen_width 842 #define error_width 243 #define clen_width 144 #define rflag_width 145 #define srcid_width 1446 #define pktid_width 447 #define trdid_width 448 #define wrplen_width 149 50 ///////////////////////////////////////////////////////////51 // VCI parameters for EXTERNAL network52 ///////////////////////////////////////////////////////////53 #define cell_width_ext 854 #define address_width_ext address_width55 #define plen_width_ext plen_width56 #define error_width_ext error_width57 #define clen_width_ext clen_width58 #define rflag_width_ext rflag_width59 #define srcid_width_ext srcid_width60 #define pktid_width_ext pktid_width61 #define trdid_width_ext trdid_width62 #define wrplen_width_ext wrplen_width63 64 36 namespace soclib { namespace caba { 65 37 66 38 /////////////////////////////////////////////////////////////////////////// 67 template< 68 typename iss_t, int cmd_width, int rsp_width69 >70 class TsarXbarCluster39 template<size_t dspin_cmd_width, 40 size_t dspin_rsp_width, 41 typename vci_param_int, 42 typename vci_param_ext> class TsarXbarCluster 71 43 /////////////////////////////////////////////////////////////////////////// 72 44 : public soclib::caba::BaseModule 73 45 { 74 // Define VCI parameters 75 typedef soclib::caba::VciParams<cell_width, 76 plen_width, 77 address_width, 78 error_width, 79 clen_width, 80 rflag_width, 81 srcid_width, 82 pktid_width, 83 trdid_width, 84 wrplen_width> vci_param_d; 85 86 typedef soclib::caba::VciParamsBis<cell_width_ext, 87 plen_width_ext, 88 address_width_ext, 89 error_width_ext, 90 clen_width_ext, 91 rflag_width_ext, 92 srcid_width_ext, 93 pktid_width_ext, 94 trdid_width_ext, 95 wrplen_width_ext> vci_param_x; 96 97 public: 98 99 // Ports 100 sc_in<bool> p_clk; 101 sc_in<bool> p_resetn; 102 soclib::caba::DspinOutput<cmd_width> **p_cmd_out; 103 soclib::caba::DspinInput<cmd_width> **p_cmd_in; 104 soclib::caba::DspinOutput<rsp_width> **p_rsp_out; 105 soclib::caba::DspinInput<rsp_width> **p_rsp_in; 46 public: 47 48 // Ports 49 sc_in<bool> p_clk; 50 sc_in<bool> p_resetn; 51 soclib::caba::DspinOutput<dspin_cmd_width> **p_cmd_out; 52 soclib::caba::DspinInput<dspin_cmd_width> **p_cmd_in; 53 soclib::caba::DspinOutput<dspin_rsp_width> **p_rsp_out; 54 soclib::caba::DspinInput<dspin_rsp_width> **p_rsp_in; 106 55 107 56 // interrupt signals 108 sc_signal<bool>signal_false;109 sc_signal<bool>signal_proc_it[8];110 sc_signal<bool>signal_irq_mdma[8];111 sc_signal<bool>signal_irq_mtty[23];112 sc_signal<bool> signal_irq_mnic_rx[8];// unused113 sc_signal<bool> signal_irq_mnic_tx[8];// unused114 sc_signal<bool>signal_irq_bdev;115 116 117 DspinSignals<cmd_width>signal_dspin_cmd_l2g_d;118 DspinSignals<cmd_width>signal_dspin_cmd_g2l_d;119 DspinSignals<cmd_width>signal_dspin_m2p_l2g_c;120 DspinSignals<cmd_width>signal_dspin_m2p_g2l_c;121 DspinSignals<rsp_width>signal_dspin_rsp_l2g_d;122 DspinSignals<rsp_width>signal_dspin_rsp_g2l_d;123 DspinSignals<rsp_width>signal_dspin_p2m_l2g_c;124 DspinSignals<rsp_width>signal_dspin_p2m_g2l_c;125 126 127 VciSignals<vci_param_d>signal_vci_ini_proc[8];128 VciSignals<vci_param_d>signal_vci_ini_mdma;129 VciSignals<vci_param_d>signal_vci_ini_bdev;130 131 VciSignals<vci_param_d>signal_vci_tgt_memc;132 VciSignals<vci_param_d>signal_vci_tgt_xicu;133 VciSignals<vci_param_d>signal_vci_tgt_mdma;134 VciSignals<vci_param_d>signal_vci_tgt_mtty;135 VciSignals<vci_param_d>signal_vci_tgt_bdev;136 VciSignals<vci_param_d>signal_vci_tgt_brom;137 VciSignals<vci_param_d>signal_vci_tgt_fbuf;138 VciSignals<vci_param_d>signal_vci_tgt_mnic;139 140 141 DspinSignals<cmd_width> signal_dspin_cmd_proc_i[8];142 DspinSignals<rsp_width> signal_dspin_rsp_proc_i[8];143 DspinSignals<cmd_width> signal_dspin_cmd_mdma_i;144 DspinSignals<rsp_width> signal_dspin_rsp_mdma_i;145 DspinSignals<cmd_width> signal_dspin_cmd_bdev_i;146 DspinSignals<rsp_width> signal_dspin_rsp_bdev_i;147 148 DspinSignals<cmd_width> signal_dspin_cmd_memc_t;149 DspinSignals<rsp_width> signal_dspin_rsp_memc_t;150 DspinSignals<cmd_width> signal_dspin_cmd_xicu_t;151 DspinSignals<rsp_width> signal_dspin_rsp_xicu_t;152 DspinSignals<cmd_width> signal_dspin_cmd_mdma_t;153 DspinSignals<rsp_width> signal_dspin_rsp_mdma_t;154 DspinSignals<cmd_width> signal_dspin_cmd_mtty_t;155 DspinSignals<rsp_width> signal_dspin_rsp_mtty_t;156 DspinSignals<cmd_width> signal_dspin_cmd_bdev_t;157 DspinSignals<rsp_width> signal_dspin_rsp_bdev_t;158 DspinSignals<cmd_width> signal_dspin_cmd_brom_t;159 DspinSignals<rsp_width> signal_dspin_rsp_brom_t;160 DspinSignals<cmd_width> signal_dspin_cmd_fbuf_t;161 DspinSignals<rsp_width> signal_dspin_rsp_fbuf_t;162 DspinSignals<cmd_width> signal_dspin_cmd_mnic_t;163 DspinSignals<rsp_width> signal_dspin_rsp_mnic_t;164 165 166 DspinSignals<cmd_width> signal_dspin_m2p_memc;167 DspinSignals<rsp_width> signal_dspin_p2m_memc;168 DspinSignals<cmd_width> signal_dspin_m2p_proc[8];169 DspinSignals<rsp_width> signal_dspin_p2m_proc[8];170 171 // external RAMVCI signal172 VciSignals<vci_param_x>signal_vci_xram;173 57 sc_signal<bool> signal_false; 58 sc_signal<bool> signal_proc_it[8]; 59 sc_signal<bool> signal_irq_mdma[8]; 60 sc_signal<bool> signal_irq_mtty[23]; 61 sc_signal<bool> signal_irq_mnic_rx[8]; // unused 62 sc_signal<bool> signal_irq_mnic_tx[8]; // unused 63 sc_signal<bool> signal_irq_bdev; 64 65 // DSPIN signals between DSPIN routers and local_crossbars 66 DspinSignals<dspin_cmd_width> signal_dspin_cmd_l2g_d; 67 DspinSignals<dspin_cmd_width> signal_dspin_cmd_g2l_d; 68 DspinSignals<dspin_cmd_width> signal_dspin_m2p_l2g_c; 69 DspinSignals<dspin_cmd_width> signal_dspin_m2p_g2l_c; 70 DspinSignals<dspin_rsp_width> signal_dspin_rsp_l2g_d; 71 DspinSignals<dspin_rsp_width> signal_dspin_rsp_g2l_d; 72 DspinSignals<dspin_rsp_width> signal_dspin_p2m_l2g_c; 73 DspinSignals<dspin_rsp_width> signal_dspin_p2m_g2l_c; 74 75 // Direct VCI signals to VCI/DSPIN wrappers 76 VciSignals<vci_param_int> signal_vci_ini_proc[8]; 77 VciSignals<vci_param_int> signal_vci_ini_mdma; 78 VciSignals<vci_param_int> signal_vci_ini_bdev; 79 80 VciSignals<vci_param_int> signal_vci_tgt_memc; 81 VciSignals<vci_param_int> signal_vci_tgt_xicu; 82 VciSignals<vci_param_int> signal_vci_tgt_mdma; 83 VciSignals<vci_param_int> signal_vci_tgt_mtty; 84 VciSignals<vci_param_int> signal_vci_tgt_bdev; 85 VciSignals<vci_param_int> signal_vci_tgt_brom; 86 VciSignals<vci_param_int> signal_vci_tgt_fbuf; 87 VciSignals<vci_param_int> signal_vci_tgt_mnic; 88 89 // Direct DSPIN signals to local crossbars 90 DspinSignals<dspin_cmd_width> signal_dspin_cmd_proc_i[8]; 91 DspinSignals<dspin_rsp_width> signal_dspin_rsp_proc_i[8]; 92 DspinSignals<dspin_cmd_width> signal_dspin_cmd_mdma_i; 93 DspinSignals<dspin_rsp_width> signal_dspin_rsp_mdma_i; 94 DspinSignals<dspin_cmd_width> signal_dspin_cmd_bdev_i; 95 DspinSignals<dspin_rsp_width> signal_dspin_rsp_bdev_i; 96 97 DspinSignals<dspin_cmd_width> signal_dspin_cmd_memc_t; 98 DspinSignals<dspin_rsp_width> signal_dspin_rsp_memc_t; 99 DspinSignals<dspin_cmd_width> signal_dspin_cmd_xicu_t; 100 DspinSignals<dspin_rsp_width> signal_dspin_rsp_xicu_t; 101 DspinSignals<dspin_cmd_width> signal_dspin_cmd_mdma_t; 102 DspinSignals<dspin_rsp_width> signal_dspin_rsp_mdma_t; 103 DspinSignals<dspin_cmd_width> signal_dspin_cmd_mtty_t; 104 DspinSignals<dspin_rsp_width> signal_dspin_rsp_mtty_t; 105 DspinSignals<dspin_cmd_width> signal_dspin_cmd_bdev_t; 106 DspinSignals<dspin_rsp_width> signal_dspin_rsp_bdev_t; 107 DspinSignals<dspin_cmd_width> signal_dspin_cmd_brom_t; 108 DspinSignals<dspin_rsp_width> signal_dspin_rsp_brom_t; 109 DspinSignals<dspin_cmd_width> signal_dspin_cmd_fbuf_t; 110 DspinSignals<dspin_rsp_width> signal_dspin_rsp_fbuf_t; 111 DspinSignals<dspin_cmd_width> signal_dspin_cmd_mnic_t; 112 DspinSignals<dspin_rsp_width> signal_dspin_rsp_mnic_t; 113 114 // Coherence DSPIN signals to local crossbar 115 DspinSignals<dspin_cmd_width> signal_dspin_m2p_memc; 116 DspinSignals<dspin_rsp_width> signal_dspin_p2m_memc; 117 DspinSignals<dspin_cmd_width> signal_dspin_m2p_proc[8]; 118 DspinSignals<dspin_rsp_width> signal_dspin_p2m_proc[8]; 119 120 // external RAM to MEMC VCI signal 121 VciSignals<vci_param_ext> signal_vci_xram; 122 174 123 // Components 175 124 176 VciCcVCacheWrapper<vci_param_d, cmd_width, rsp_width, iss_t>* proc[8]; 177 VciDspinInitiatorWrapper<vci_param_d,cmd_width,rsp_width>* wi_proc[4]; 178 179 VciMemCache<vci_param_d, vci_param_x, rsp_width, cmd_width> * memc; 180 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_memc; 181 182 VciXicu<vci_param_d>* xicu; 183 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_xicu; 184 185 VciMultiDma<vci_param_d>* mdma; 186 VciDspinInitiatorWrapper<vci_param_d,cmd_width,rsp_width>* wi_mdma; 187 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_mdma; 188 189 VciSimpleRam<vci_param_x>* xram; 190 191 VciSimpleRam<vci_param_d>* brom; 192 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_brom; 193 194 VciMultiTty<vci_param_d>* mtty; 195 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_mtty; 196 197 VciFrameBuffer<vci_param_d>* fbuf; 198 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_fbuf; 199 200 VciMultiNic<vci_param_d>* mnic; 201 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_mnic; 202 203 VciBlockDeviceTsar<vci_param_d>* bdev; 204 VciDspinInitiatorWrapper<vci_param_d,cmd_width,rsp_width>* wi_bdev; 205 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_bdev; 206 207 DspinLocalCrossbar<cmd_width>* xbar_cmd_d; 208 DspinLocalCrossbar<rsp_width>* xbar_rsp_d; 209 DspinLocalCrossbar<cmd_width>* xbar_m2p_c; 210 DspinLocalCrossbar<rsp_width>* xbar_p2m_c; 211 212 VirtualDspinRouter<cmd_width>* router_cmd; 213 VirtualDspinRouter<rsp_width>* router_rsp; 214 215 TsarXbarCluster( sc_module_name insname, 216 size_t nb_procs, // number of processors 217 size_t nb_ttys, // number of TTY terminals 218 size_t nb_dmas, // number of DMA channels 125 VciCcVCacheWrapper<vci_param_int, 126 dspin_cmd_width, 127 dspin_rsp_width, 128 GdbServer<Mips32ElIss> >* proc[8]; 129 130 VciDspinInitiatorWrapper<vci_param_int, 131 dspin_cmd_width, 132 dspin_rsp_width>* wi_proc[8]; 133 134 VciMemCache<vci_param_int, 135 vci_param_ext, 136 dspin_rsp_width, 137 dspin_cmd_width>* memc; 138 139 VciDspinTargetWrapper<vci_param_int, 140 dspin_cmd_width, 141 dspin_rsp_width>* wt_memc; 142 143 VciXicu<vci_param_int>* xicu; 144 145 VciDspinTargetWrapper<vci_param_int, 146 dspin_cmd_width, 147 dspin_rsp_width>* wt_xicu; 148 149 VciMultiDma<vci_param_int>* mdma; 150 151 VciDspinInitiatorWrapper<vci_param_int, 152 dspin_cmd_width, 153 dspin_rsp_width>* wi_mdma; 154 155 VciDspinTargetWrapper<vci_param_int, 156 dspin_cmd_width, 157 dspin_rsp_width>* wt_mdma; 158 159 VciSimpleRam<vci_param_ext>* xram; 160 161 VciSimpleRam<vci_param_int>* brom; 162 163 VciDspinTargetWrapper<vci_param_int, 164 dspin_cmd_width, 165 dspin_rsp_width>* wt_brom; 166 167 VciMultiTty<vci_param_int>* mtty; 168 169 VciDspinTargetWrapper<vci_param_int, 170 dspin_cmd_width, 171 dspin_rsp_width>* wt_mtty; 172 173 VciFrameBuffer<vci_param_int>* fbuf; 174 175 VciDspinTargetWrapper<vci_param_int, 176 dspin_cmd_width, 177 dspin_rsp_width>* wt_fbuf; 178 179 VciMultiNic<vci_param_int>* mnic; 180 181 VciDspinTargetWrapper<vci_param_int, 182 dspin_cmd_width, 183 dspin_rsp_width>* wt_mnic; 184 185 VciBlockDeviceTsar<vci_param_int>* bdev; 186 187 VciDspinInitiatorWrapper<vci_param_int, 188 dspin_cmd_width, 189 dspin_rsp_width>* wi_bdev; 190 191 VciDspinTargetWrapper<vci_param_int, 192 dspin_cmd_width, 193 dspin_rsp_width>* wt_bdev; 194 195 DspinLocalCrossbar<dspin_cmd_width>* xbar_cmd_d; 196 DspinLocalCrossbar<dspin_rsp_width>* xbar_rsp_d; 197 DspinLocalCrossbar<dspin_cmd_width>* xbar_m2p_c; 198 DspinLocalCrossbar<dspin_rsp_width>* xbar_p2m_c; 199 200 VirtualDspinRouter<dspin_cmd_width>* router_cmd; 201 VirtualDspinRouter<dspin_rsp_width>* router_rsp; 202 203 TsarXbarCluster( sc_module_name insname, 204 size_t nb_procs, // processors 205 size_t nb_ttys, // TTY terminals 206 size_t nb_dmas, // DMA channels 219 207 size_t x, // x coordinate 220 208 size_t y, // y coordinate 221 209 size_t cluster, // y + ymax*x 222 const soclib::common::MappingTable &mtd, // direct mapping table223 const soclib::common::MappingTable &mtx, // xram mapping table224 size_t x_width, // x field number ofbits225 size_t y_width, // y field number ofbits226 size_t l_width, // l field number ofbits227 size_t 228 size_t 210 const soclib::common::MappingTable &mtd, // internal 211 const soclib::common::MappingTable &mtx, // external 212 size_t x_width, // x field bits 213 size_t y_width, // y field bits 214 size_t l_width, // l field bits 215 size_t tgtid_memc, 216 size_t tgtid_xicu, 229 217 size_t tgtid_mdma, 230 218 size_t tgtid_fbuf, … … 239 227 size_t l1_d_ways, 240 228 size_t l1_d_sets, 241 size_t xram_latency, // external ram latency242 bool io, // I/O cluster if true243 size_t xfb, // f rame bufferpixels244 size_t yfb, // f rame bufferlines245 char* disk_name, // virtual disk for BDEV246 size_t block_size, // block size for BDEV247 size_t nic_channels, // number ofchannels248 char* nic_rx_name, // file name rx packets249 char* nic_tx_name, // file name tx packets250 uint32_t nic_timeout, // number ofcycles251 const Loader &loader, // loader for BROM 252 uint32_t frozen_cycles, // max frozen cycles229 size_t xram_latency, // external ram 230 bool io, // I/O cluster 231 size_t xfb, // fbf pixels 232 size_t yfb, // fbf lines 233 char* disk_name, // virtual disk 234 size_t block_size, // block size 235 size_t nic_channels, // number channels 236 char* nic_rx_name, // filename rx 237 char* nic_tx_name, // filename tx 238 uint32_t nic_timeout, // cycles 239 const Loader &loader, 240 uint32_t frozen_cycles, 253 241 uint32_t start_debug_cycle, 254 242 bool memc_debug_ok, 255 243 bool proc_debug_ok); 256 244 257 ~TsarXbarCluster();258 245 }; 259 246 }}
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