Ignore:
Timestamp:
Jun 6, 2013, 9:42:29 PM (10 years ago)
Author:
alain
Message:

Updating vci_cc_vcache_wrapper and vci_mem_cache to comply with the new DSPIN signals (explcit EOP).

Location:
trunk/modules/vci_mem_cache/caba/source
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h

    r395 r403  
    106106        CC_RECEIVE_IDLE,
    107107        CC_RECEIVE_CLEANUP,
     108        CC_RECEIVE_CLEANUP_EOP,
    108109        CC_RECEIVE_MULTI_ACK
    109110      };
     
    496497      GenericFifo<data_t>    m_cmd_cas_wdata_fifo;
    497498
    498       // Fifo between INIT_RSP fsm and CLEANUP fsm
     499      // Fifo between CC_RECEIVE fsm and CLEANUP fsm
    499500      GenericFifo<uint64_t>  m_cc_receive_to_cleanup_fifo;
    500501     
    501       // Fifo between INIT_RSP fsm and MULTI_ACK fsm
     502      // Fifo between CC_RECEIVE fsm and MULTI_ACK fsm
    502503      GenericFifo<uint64_t>  m_cc_receive_to_multi_ack_fifo;
    503504
  • trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp

    r395 r403  
    8484  "CC_RECEIVE_IDLE",
    8585  "CC_RECEIVE_CLEANUP",
     86  "CC_RECEIVE_CLEANUP_EOP",
    8687  "CC_RECEIVE_MULTI_ACK"
    8788};
     
    10971098  switch(r_multi_ack_fsm.read())
    10981099  {
     1100    ///////////////////
    10991101    case MULTI_ACK_IDLE:
    11001102      {
    11011103        bool multi_ack_fifo_rok = m_cc_receive_to_multi_ack_fifo.rok();
    11021104
    1103         // None Multicast Acknowledgement received and
    1104         // none WRITE FSM UPT decrement request
    1105         if( not multi_ack_fifo_rok and
    1106             not r_write_to_multi_ack_req.read())
    1107         {
    1108           break;
    1109         }
    1110 
    1111         // WRITE FSM request to decrement update table response counter
    1112         // Priority to Multicast Acknowledgement priority
     1105        // No CC_RECEIVE FSM request and no WRITE FSM request
     1106        if( not multi_ack_fifo_rok and not r_write_to_multi_ack_req.read()) break;
     1107
     1108        // handling WRITE FSM request to decrement update table response counter
     1109        // if no CC_RECEIVE FSM request
    11131110        if(not multi_ack_fifo_rok)
    11141111        {
     
    11201117        }
    11211118
    1122         // Multicast Acknowledgement received
     1119        // Handling CC_RECEIVE FSM request
    11231120        uint64_t flit = m_cc_receive_to_multi_ack_fifo.read();
    11241121
     
    11261123          DspinDhccpParam::dspin_get(flit, DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
    11271124
    1128         bool eop =
    1129           (DspinDhccpParam::dspin_get(flit, DspinDhccpParam::FROM_L1_EOP) == 0x1);
    1130 
    1131         if(updt_index >= m_upt.size())
    1132         {
    1133           std::cout
    1134             << "VCI_MEM_CACHE ERROR " << name()
    1135             << " MULTI_ACK_IDLE state" << std::endl
    1136             << "index too large for UPT: "
    1137             << std::dec
    1138             << " / UPT index = " << updt_index
    1139             << " / UPT size = "  << m_upt.size()
    1140             << std::endl;
    1141 
    1142           exit(0);
    1143         }
    1144 
    1145         if(not eop)
    1146         {
    1147           std::cout
    1148             << "VCI_MEM_CACHE ERROR " << name()
    1149             << " MULTI_ACK_IDLE state" << std::endl
    1150             << "A Multicast Acknowledgement must be an one flit packet"
    1151             << std::endl;
    1152 
    1153           exit(0);
    1154         }
     1125        assert( (updt_index < m_upt.size()) and
     1126        "VCI_MEM_CACHE ERROR in MULTI_ACK_IDLE : index too large for UPT");
    11551127
    11561128        cc_receive_to_multi_ack_fifo_get = true;
     
    11711143      }
    11721144
     1145    ////////////////////////
    11731146    case MULTI_ACK_UPT_LOCK:
    11741147      {
     
    12141187      }
    12151188
     1189    /////////////////////////
    12161190    case MULTI_ACK_UPT_CLEAR:
    12171191      {
     
    12581232      }
    12591233
     1234    /////////////////////////
    12601235    case MULTI_ACK_WRITE_RSP:
    12611236      {
     
    37513726  switch(r_cleanup_fsm.read())
    37523727  {
    3753     case CLEANUP_IDLE:
    3754     {
    3755       // Get first DSPIN flit of the CLEANUP command
     3728    //////////////////
     3729    case CLEANUP_IDLE:     // Get first DSPIN flit of the CLEANUP command
     3730    {
    37563731      if(not m_cc_receive_to_cleanup_fifo.rok()) break;
    37573732
     
    37763751        DspinDhccpParam::dspin_get(
    37773752            flit,
    3778             DspinDhccpParam::CLEANUP_NLINE_MSB)
    3779         << 32;
     3753            DspinDhccpParam::CLEANUP_NLINE_MSB) << 32;
    37803754
    37813755      r_cleanup_inst  = (type == DspinDhccpParam::TYPE_CLEANUP_INST);
     
    37943768      m_cpt_cleanup++;
    37953769      cc_receive_to_cleanup_fifo_get = true;
    3796       r_cleanup_fsm                 = CLEANUP_GET_NLINE;
     3770      r_cleanup_fsm                  = CLEANUP_GET_NLINE;
    37973771
    37983772#if DEBUG_MEMC_CLEANUP
     
    38103784    }
    38113785
    3812     case CLEANUP_GET_NLINE:
    3813     {
    3814       // Get second flit of cleanup command
     3786    ///////////////////////
     3787    case CLEANUP_GET_NLINE:  // GET second DSPIN flit of the cleanup command
     3788    {
    38153789      if(not m_cc_receive_to_cleanup_fifo.rok()) break;
    38163790
    38173791      uint64_t flit = m_cc_receive_to_cleanup_fifo.read();
    38183792
    3819       addr_t nline =
    3820         r_cleanup_nline.read() |
     3793      addr_t nline = r_cleanup_nline.read() |
    38213794        DspinDhccpParam::dspin_get(flit, DspinDhccpParam::CLEANUP_NLINE_LSB);
    38223795
    3823       bool eop =
    3824         DspinDhccpParam::dspin_get(flit, DspinDhccpParam::FROM_L1_EOP) == 0x1;
    3825 
    3826       assert(
    3827           eop &&
    3828           "VCI_MEM_CACHE ERROR: "
    3829           "CLEANUP command must have exactly two flits");
    3830 
    38313796      cc_receive_to_cleanup_fifo_get = true;
    3832       r_cleanup_nline               = nline;
    3833       r_cleanup_fsm                 = CLEANUP_DIR_REQ;
     3797      r_cleanup_nline                = nline;
     3798      r_cleanup_fsm                  = CLEANUP_DIR_REQ;
    38343799
    38353800#if DEBUG_MEMC_CLEANUP
     
    38473812    }
    38483813
     3814    /////////////////////
    38493815    case CLEANUP_DIR_REQ:
    38503816    {
     
    38653831    }
    38663832
     3833    //////////////////////
    38673834    case CLEANUP_DIR_LOCK:
    38683835    {
     
    39463913    }
    39473914
     3915    ///////////////////////
    39483916    case CLEANUP_DIR_WRITE:
    39493917    {
     
    40203988    }
    40213989
     3990    //////////////////////
    40223991    case CLEANUP_HEAP_REQ:
    40233992    {
     
    40394008    }
    40404009
     4010    //////////////////////
    40414011    case CLEANUP_HEAP_LOCK:
    40424012    {
     
    41984168    }
    41994169
     4170    ////////////////////////
    42004171    case CLEANUP_HEAP_SEARCH:
    42014172    {
     
    59695940  switch(r_cc_receive_fsm.read())
    59705941  {
     5942    /////////////////////
    59715943    case CC_RECEIVE_IDLE:
    59725944      {
     
    59935965        assert(
    59945966            false &&
    5995             "VCI_MEM_CACHE ERROR: Incorrect type in coherence request from "
    5996             "L1 Cache");
     5967            "VCI_MEM_CACHE ERROR: Illegal type in coherence request");
    59975968       
    59985969        break;
    59995970      }
    6000     case CC_RECEIVE_CLEANUP:
    6001       {
    6002         // wait for a valid cleanup flit
    6003         // wait for a WOK in the CC_RECEIVE to CLEANUP fifo
     5971    ////////////////////////
     5972    case CC_RECEIVE_CLEANUP:  // write first CLEANUP flit in CC_RECEIVE to CLEANUP fifo
     5973      {
    60045974        if(not p_dspin_in.write or not m_cc_receive_to_cleanup_fifo.wok()) break;
    60055975
    6006         bool eop = (
    6007             DspinDhccpParam::dspin_get(
    6008               p_dspin_in.data.read(),
    6009               DspinDhccpParam::FROM_L1_EOP)
    6010             == 0x1);
     5976        assert( not p_dspin_in.eop.read() and
     5977        "VCI_MEM_CACHE ERROR in CC_RECEIVE : CLEANUP command must have two flits");
    60115978
    60125979        cc_receive_to_cleanup_fifo_put = true;
    6013         if(eop)
    6014         {
    6015           r_cc_receive_fsm = CC_RECEIVE_IDLE;
    6016         }
     5980        r_cc_receive_fsm               = CC_RECEIVE_CLEANUP_EOP;
    60175981
    60185982        break;
    60195983      }
     5984    ////////////////////////////
     5985    case CC_RECEIVE_CLEANUP_EOP:  // write second CLEANUP flit in CC_RECEIVE to CLEANUP fifo
     5986      {
     5987        if(not p_dspin_in.write or not m_cc_receive_to_cleanup_fifo.wok()) break;
     5988
     5989        assert( p_dspin_in.eop.read() and
     5990        "VCI_MEM_CACHE ERROR in CC_RECEIVE : CLEANUP command must have two flits");
     5991
     5992        cc_receive_to_cleanup_fifo_put = true;
     5993        r_cc_receive_fsm               = CC_RECEIVE_IDLE;
     5994
     5995        break;
     5996      }
     5997
     5998    //////////////////////////
    60205999    case CC_RECEIVE_MULTI_ACK:
    60216000      {
    6022         // wait for a valid multicast acknowledgement flit
    60236001        // wait for a WOK in the CC_RECEIVE to MULTI_ACK fifo
    60246002        if(not p_dspin_in.write or not m_cc_receive_to_multi_ack_fifo.wok()) break;
    60256003
    6026         bool eop = (
    6027             DspinDhccpParam::dspin_get(
    6028               p_dspin_in.data.read(),
    6029               DspinDhccpParam::FROM_L1_EOP)
    6030             == 0x1);
     6004        assert( p_dspin_in.eop.read() and
     6005        "VCI_MEM_CACHE ERROR in CC_RECEIVE : MULTI_ACK command must have one flit");
    60316006
    60326007        cc_receive_to_multi_ack_fifo_put  = true;
    6033         if(eop)
    6034         {
    6035           r_cc_receive_fsm = CC_RECEIVE_IDLE;
    6036         }
    6037 
     6008        r_cc_receive_fsm                  = CC_RECEIVE_IDLE;
    60386009        break;
    6039       }
    6040     default:
    6041       {
    6042         assert(
    6043             false &&
    6044             "VCI_MEM_CACHE ERROR: Invalid state in CC_RECEIVE FSM");
    60456010      }
    60466011  }
     
    73987363
    73997364  ////////////////////////////////////////////////////////////////////
    7400   // Initiator command signals on the p_dspin_out port (CC_SEND FSM)
     7365  // p_dspin_out port (CC_SEND FSM)
    74017366  ////////////////////////////////////////////////////////////////////
    74027367
    74037368  p_dspin_out.write = false;
     7369  p_dspin_out.eop   = false;
    74047370  p_dspin_out.data  = 0;
    74057371
    74067372  switch(r_cc_send_fsm.read())
    74077373  {
    7408  
     7374    ///////////////////////////
    74097375    case CC_SEND_XRAM_RSP_IDLE:
    74107376    case CC_SEND_WRITE_IDLE:
     
    74137379        break;
    74147380
     7381    ////////////////////////
    74157382    case CC_SEND_CLEANUP_ACK:
    74167383      {
     
    74327399        DspinDhccpParam::dspin_set(
    74337400            flit,
    7434             1ULL,
    7435             DspinDhccpParam::FROM_MC_EOP);
    7436 
    7437         DspinDhccpParam::dspin_set(
    7438             flit,
    74397401            dest,
    74407402            DspinDhccpParam::CLEANUP_ACK_DEST);
     
    74557417            DspinDhccpParam::FROM_MC_TYPE);
    74567418
     7419        p_dspin_out.eop   = true;
    74577420        p_dspin_out.write = true;
    74587421        p_dspin_out.data  = flit;
     
    74617424      }
    74627425
     7426    ///////////////////////////////////
    74637427    case CC_SEND_XRAM_RSP_INVAL_HEADER:
    74647428      {
     
    75067470      }
    75077471
     7472    //////////////////////////////////
    75087473    case CC_SEND_XRAM_RSP_INVAL_NLINE:
    75097474      {
    75107475        uint64_t flit = 0;
    7511 
    7512         DspinDhccpParam::dspin_set(
    7513             flit,
    7514             1ULL,
    7515             DspinDhccpParam::FROM_MC_EOP);
    75167476
    75177477        DspinDhccpParam::dspin_set(
     
    75217481       
    75227482
     7483        p_dspin_out.eop   = true;
    75237484        p_dspin_out.write = true;
    75247485        p_dspin_out.data  = flit;
     
    75277488      }
    75287489
     7490    /////////////////////////////////////
    75297491    case CC_SEND_XRAM_RSP_BRDCAST_HEADER:
    75307492    case CC_SEND_WRITE_BRDCAST_HEADER:
     
    75537515        break;
    75547516      }
    7555 
     7517    ////////////////////////////////////
    75567518    case CC_SEND_XRAM_RSP_BRDCAST_NLINE:
    75577519      {
    75587520        uint64_t flit = 0;
    7559 
    7560         DspinDhccpParam::dspin_set(
    7561             flit,
    7562             1ULL,
    7563             DspinDhccpParam::FROM_MC_EOP);
    75647521
    75657522        DspinDhccpParam::dspin_set(
     
    75697526
    75707527        p_dspin_out.write = true;
     7528        p_dspin_out.eop   = true;
    75717529        p_dspin_out.data  = flit;
    75727530
    75737531        break;
    75747532      }
    7575 
     7533    /////////////////////////////////
    75767534    case CC_SEND_WRITE_BRDCAST_NLINE:
    75777535      {
    75787536        uint64_t flit = 0;
    7579 
    7580         DspinDhccpParam::dspin_set(
    7581             flit,
    7582             1ULL,
    7583             DspinDhccpParam::FROM_MC_EOP);
    75847537
    75857538        DspinDhccpParam::dspin_set(
     
    75897542
    75907543        p_dspin_out.write = true;
     7544        p_dspin_out.eop   = true;
    75917545        p_dspin_out.data  = flit;
    75927546
    75937547        break;
    75947548      }
    7595 
     7549    ///////////////////////////////
    75967550    case CC_SEND_CAS_BRDCAST_NLINE:
    75977551      {
    75987552        uint64_t flit = 0;
    7599 
    7600         DspinDhccpParam::dspin_set(
    7601             flit,
    7602             1ULL,
    7603             DspinDhccpParam::FROM_MC_EOP);
    76047553
    76057554        DspinDhccpParam::dspin_set(
     
    76097558
    76107559        p_dspin_out.write = true;
     7560        p_dspin_out.eop   = true;
    76117561        p_dspin_out.data  = flit;
    76127562
    76137563        break;
    76147564      }
    7615 
     7565    ///////////////////////////////
    76167566    case CC_SEND_WRITE_UPDT_HEADER:
    76177567      {
     
    76587608        break;
    76597609      }
    7660 
     7610    //////////////////////////////
    76617611    case CC_SEND_WRITE_UPDT_NLINE:
    76627612      {
     
    76787628        break;
    76797629      }
    7680 
     7630    /////////////////////////////
    76817631    case CC_SEND_WRITE_UPDT_DATA:
    76827632      {
    7683         uint8_t multi_updt_eop;
    7684         if(  r_cc_send_cpt.read() ==
    7685             (r_write_to_cc_send_count.read()-1))
    7686         {
    7687           multi_updt_eop = 1;
    7688         }
    7689         else
    7690         {
    7691           multi_updt_eop = 0;
    7692         }
    76937633
    76947634        uint8_t multi_updt_cpt  =
     
    76997639
    77007640        uint64_t flit = 0;
    7701 
    7702         DspinDhccpParam::dspin_set(
    7703             flit,
    7704             (uint64_t)multi_updt_eop,
    7705             DspinDhccpParam::FROM_MC_EOP);
    77067641
    77077642        DspinDhccpParam::dspin_set(
     
    77167651
    77177652        p_dspin_out.write = true;
     7653        p_dspin_out.eop   = (r_cc_send_cpt.read() == (r_write_to_cc_send_count.read()-1));
    77187654        p_dspin_out.data  = flit;
    77197655
    77207656        break;
    77217657      }
    7722 
     7658    ////////////////////////////
    77237659    case CC_SEND_CAS_UPDT_HEADER:
    77247660      {
     
    77657701        break;
    77667702      }
    7767 
     7703    ////////////////////////////
    77687704    case CC_SEND_CAS_UPDT_NLINE:
    77697705      {
     
    77857721        break;
    77867722      }
    7787 
     7723    ///////////////////////////
    77887724    case CC_SEND_CAS_UPDT_DATA:
    77897725      {
    7790         uint8_t multi_updt_eop;
    7791         if(not r_cas_to_cc_send_is_long.read())
    7792         {
    7793           multi_updt_eop = 1;
    7794         }
    7795         else
    7796         {
    7797           multi_updt_eop = 0;
    7798         }
    7799 
    78007726        uint64_t flit = 0;
    7801 
    7802         DspinDhccpParam::dspin_set(
    7803             flit,
    7804             (uint64_t)multi_updt_eop,
    7805             DspinDhccpParam::FROM_MC_EOP);
    78067727
    78077728        DspinDhccpParam::dspin_set(
     
    78167737
    78177738        p_dspin_out.write = true;
     7739        p_dspin_out.eop   = not r_cas_to_cc_send_is_long.read();
    78187740        p_dspin_out.data  = flit;
    78197741
    78207742        break;
    78217743      }
    7822 
     7744    ////////////////////////////////
    78237745    case CC_SEND_CAS_UPDT_DATA_HIGH:
    78247746      {
    78257747        uint64_t flit = 0;
    7826 
    7827         DspinDhccpParam::dspin_set(
    7828             flit,
    7829             1ULL,
    7830             DspinDhccpParam::FROM_MC_EOP);
    78317748
    78327749        DspinDhccpParam::dspin_set(
     
    78417758
    78427759        p_dspin_out.write = true;
     7760        p_dspin_out.eop   = true;
    78437761        p_dspin_out.data  = flit;
    78447762
     
    78487766
    78497767  ///////////////////////////////////////////////////////////////////
    7850   // Target command signals from the p_dspin_in port (CC_RECEIVE FSM)
     7768  // p_dspin_in port (CC_RECEIVE FSM)
    78517769  ///////////////////////////////////////////////////////////////////
    78527770  p_dspin_in.read = false;
     
    78587776      }
    78597777    case CC_RECEIVE_CLEANUP:
     7778    case CC_RECEIVE_CLEANUP_EOP:
    78607779      {
    78617780        p_dspin_in.read = m_cc_receive_to_cleanup_fifo.wok();
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