Changeset 428 for trunk/platforms
- Timestamp:
- Jul 1, 2013, 9:51:00 AM (11 years ago)
- Location:
- trunk/platforms/tsar_generic_xbar
- Files:
-
- 5 edited
-
top.cpp (modified) (7 diffs)
-
top.desc (modified) (1 diff)
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tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd (modified) (1 diff)
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tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h (modified) (7 diffs)
-
tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp (modified) (21 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/platforms/tsar_generic_xbar/top.cpp
r404 r428 241 241 #define FBUF_TGTID 4 242 242 #define BDEV_TGTID 5 243 #define MNIC_TGTID 6244 #define BROM_TGTID 7243 #define BROM_TGTID 6 244 #define MNIC_TGTID 7 245 245 246 246 ///////////////////////////////// … … 250 250 using namespace soclib::caba; 251 251 using namespace soclib::common; 252 253 252 254 253 char soft_name[256] = SOFT_NAME; // pathname to binary code … … 386 385 int_vci_wrplen_width> vci_param_int; 387 386 388 typedef soclib::caba::VciParams Bis<ext_vci_cell_width,389 390 391 392 393 394 395 396 397 387 typedef soclib::caba::VciParams<ext_vci_cell_width, 388 ext_vci_plen_width, 389 ext_vci_address_width, 390 ext_vci_rerror_width, 391 ext_vci_clen_width, 392 ext_vci_rflag_width, 393 ext_vci_srcid_width, 394 ext_vci_pktid_width, 395 ext_vci_trdid_width, 396 ext_vci_wrplen_width> vci_param_ext; 398 397 399 398 #if USE_OPENMP … … 499 498 sc_clock signal_clk("clk"); 500 499 sc_signal<bool> signal_resetn("resetn"); 500 501 enum { 502 NORTH = VirtualDspinRouter<dspin_cmd_width>::NORTH, 503 SOUTH = VirtualDspinRouter<dspin_cmd_width>::SOUTH, 504 EAST = VirtualDspinRouter<dspin_cmd_width>::EAST, 505 WEST = VirtualDspinRouter<dspin_cmd_width>::WEST, 506 LOCAL = VirtualDspinRouter<dspin_cmd_width>::LOCAL 507 }; 501 508 502 509 // Horizontal inter-clusters DSPIN signals … … 649 656 for (size_t y = 0; y < CLUSTER_Y; y++){ 650 657 for (size_t k = 0; k < 2; k++){ 651 clusters[x][y]->p_cmd_out[k][EAST] 652 clusters[x+1][y]->p_cmd_in[k][WEST] 653 clusters[x][y]->p_cmd_in[k][EAST] 654 clusters[x+1][y]->p_cmd_out[k][WEST] 655 clusters[x][y]->p_rsp_out[k][EAST] 656 clusters[x+1][y]->p_rsp_in[k][WEST] 657 clusters[x][y]->p_rsp_in[k][EAST] 658 clusters[x+1][y]->p_rsp_out[k][WEST] 658 clusters[x][y]->p_cmd_out[k][EAST] (signal_dspin_h_cmd_inc[x][y][k]); 659 clusters[x+1][y]->p_cmd_in[k][WEST] (signal_dspin_h_cmd_inc[x][y][k]); 660 clusters[x][y]->p_cmd_in[k][EAST] (signal_dspin_h_cmd_dec[x][y][k]); 661 clusters[x+1][y]->p_cmd_out[k][WEST] (signal_dspin_h_cmd_dec[x][y][k]); 662 clusters[x][y]->p_rsp_out[k][EAST] (signal_dspin_h_rsp_inc[x][y][k]); 663 clusters[x+1][y]->p_rsp_in[k][WEST] (signal_dspin_h_rsp_inc[x][y][k]); 664 clusters[x][y]->p_rsp_in[k][EAST] (signal_dspin_h_rsp_dec[x][y][k]); 665 clusters[x+1][y]->p_rsp_out[k][WEST] (signal_dspin_h_rsp_dec[x][y][k]); 659 666 } 660 667 } … … 668 675 for (size_t x = 0; x < CLUSTER_X; x++){ 669 676 for (size_t k = 0; k < 2; k++){ 670 clusters[x][y]->p_cmd_out[k][NORTH] 671 clusters[x][y+1]->p_cmd_in[k][SOUTH] 672 clusters[x][y]->p_cmd_in[k][NORTH] 673 clusters[x][y+1]->p_cmd_out[k][SOUTH] 674 clusters[x][y]->p_rsp_out[k][NORTH] 675 clusters[x][y+1]->p_rsp_in[k][SOUTH] 676 clusters[x][y]->p_rsp_in[k][NORTH] 677 clusters[x][y+1]->p_rsp_out[k][SOUTH] 677 clusters[x][y]->p_cmd_out[k][NORTH] (signal_dspin_v_cmd_inc[x][y][k]); 678 clusters[x][y+1]->p_cmd_in[k][SOUTH] (signal_dspin_v_cmd_inc[x][y][k]); 679 clusters[x][y]->p_cmd_in[k][NORTH] (signal_dspin_v_cmd_dec[x][y][k]); 680 clusters[x][y+1]->p_cmd_out[k][SOUTH] (signal_dspin_v_cmd_dec[x][y][k]); 681 clusters[x][y]->p_rsp_out[k][NORTH] (signal_dspin_v_rsp_inc[x][y][k]); 682 clusters[x][y+1]->p_rsp_in[k][SOUTH] (signal_dspin_v_rsp_inc[x][y][k]); 683 clusters[x][y]->p_rsp_in[k][NORTH] (signal_dspin_v_rsp_dec[x][y][k]); 684 clusters[x][y+1]->p_rsp_out[k][SOUTH] (signal_dspin_v_rsp_dec[x][y][k]); 678 685 } 679 686 } … … 687 694 for (size_t k = 0; k < 2; k++) 688 695 { 689 clusters[0][y]->p_cmd_in[k][WEST] 690 clusters[0][y]->p_cmd_out[k][WEST] 691 clusters[0][y]->p_rsp_in[k][WEST] 692 clusters[0][y]->p_rsp_out[k][WEST] 693 694 clusters[CLUSTER_X-1][y]->p_cmd_in[k][EAST] 695 clusters[CLUSTER_X-1][y]->p_cmd_out[k][EAST] 696 clusters[CLUSTER_X-1][y]->p_rsp_in[k][EAST] 697 clusters[CLUSTER_X-1][y]->p_rsp_out[k][EAST] 696 clusters[0][y]->p_cmd_in[k][WEST] (signal_dspin_false_cmd_in[0][y][k][WEST]); 697 clusters[0][y]->p_cmd_out[k][WEST] (signal_dspin_false_cmd_out[0][y][k][WEST]); 698 clusters[0][y]->p_rsp_in[k][WEST] (signal_dspin_false_rsp_in[0][y][k][WEST]); 699 clusters[0][y]->p_rsp_out[k][WEST] (signal_dspin_false_rsp_out[0][y][k][WEST]); 700 701 clusters[CLUSTER_X-1][y]->p_cmd_in[k][EAST] (signal_dspin_false_cmd_in[CLUSTER_X-1][y][k][EAST]); 702 clusters[CLUSTER_X-1][y]->p_cmd_out[k][EAST] (signal_dspin_false_cmd_out[CLUSTER_X-1][y][k][EAST]); 703 clusters[CLUSTER_X-1][y]->p_rsp_in[k][EAST] (signal_dspin_false_rsp_in[CLUSTER_X-1][y][k][EAST]); 704 clusters[CLUSTER_X-1][y]->p_rsp_out[k][EAST] (signal_dspin_false_rsp_out[CLUSTER_X-1][y][k][EAST]); 698 705 } 699 706 } -
trunk/platforms/tsar_generic_xbar/top.desc
r404 r428 31 31 32 32 todo = Platform('caba', 'top.cpp', 33 uses = [ 34 Uses('caba:tsar_xbar_cluster', 35 dspin_cmd_width = dspin_cmd_flit_size, 36 dspin_rsp_width = dspin_rsp_flit_size, 33 37 34 uses = [ 35 Uses('caba:tsar_xbar_cluster', 36 dspin_cmd_width = dspin_cmd_flit_size, 37 dspin_rsp_width = dspin_rsp_flit_size, 38 vci_param_int = 'caba:vci_param', 38 39 39 vci_param_int = 'caba:vci_param', 40 cell_size = int_vci_cell_size, 41 plen_size = int_vci_plen_size, 42 addr_size = int_vci_addr_size, 43 rerror_size = int_vci_rerror_size, 44 clen_size = int_vci_clen_size, 45 rflag_size = int_vci_rflag_size, 46 srcid_size = int_vci_srcid_size, 47 pktid_size = int_vci_pktid_size, 48 trdid_size = int_vci_trdid_size, 49 wrplen_size = int_vci_wrplen_size, 40 50 41 cell_size = int_vci_cell_size, 42 plen_size = int_vci_plen_size, 43 addr_size = int_vci_addr_size, 44 rerror_size = int_vci_rerror_size, 45 clen_size = int_vci_clen_size, 46 rflag_size = int_vci_rflag_size, 47 srcid_size = int_vci_srcid_size, 48 pktid_size = int_vci_pktid_size, 49 trdid_size = int_vci_trdid_size, 50 wrplen_size = int_vci_wrplen_size, 51 vci_param_ext = 'caba:vci_param', 51 52 52 vci_param_ext = 'caba:vci_param_bis', 53 cell_size_ext = ext_vci_cell_size, 54 ), 53 55 54 cell_size_bis = ext_vci_cell_size, 55 plen_size_bis = ext_vci_plen_size, 56 addr_size_bis = ext_vci_addr_size, 57 rerror_size_bis = ext_vci_rerror_size, 58 clen_size_bis = ext_vci_clen_size, 59 rflag_size_bis = ext_vci_rflag_size, 60 srcid_size_bis = ext_vci_srcid_size, 61 pktid_size_bis = ext_vci_pktid_size, 62 trdid_size_bis = ext_vci_trdid_size, 63 wrplen_size_bis = ext_vci_wrplen_size), 56 Uses('common:elf_file_loader'), 57 Uses('common:plain_file_loader'), 58 ], 59 ) 64 60 65 Uses('common:elf_file_loader'),66 Uses('common:plain_file_loader'),67 ],68 ) -
trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd
r396 r428 2 2 # -*- python -*- 3 3 4 Module('caba:tsar_xbar_cluster', 4 Module('caba:tsar_xbar_cluster', 5 5 classname = 'soclib::caba::TsarXbarCluster', 6 tmpl_parameters = [ 7 parameter.Int('dspin_cmd_width'), 8 parameter.Int('dspin_rsp_width'), 6 7 tmpl_parameters = [ 8 parameter.Int('dspin_cmd_width'), 9 parameter.Int('dspin_rsp_width'), 9 10 parameter.Module('vci_param_int'), 10 parameter.Module('vci_param_ext'), 11 ], 11 parameter.Module('vci_param_ext', 12 cell_size = parameter.Reference('cell_size_ext') 13 ), 14 ], 12 15 13 header_files = [ '../source/include/tsar_xbar_cluster.h', ], 14 implementation_files = [ '../source/src/tsar_xbar_cluster.cpp', ], 16 header_files = [ '../source/include/tsar_xbar_cluster.h', ], 15 17 16 uses = [ 17 Uses('caba:base_module'), 18 Uses('common:mapping_table'), 19 Uses('common:iss2'), 20 21 Uses('caba:vci_cc_vcache_wrapper', 22 vci_param = parameter.Reference('vci_param_int'), 23 dspin_in_width = parameter.Reference('dspin_cmd_width'), 24 dspin_out_width = parameter.Reference('dspin_rsp_width'), 25 iss_t = 'common:gdb_iss', 26 gdb_iss_t = 'common:mips32el'), 18 implementation_files = [ '../source/src/tsar_xbar_cluster.cpp', ], 27 19 28 Uses('caba:vci_simple_ram', 29 vci_param = parameter.Reference('vci_param_int')), 20 uses = [ 21 Uses('caba:base_module'), 22 Uses('common:mapping_table'), 23 Uses('common:iss2'), 30 24 31 Uses('caba:vci_simple_ram', 32 vci_param = parameter.Reference('vci_param_ext')), 25 Uses('caba:vci_cc_vcache_wrapper', 26 vci_param = parameter.Reference('vci_param_int'), 27 dspin_in_width = parameter.Reference('dspin_cmd_width'), 28 dspin_out_width = parameter.Reference('dspin_rsp_width'), 29 iss_t = 'common:gdb_iss', 30 gdb_iss_t = 'common:mips32el' 31 ), 32 Uses('caba:vci_simple_ram', 33 vci_param = parameter.Reference('vci_param_int') 34 ), 35 Uses('caba:vci_simple_ram', 36 vci_param = parameter.Reference('vci_param_ext'), 37 cell_size = parameter.Reference('cell_size_ext'), 38 ), 39 Uses('caba:vci_xicu', 40 vci_param = parameter.Reference('vci_param_int') 41 ), 42 Uses('caba:dspin_local_crossbar', 43 flit_width = parameter.Reference('dspin_cmd_width') 44 ), 45 Uses('caba:dspin_local_crossbar', 46 flit_width = parameter.Reference('dspin_rsp_width') 47 ), 48 Uses('caba:virtual_dspin_router', 49 flit_width = parameter.Reference('dspin_cmd_width') 50 ), 51 Uses('caba:virtual_dspin_router', 52 flit_width = parameter.Reference('dspin_rsp_width') 53 ), 54 Uses('caba:vci_multi_tty', 55 vci_param = parameter.Reference('vci_param_int') 56 ), 57 Uses('caba:vci_framebuffer', 58 vci_param = parameter.Reference('vci_param_int') 59 ), 60 Uses('caba:vci_multi_nic', 61 vci_param = parameter.Reference('vci_param_int') 62 ), 63 Uses('caba:vci_block_device_tsar', 64 vci_param = parameter.Reference('vci_param_int') 65 ), 66 Uses('caba:vci_multi_dma', 67 vci_param = parameter.Reference('vci_param_int') 68 ), 69 Uses('caba:vci_dspin_target_wrapper', 70 vci_param = parameter.Reference('vci_param_int') 71 ), 72 Uses('caba:vci_dspin_initiator_wrapper', 73 vci_param = parameter.Reference('vci_param_int') 74 ), 75 Uses('caba:vci_mem_cache', 76 dspin_in_width = parameter.Reference('dspin_rsp_width'), 77 dspin_out_width = parameter.Reference('dspin_cmd_width'), 78 memc_cell_size_int = parameter.Reference('cell_size'), 79 memc_cell_size_ext = parameter.Reference('cell_size_ext') 80 ), 33 81 34 Uses('c aba:vci_xicu',35 vci_param = parameter.Reference('vci_param_int')),82 Uses('common:elf_file_loader'), 83 ], 36 84 37 Uses('caba:dspin_local_crossbar', 38 flit_width = parameter.Reference('dspin_cmd_width')), 85 ports = [ 86 Port('caba:bit_in', 'p_resetn', auto = 'resetn'), 87 Port('caba:clock_in', 'p_clk', auto = 'clock'), 39 88 40 Uses('caba:dspin_local_crossbar', 41 flit_width = parameter.Reference('dspin_rsp_width')), 42 43 Uses('caba:virtual_dspin_router', 44 flit_width = parameter.Reference('dspin_cmd_width')), 45 46 Uses('caba:virtual_dspin_router', 47 flit_width = parameter.Reference('dspin_rsp_width')), 48 49 Uses('caba:vci_multi_tty', 50 vci_param = parameter.Reference('vci_param_int')), 51 52 Uses('caba:vci_framebuffer', 53 vci_param = parameter.Reference('vci_param_int')), 54 55 Uses('caba:vci_multi_nic', 56 vci_param = parameter.Reference('vci_param_int')), 57 58 Uses('caba:vci_block_device_tsar', 59 vci_param = parameter.Reference('vci_param_int')), 60 61 Uses('caba:vci_multi_dma', 62 vci_param = parameter.Reference('vci_param_int')), 63 64 Uses('caba:vci_dspin_target_wrapper', 65 vci_param = parameter.Reference('vci_param_int')), 66 67 Uses('caba:vci_dspin_initiator_wrapper', 68 vci_param = parameter.Reference('vci_param_int')), 69 70 Uses('caba:vci_mem_cache', 71 vci_param_int = 'caba:vci_param', 72 vci_param_ext = 'caba:vci_param_bis', 73 dspin_in_width = parameter.Reference('dspin_rsp_width'), 74 dspin_out_width = parameter.Reference('dspin_cmd_width')), 75 76 Uses('common:elf_file_loader'), 77 ], 78 79 ports = [ 80 Port('caba:bit_in', 'p_resetn', auto = 'resetn'), 81 Port('caba:clock_in', 'p_clk', auto = 'clock'), 82 Port('caba:dspin_output', 'p_cmd_out', [2, 4], 83 dspin_data_size = parameter.Reference('dspin_cmd_width')), 84 Port('caba:dspin_input', 'p_cmd_in', [2, 4], 85 dspin_data_size = parameter.Reference('dspin_cmd_width')), 86 Port('caba:dspin_output', 'p_rsp_out', [2, 4], 87 dspin_data_size = parameter.Reference('dspin_rsp_width')), 88 Port('caba:dspin_input', 'p_rsp_in', [2, 4], 89 dspin_data_size = parameter.Reference('dspin_rsp_width')), 90 ], 89 Port('caba:dspin_output', 'p_cmd_out', [2, 4], 90 dspin_data_size = parameter.Reference('dspin_cmd_width') 91 ), 92 Port('caba:dspin_input', 'p_cmd_in', [2, 4], 93 dspin_data_size = parameter.Reference('dspin_cmd_width') 94 ), 95 Port('caba:dspin_output', 'p_rsp_out', [2, 4], 96 dspin_data_size = parameter.Reference('dspin_rsp_width') 97 ), 98 Port('caba:dspin_input', 'p_rsp_in', [2, 4], 99 dspin_data_size = parameter.Reference('dspin_rsp_width') 100 ), 101 ], 91 102 ) 92 103 93 -
trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h
r396 r428 1 1 ////////////////////////////////////////////////////////////////////////////// 2 2 // File: tsar_xbar_cluster.h 3 // Author: Alain Greiner 3 // Author: Alain Greiner 4 4 // Copyright: UPMC/LIP6 5 5 // Date : march 2013 … … 38 38 /////////////////////////////////////////////////////////////////////////// 39 39 template<size_t dspin_cmd_width, 40 size_t dspin_rsp_width, 40 size_t dspin_rsp_width, 41 41 typename vci_param_int, 42 typename vci_param_ext> class TsarXbarCluster 42 typename vci_param_ext> class TsarXbarCluster 43 43 /////////////////////////////////////////////////////////////////////////// 44 44 : public soclib::caba::BaseModule … … 46 46 public: 47 47 48 49 sc_in<bool> 50 sc_in<bool> 51 soclib::caba::DspinOutput<dspin_cmd_width>**p_cmd_out;52 soclib::caba::DspinInput<dspin_cmd_width>**p_cmd_in;53 soclib::caba::DspinOutput<dspin_rsp_width> 54 soclib::caba::DspinInput<dspin_rsp_width> 48 // Ports 49 sc_in<bool> p_clk; 50 sc_in<bool> p_resetn; 51 soclib::caba::DspinOutput<dspin_cmd_width> **p_cmd_out; 52 soclib::caba::DspinInput<dspin_cmd_width> **p_cmd_in; 53 soclib::caba::DspinOutput<dspin_rsp_width> **p_rsp_out; 54 soclib::caba::DspinInput<dspin_rsp_width> **p_rsp_in; 55 55 56 56 // interrupt signals 57 sc_signal<bool>signal_false;58 sc_signal<bool>signal_proc_it[8];59 sc_signal<bool>signal_irq_mdma[8];60 sc_signal<bool>signal_irq_mtty[23];61 sc_signal<bool> signal_irq_mnic_rx[8];// unused62 sc_signal<bool> signal_irq_mnic_tx[8];// unused63 sc_signal<bool>signal_irq_bdev;64 65 66 DspinSignals<dspin_cmd_width> signal_dspin_cmd_l2g_d; 67 DspinSignals<dspin_cmd_width> signal_dspin_cmd_g2l_d; 68 DspinSignals<dspin_cmd_width>signal_dspin_m2p_l2g_c;69 DspinSignals<dspin_cmd_width> signal_dspin_m2p_g2l_c; 70 DspinSignals<dspin_rsp_width> signal_dspin_rsp_l2g_d; 71 DspinSignals<dspin_rsp_width> signal_dspin_rsp_g2l_d; 72 DspinSignals<dspin_rsp_width>signal_dspin_p2m_l2g_c;73 DspinSignals<dspin_rsp_width>signal_dspin_p2m_g2l_c;74 75 76 VciSignals<vci_param_int> signal_vci_ini_proc[8]; 77 VciSignals<vci_param_int> signal_vci_ini_mdma; 78 VciSignals<vci_param_int> signal_vci_ini_bdev; 79 80 VciSignals<vci_param_int>signal_vci_tgt_memc;81 VciSignals<vci_param_int>signal_vci_tgt_xicu;82 VciSignals<vci_param_int>signal_vci_tgt_mdma;83 VciSignals<vci_param_int>signal_vci_tgt_mtty;84 VciSignals<vci_param_int>signal_vci_tgt_bdev;85 VciSignals<vci_param_int>signal_vci_tgt_brom;86 VciSignals<vci_param_int>signal_vci_tgt_fbuf;87 VciSignals<vci_param_int>signal_vci_tgt_mnic;88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 57 sc_signal<bool> signal_false; 58 sc_signal<bool> signal_proc_it[8]; 59 sc_signal<bool> signal_irq_mdma[8]; 60 sc_signal<bool> signal_irq_mtty[23]; 61 sc_signal<bool> signal_irq_mnic_rx[8]; // unused 62 sc_signal<bool> signal_irq_mnic_tx[8]; // unused 63 sc_signal<bool> signal_irq_bdev; 64 65 // DSPIN signals between DSPIN routers and local_crossbars 66 DspinSignals<dspin_cmd_width> signal_dspin_cmd_l2g_d; 67 DspinSignals<dspin_cmd_width> signal_dspin_cmd_g2l_d; 68 DspinSignals<dspin_cmd_width> signal_dspin_m2p_l2g_c; 69 DspinSignals<dspin_cmd_width> signal_dspin_m2p_g2l_c; 70 DspinSignals<dspin_rsp_width> signal_dspin_rsp_l2g_d; 71 DspinSignals<dspin_rsp_width> signal_dspin_rsp_g2l_d; 72 DspinSignals<dspin_rsp_width> signal_dspin_p2m_l2g_c; 73 DspinSignals<dspin_rsp_width> signal_dspin_p2m_g2l_c; 74 75 // Direct VCI signals to VCI/DSPIN wrappers 76 VciSignals<vci_param_int> signal_vci_ini_proc[8]; 77 VciSignals<vci_param_int> signal_vci_ini_mdma; 78 VciSignals<vci_param_int> signal_vci_ini_bdev; 79 80 VciSignals<vci_param_int> signal_vci_tgt_memc; 81 VciSignals<vci_param_int> signal_vci_tgt_xicu; 82 VciSignals<vci_param_int> signal_vci_tgt_mdma; 83 VciSignals<vci_param_int> signal_vci_tgt_mtty; 84 VciSignals<vci_param_int> signal_vci_tgt_bdev; 85 VciSignals<vci_param_int> signal_vci_tgt_brom; 86 VciSignals<vci_param_int> signal_vci_tgt_fbuf; 87 VciSignals<vci_param_int> signal_vci_tgt_mnic; 88 89 // Direct DSPIN signals to local crossbars 90 DspinSignals<dspin_cmd_width> signal_dspin_cmd_proc_i[8]; 91 DspinSignals<dspin_rsp_width> signal_dspin_rsp_proc_i[8]; 92 DspinSignals<dspin_cmd_width> signal_dspin_cmd_mdma_i; 93 DspinSignals<dspin_rsp_width> signal_dspin_rsp_mdma_i; 94 DspinSignals<dspin_cmd_width> signal_dspin_cmd_bdev_i; 95 DspinSignals<dspin_rsp_width> signal_dspin_rsp_bdev_i; 96 97 DspinSignals<dspin_cmd_width> signal_dspin_cmd_memc_t; 98 DspinSignals<dspin_rsp_width> signal_dspin_rsp_memc_t; 99 DspinSignals<dspin_cmd_width> signal_dspin_cmd_xicu_t; 100 DspinSignals<dspin_rsp_width> signal_dspin_rsp_xicu_t; 101 DspinSignals<dspin_cmd_width> signal_dspin_cmd_mdma_t; 102 DspinSignals<dspin_rsp_width> signal_dspin_rsp_mdma_t; 103 DspinSignals<dspin_cmd_width> signal_dspin_cmd_mtty_t; 104 DspinSignals<dspin_rsp_width> signal_dspin_rsp_mtty_t; 105 DspinSignals<dspin_cmd_width> signal_dspin_cmd_bdev_t; 106 DspinSignals<dspin_rsp_width> signal_dspin_rsp_bdev_t; 107 DspinSignals<dspin_cmd_width> signal_dspin_cmd_brom_t; 108 DspinSignals<dspin_rsp_width> signal_dspin_rsp_brom_t; 109 DspinSignals<dspin_cmd_width> signal_dspin_cmd_fbuf_t; 110 DspinSignals<dspin_rsp_width> signal_dspin_rsp_fbuf_t; 111 DspinSignals<dspin_cmd_width> signal_dspin_cmd_mnic_t; 112 DspinSignals<dspin_rsp_width> signal_dspin_rsp_mnic_t; 113 114 // Coherence DSPIN signals to local crossbar 115 DspinSignals<dspin_cmd_width> signal_dspin_m2p_memc; 116 DspinSignals<dspin_rsp_width> signal_dspin_p2m_memc; 117 DspinSignals<dspin_cmd_width> signal_dspin_m2p_proc[8]; 118 DspinSignals<dspin_rsp_width> signal_dspin_p2m_proc[8]; 119 120 // external RAM to MEMC VCI signal 121 VciSignals<vci_param_ext> signal_vci_xram; 122 123 123 // Components 124 124 125 VciCcVCacheWrapper<vci_param_int, 125 VciCcVCacheWrapper<vci_param_int, 126 126 dspin_cmd_width, 127 127 dspin_rsp_width, … … 132 132 dspin_rsp_width>* wi_proc[8]; 133 133 134 VciMemCache<vci_param_int, 135 vci_param_ext, 136 dspin_rsp_width, 134 VciMemCache<vci_param_int, 135 vci_param_ext, 136 dspin_rsp_width, 137 137 dspin_cmd_width>* memc; 138 138 … … 201 201 VirtualDspinRouter<dspin_rsp_width>* router_rsp; 202 202 203 204 size_t nb_procs, // processors 205 size_t nb_ttys, // TTY terminals 206 size_t nb_dmas, // DMA channels 203 TsarXbarCluster( sc_module_name insname, 204 size_t nb_procs, // processors 205 size_t nb_ttys, // TTY terminals 206 size_t nb_dmas, // DMA channels 207 207 size_t x, // x coordinate 208 208 size_t y, // y coordinate … … 210 210 const soclib::common::MappingTable &mtd, // internal 211 211 const soclib::common::MappingTable &mtx, // external 212 size_t 213 size_t 214 size_t 215 size_t 216 size_t 212 size_t x_width, // x field bits 213 size_t y_width, // y field bits 214 size_t l_width, // l field bits 215 size_t tgtid_memc, 216 size_t tgtid_xicu, 217 217 size_t tgtid_mdma, 218 218 size_t tgtid_fbuf, … … 224 224 size_t memc_sets, 225 225 size_t l1_i_ways, 226 size_t l1_i_sets, 226 size_t l1_i_sets, 227 227 size_t l1_d_ways, 228 size_t l1_d_sets, 229 size_t xram_latency, // external ram 230 bool io, 228 size_t l1_d_sets, 229 size_t xram_latency, // external ram 230 bool io, // I/O cluster 231 231 size_t xfb, // fbf pixels 232 232 size_t yfb, // fbf lines 233 char* disk_name, // virtual disk 234 size_t block_size, // block size 233 char* disk_name, // virtual disk 234 size_t block_size, // block size 235 235 size_t nic_channels, // number channels 236 char* nic_rx_name, // filename rx 237 char* nic_tx_name, // filename tx 238 uint32_t 239 const Loader &loader, 240 uint32_t frozen_cycles, 236 char* nic_rx_name, // filename rx 237 char* nic_tx_name, // filename tx 238 uint32_t nic_timeout, // cycles 239 const Loader &loader, 240 uint32_t frozen_cycles, 241 241 uint32_t start_debug_cycle, 242 bool memc_debug_ok, 243 bool proc_debug_ok); 242 bool memc_debug_ok, 243 bool proc_debug_ok); 244 244 245 245 }; -
trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp
r396 r428 1 1 ////////////////////////////////////////////////////////////////////////////// 2 2 // File: tsar_xbar_cluster.cpp 3 // Author: Alain Greiner 3 // Author: Alain Greiner 4 4 // Copyright: UPMC/LIP6 5 5 // Date : march 2011 … … 7 7 ////////////////////////////////////////////////////////////////////////////// 8 8 // This file define a TSAR cluster architecture with virtual memory: 9 // - It uses two virtual_dspin_router as distributed global interconnect 10 // - It uses four dspin_local_crossbar as local interconnect 9 // - It uses two virtual_dspin_router as distributed global interconnect 10 // - It uses four dspin_local_crossbar as local interconnect 11 11 // - It uses the vci_cc_vcache_wrapper 12 12 // - It uses the vci_mem_cache … … 16 16 // - It uses the vci_xicu interrupt controller 17 17 // - The peripherals MTTY, BDEV, FBUF, MNIC and BROM are in cluster (0,0) 18 // - The Multi-TTY component controls up to 15 terminals. 18 // - The Multi-TTY component controls up to 15 terminals. 19 19 // - Each Multi-DMA component controls up to 8 DMA channels. 20 20 // - The DMA IRQs are connected to IRQ_IN[8]...IRQ_IN[15] 21 21 // - The TTY IRQs are connected to IRQ_IN[16]...IRQ_IN[30] 22 22 // - The BDEV IRQ is connected to IRQ_IN[31] 23 ////////////////////////////////////////////////////////////////////////////////// 23 ////////////////////////////////////////////////////////////////////////////////// 24 24 25 25 #include "../include/tsar_xbar_cluster.h" … … 30 30 31 31 //////////////////////////////////////////////////////////////////////////////////// 32 template<size_t dspin_cmd_width, 32 template<size_t dspin_cmd_width, 33 33 size_t dspin_rsp_width, 34 34 typename vci_param_int, … … 46 46 size_t cluster_id, 47 47 const soclib::common::MappingTable &mtd, 48 const soclib::common::MappingTable &mtx, 48 const soclib::common::MappingTable &mtx, 49 49 size_t x_width, 50 50 size_t y_width, … … 91 91 92 92 ///////////////////////////////////////////////////////////////////////////// 93 // Components definition 93 // Components definition 94 94 ///////////////////////////////////////////////////////////////////////////// 95 95 std::cout << " - building proc_" << x_id << "_" << y_id << "-*" << std::endl; 96 96 97 97 for (size_t p = 0; p < nb_procs; p++) 98 { 98 { 99 99 std::ostringstream sproc; 100 100 sproc << "proc_" << x_id << "_" << y_id << "_" << p; 101 101 proc[p] = new VciCcVCacheWrapper<vci_param_int, 102 102 dspin_cmd_width, 103 dspin_rsp_width, 103 dspin_rsp_width, 104 104 GdbServer<Mips32ElIss> >( 105 105 sproc.str().c_str(), 106 106 cluster_id*nb_procs + p, // GLOBAL PROC_ID 107 mtd, // Mapping Table 107 mtd, // Mapping Table 108 108 IntTab(cluster_id,p), // SRCID 109 109 (cluster_id << l_width) + p, // CC_GLOBAL_ID … … 234 234 x_width, y_width, l_width, 235 235 nb_direct_initiators, // number of local of sources 236 nb_direct_targets, // number of local dests 237 2, 2, // fifo depths 238 true, // use local routing table 236 nb_direct_targets, // number of local dests 237 2, 2, // fifo depths 238 true, // use local routing table 239 239 false ); // no broacast 240 240 … … 247 247 x_id, y_id, // cluster coordinates 248 248 x_width, y_width, l_width, 249 nb_direct_targets, // number of local sources 249 nb_direct_targets, // number of local sources 250 250 nb_direct_initiators, // number of local dests 251 2, 2, // fifo depths 252 false, // don't use local routing table 251 2, 2, // fifo depths 252 false, // don't use local routing table 253 253 false ); // no broacast 254 254 … … 262 262 x_width, y_width, l_width, 263 263 1, // number of local sources 264 nb_procs, // number of local targets 265 2, 2, // fifo depths 264 nb_procs, // number of local targets 265 2, 2, // fifo depths 266 266 false, // don't use local routing table 267 267 true ); // broacast … … 277 277 nb_procs, // number of local sources 278 278 1, // number of local dests 279 2, 2, // fifo depths 279 2, 2, // fifo depths 280 280 false, // don't use local routing table 281 false ); // no broacast 281 false ); // no broacast 282 282 283 283 ///////////////////////////////////////////////////////////////////////////// … … 324 324 IntTab(cluster_id, tgtid_fbuf), 325 325 mtd, 326 xfb, yfb); 326 xfb, yfb); 327 327 328 328 wt_fbuf = new VciDspinTargetWrapper<vci_param_int, … … 388 388 "mtty", 389 389 IntTab(cluster_id, tgtid_mtty), 390 mtd, 390 mtd, 391 391 vect_names); 392 392 … … 494 494 xbar_m2p_c->p_global_in (signal_dspin_m2p_g2l_c); 495 495 xbar_m2p_c->p_local_in[0] (signal_dspin_m2p_memc); 496 for (size_t p = 0; p < nb_procs; p++) 496 for (size_t p = 0; p < nb_procs; p++) 497 497 xbar_m2p_c->p_local_out[p] (signal_dspin_m2p_proc[p]); 498 498 … … 505 505 xbar_p2m_c->p_global_in (signal_dspin_p2m_g2l_c); 506 506 xbar_p2m_c->p_local_out[0] (signal_dspin_p2m_memc); 507 for (size_t p = 0; p < nb_procs; p++) 507 for (size_t p = 0; p < nb_procs; p++) 508 508 xbar_p2m_c->p_local_in[p] (signal_dspin_p2m_proc[p]); 509 509 … … 535 535 536 536 ///////////////////////////////////// XICU 537 xicu->p_clk 538 xicu->p_resetn 539 xicu->p_vci 537 xicu->p_clk (this->p_clk); 538 xicu->p_resetn (this->p_resetn); 539 xicu->p_vci (signal_vci_tgt_xicu); 540 540 for ( size_t p=0 ; p<nb_procs ; p++) 541 541 { 542 xicu->p_irq[p] 542 xicu->p_irq[p] (signal_proc_it[p]); 543 543 } 544 544 for ( size_t i=0 ; i<32 ; i++) … … 547 547 { 548 548 if (i < 8) xicu->p_hwi[i] (signal_false); 549 else if (i < (8 + nb_dmas)) xicu->p_hwi[i] 549 else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i-8]); 550 550 else if (i < 16) xicu->p_hwi[i] (signal_false); 551 551 else if (i < (16 + nb_ttys)) xicu->p_hwi[i] (signal_irq_mtty[i-16]); 552 else if (i < 31) xicu->p_hwi[i] 552 else if (i < 31) xicu->p_hwi[i] (signal_false); 553 553 else xicu->p_hwi[i] (signal_irq_bdev); 554 554 } … … 556 556 { 557 557 if (i < 8) xicu->p_hwi[i] (signal_false); 558 else if (i < (8 + nb_dmas)) xicu->p_hwi[i] 559 else xicu->p_hwi[i] 558 else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i-8]); 559 else xicu->p_hwi[i] (signal_false); 560 560 } 561 561 } … … 571 571 572 572 //////////////////////////////////////////////// MEMC 573 memc->p_clk 574 memc->p_resetn 575 memc->p_vci_ixr 576 memc->p_vci_tgt 573 memc->p_clk (this->p_clk); 574 memc->p_resetn (this->p_resetn); 575 memc->p_vci_ixr (signal_vci_xram); 576 memc->p_vci_tgt (signal_vci_tgt_memc); 577 577 memc->p_dspin_in (signal_dspin_p2m_memc); 578 memc->p_dspin_out 578 memc->p_dspin_out (signal_dspin_m2p_memc); 579 579 580 580 // wrapper MEMC … … 588 588 589 589 /////////////////////////////////////////////// XRAM 590 xram->p_clk 591 xram->p_resetn 592 xram->p_vci 590 xram->p_clk (this->p_clk); 591 xram->p_resetn (this->p_resetn); 592 xram->p_vci (signal_vci_xram); 593 593 594 594 std::cout << " - XRAM connected" << std::endl; 595 595 596 596 ////////////////////////////////////////////// MDMA 597 mdma->p_clk 598 mdma->p_resetn 599 mdma->p_vci_target 600 mdma->p_vci_initiator 597 mdma->p_clk (this->p_clk); 598 mdma->p_resetn (this->p_resetn); 599 mdma->p_vci_target (signal_vci_tgt_mdma); 600 mdma->p_vci_initiator (signal_vci_ini_mdma); 601 601 for (size_t i=0 ; i<nb_dmas ; i++) 602 602 mdma->p_irq[i] (signal_irq_mdma[i]); … … 618 618 std::cout << " - MDMA connected" << std::endl; 619 619 620 621 622 623 624 // BDEV 625 620 /////////////////////////////// Components in I/O cluster 621 622 if ( io ) 623 { 624 // BDEV 625 bdev->p_clk (this->p_clk); 626 626 bdev->p_resetn (this->p_resetn); 627 627 bdev->p_irq (signal_irq_bdev); … … 698 698 for ( size_t i=0 ; i<nb_ttys ; i++ ) 699 699 { 700 mtty->p_irq[i] 700 mtty->p_irq[i] (signal_irq_mtty[i]); 701 701 } 702 702
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