Index: trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
===================================================================
--- trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp	(revision 431)
+++ trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp	(revision 434)
@@ -34,12 +34,12 @@
 #include "../include/vci_mem_cache.h"
 
-//////   debug services   ///////////////////////////////////////////////////////
+//////   debug services   /////////////////////////////////////////////////////////////
 // All debug messages are conditionned by two variables:
 // - compile time   : DEBUG_MEMC_*** : defined below
-// - execution time : m_debug_***    : defined by constructor arguments
-//    m_debug_* = (m_debug_ok) and (m_cpt_cycle > m_debug_start_cycle)
-/////////////////////////////////////////////////////////////////////////////////
+// - execution time : m_debug  = (m_debug_ok) and (m_cpt_cycle > m_debug_start_cycle)
+///////////////////////////////////////////////////////////////////////////////////////
 
 #define DEBUG_MEMC_GLOBAL    0 // synthetic trace of all FSMs
+#define DEBUG_MEMC_CONFIG    1 // detailed trace of CONFIG FSM
 #define DEBUG_MEMC_READ      1 // detailed trace of READ FSM
 #define DEBUG_MEMC_WRITE     1 // detailed trace of WRITE FSM
@@ -64,5 +64,6 @@
   "TGT_CMD_READ",
   "TGT_CMD_WRITE",
-  "TGT_CMD_CAS"
+  "TGT_CMD_CAS",
+  "TGT_CMD_CONFIG"
 };
 const char *tgt_rsp_fsm_str[] =
@@ -118,5 +119,6 @@
   "MULTI_ACK_UPT_LOCK",
   "MULTI_ACK_UPT_CLEAR",
-  "MULTI_ACK_WRITE_RSP"
+  "MULTI_ACK_WRITE_RSP",
+  "MULTI_ACK_CONFIG_ACK"
 };
 const char *read_fsm_str[] =
@@ -237,5 +239,6 @@
   "CLEANUP_UPT_CLEAR",
   "CLEANUP_WRITE_RSP",
-  "CLEANUP_SEND_ACK"
+  "CLEANUP_CONFIG_ACK",
+  "CLEANUP_SEND_CLACK"
 };
 const char *alloc_dir_fsm_str[] =
@@ -457,4 +460,5 @@
     for(seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++)
     {
+        if ( seg->special() ) m_seg_config = i;
         m_seg[i] = & (*seg);
         i++;
@@ -631,4 +635,5 @@
     // Initializing FSMs
     r_tgt_cmd_fsm    = TGT_CMD_IDLE;
+    r_config_fsm     = CONFIG_IDLE;
     r_tgt_rsp_fsm    = TGT_RSP_TGT_CMD_IDLE;
     r_cc_send_fsm    = CC_SEND_XRAM_RSP_IDLE;
@@ -647,17 +652,5 @@
     r_ixr_cmd_fsm    = IXR_CMD_READ_IDLE;
 
-    m_debug_global         = false;
-    m_debug_tgt_cmd_fsm    = false;
-    m_debug_tgt_rsp_fsm    = false;
-    m_debug_cc_send_fsm    = false;
-    m_debug_cc_receive_fsm = false;
-    m_debug_multi_ack_fsm  = false;
-    m_debug_read_fsm       = false;
-    m_debug_write_fsm      = false;
-    m_debug_cas_fsm        = false;
-    m_debug_cleanup_fsm    = false;
-    m_debug_ixr_cmd_fsm    = false;
-    m_debug_ixr_rsp_fsm    = false;
-    m_debug_xram_rsp_fsm   = false;
+    m_debug                = false;
     m_debug_previous_hit   = false;
     m_debug_previous_count = 0;
@@ -690,4 +683,7 @@
     m_cmd_cas_eop_fifo.init()   ;
 
+    r_config_cmd  = MEMC_CMD_NOP;
+    r_config_lock = false;
+
     r_tgt_cmd_to_tgt_rsp_req = false;
 
@@ -697,6 +693,6 @@
     r_write_to_tgt_rsp_req          = false;
     r_write_to_ixr_cmd_req          = false;
-    r_write_to_cc_send_multi_req   = false;
-    r_write_to_cc_send_brdcast_req = false;
+    r_write_to_cc_send_multi_req    = false;
+    r_write_to_cc_send_brdcast_req  = false;
     r_write_to_multi_ack_req        = false;
 
@@ -816,21 +812,9 @@
 #endif
 
-  m_debug_global         = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
-  m_debug_tgt_cmd_fsm    = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
-  m_debug_tgt_rsp_fsm    = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
-  m_debug_cc_send_fsm    = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
-  m_debug_cc_receive_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
-  m_debug_multi_ack_fsm  = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
-  m_debug_read_fsm       = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
-  m_debug_write_fsm      = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
-  m_debug_cas_fsm        = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
-  m_debug_cleanup_fsm    = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
-  m_debug_ixr_cmd_fsm    = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
-  m_debug_ixr_rsp_fsm    = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
-  m_debug_xram_rsp_fsm   = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
+  m_debug = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
 
 #if DEBUG_MEMC_GLOBAL
-  if(m_debug_global)
-  {
+if(m_debug)
+{
     std::cout
         << "---------------------------------------------"           << std::dec << std::endl
@@ -853,5 +837,5 @@
         << " - ALLOC_UPT FSM  = "  << alloc_upt_fsm_str[r_alloc_upt_fsm.read()]   << std::endl
         << " - ALLOC_HEAP FSM = "  << alloc_heap_fsm_str[r_alloc_heap_fsm.read()] << std::endl;
-  }
+}
 #endif
 
@@ -859,130 +843,137 @@
   //    TGT_CMD FSM
   ////////////////////////////////////////////////////////////////////////////////////
-  // The TGT_CMD_FSM controls the incoming VCI command pakets from the processors
+  // The TGT_CMD_FSM controls the incoming VCI command pakets from the processors,
+  // and dispatch these commands to the proper FSM through dedicated FIFOs.
   //
-  // There are 5 types of accepted commands :
-  // - READ   : A READ request has a length of 1 VCI cell. It can be a single word
-  //            or an entire cache line, depending on the PLEN value.
-  // - WRITE  : A WRITE request has a maximum length of 16 cells, and can only
-  //            concern words in a same line.
-  // - CAS    : A CAS request has a length of 2 cells or 4 cells.
-  // - LL     : An LL request has a length of 1 cell.
-  // - SC     : An SC request has a length of 2 cells. First cell contains the
-  //            acces key, second cell the data to write in case of success.
+  // There are 5 types of commands accepted in the XRAM segment:
+  // - READ   : A READ request has a length of 1 VCI flit. It can be a single word
+  //            or an entire cache line, depending on the PLEN value => READ FSM
+  // - WRITE  : A WRITE request has a maximum length of 16 flits, and can only
+  //            concern words in a same line => WRITE FSM
+  // - CAS    : A CAS request has a length of 2 flits or 4 flits => CAS FSM
+  // - LL     : An LL request has a length of 1 flit => READ FSM
+  // - SC     : An SC request has a length of 2 flits. First flit contains the
+  //            acces key, second flit the data to write => WRITE FSM.
+  //
+  // The READ/WRITE commands accepted in the configuration segment are targeting,
+  // configuration or status registers. They must contain one single flit.
+  // - For almost all addressable registers, the response is returned immediately. 
+  // - For MEMC_CMD_TYPE, the response is delayed until the operation is completed.
   ////////////////////////////////////////////////////////////////////////////////////
 
   switch(r_tgt_cmd_fsm.read())
   {
-      //////////////////
-    case TGT_CMD_IDLE:
-      if(p_vci_tgt.cmdval)
-      {
+    //////////////////
+    case TGT_CMD_IDLE:     // waiting a VCI command (RAM or CONFIG)
+    if(p_vci_tgt.cmdval)
+    {
 
 #if DEBUG_MEMC_TGT_CMD
-        if(m_debug_tgt_cmd_fsm)
-        {
-          std::cout
-              << "  <MEMC " << name()
-              << " TGT_CMD_IDLE> Receive command from srcid "
-              << std::dec << p_vci_tgt.srcid.read()
-              << " / for address "
-              << std::hex << p_vci_tgt.address.read()
-              << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " TGT_CMD_IDLE> Receive command from srcid "
+          << std::dec << p_vci_tgt.srcid.read()
+          << " / address " << std::hex << p_vci_tgt.address.read() << std::endl;
 #endif
         // checking segmentation violation
-        addr_t  address = p_vci_tgt.address.read();
-        uint32_t    plen    = p_vci_tgt.plen.read();
-        bool found = false;
-        for(size_t seg_id = 0 ; seg_id < m_nseg ; seg_id++)
-        {
-          if(m_seg[seg_id]->contains(address) &&
-              m_seg[seg_id]->contains(address + plen - vci_param_int::B))
-          {
-            found = true;
-          }
-        }
-
-        if(not found)
-        {
-          r_tgt_cmd_fsm = TGT_CMD_ERROR;
-        }
-        else if(p_vci_tgt.cmd.read() == vci_param_int::CMD_READ)
-        {
-          // check that the pktid is either :
-          // TYPE_READ_DATA_UNC
-          // TYPE_READ_DATA_MISS
-          // TYPE_READ_INS_UNC
-          // TYPE_READ_INS_MISS
-          // ==> bit2 must be zero with the TSAR encoding
-          // ==> mask = 0b0100 = 0x4
-          assert(((p_vci_tgt.pktid.read() & 0x4) == 0x0) &&
-                 "The type specified in the pktid field is incompatible with the READ CMD");
-          r_tgt_cmd_fsm = TGT_CMD_READ;
-        }
-        else if(p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)
-        {
-          // check that the pktid is TYPE_WRITE
-          // ==> TYPE_WRITE = X100 with the TSAR encoding
-          // ==> mask = 0b0111 = 0x7
-          assert(((p_vci_tgt.pktid.read() & 0x7) == 0x4) &&
-                 "The type specified in the pktid field is incompatible with the WRITE CMD");
-          r_tgt_cmd_fsm = TGT_CMD_WRITE;
-        }
-        else if(p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ)
-        {
-          // check that the pktid is TYPE_LL
-          // ==> TYPE_LL = X110 with the TSAR encoding
-          // ==> mask = 0b0111 = 0x7
-          assert(((p_vci_tgt.pktid.read() & 0x7) == 0x6) &&
-                 "The type specified in the pktid field is incompatible with the LL CMD");
-          r_tgt_cmd_fsm = TGT_CMD_READ;
-        }
-        else if(p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP)
-        {
-          // check that the pktid is either :
-          // TYPE_CAS
-          // TYPE_SC
-          // ==> TYPE_CAS = X101 with the TSAR encoding
-          // ==> TYPE_SC  = X111 with the TSAR encoding
-          // ==> mask = 0b0101 = 0x5
-          assert(((p_vci_tgt.pktid.read() & 0x5) == 0x5) &&
-                 "The type specified in the pktid field is incompatible with the NOP CMD");
-
-          if((p_vci_tgt.pktid.read() & 0x7) == TYPE_CAS)
-            r_tgt_cmd_fsm = TGT_CMD_CAS;
-          else // TYPE_SC
-            r_tgt_cmd_fsm = TGT_CMD_WRITE;
-        }
-        else
-        {
-          std::cout << "VCI_MEM_CACHE ERROR " << name()
-                    << " TGT_CMD_IDLE state" << std::endl;
-          std::cout << " illegal VCI command type" << std::endl;
-          exit(0);
-        }
-      }
-      break;
-
-    case TGT_CMD_ERROR:
-      // A segmentation violation has been detected, thus a response with error
-      // must be sent
-
-      // wait if pending TGT_CMD request to TGT_RSP FSM
-      if(r_tgt_cmd_to_tgt_rsp_req.read()) break;
-
-      // consume all the command packet flits and set new request to the
-      // TGT_RSP FSM
-      if(p_vci_tgt.cmdval and p_vci_tgt.eop)
-      {
-        r_tgt_cmd_to_tgt_rsp_req   = true;
+        addr_t      address  = p_vci_tgt.address.read();
+        uint32_t    plen     = p_vci_tgt.plen.read();
+        bool        found    = false;
+        bool        config   = false;
+
+        // register arguments for response (segmentation violation or config)
         r_tgt_cmd_to_tgt_rsp_srcid = p_vci_tgt.srcid.read();
         r_tgt_cmd_to_tgt_rsp_trdid = p_vci_tgt.trdid.read();
         r_tgt_cmd_to_tgt_rsp_pktid = p_vci_tgt.pktid.read();
 
-        r_tgt_cmd_fsm = TGT_CMD_IDLE;
+        for(size_t seg_id = 0 ; (seg_id < m_nseg) and not found ; seg_id++)
+        {
+            if( m_seg[seg_id]->contains(address) and
+                m_seg[seg_id]->contains(address + plen - vci_param_int::B) )
+            {
+                found = true;
+                if ( m_seg[seg_id]->special() ) config = true;
+            }
+        }
+
+        if ( not found )                /////////// out of segment error
+        {
+            r_tgt_cmd_fsm   = TGT_CMD_ERROR;
+        }
+        else if ( config )              /////////// configuration command
+        {
+            if ( not p_vci_tgt.eop.read() ) r_tgt_cmd_fsm = TGT_CMD_ERROR;
+            else                            r_tgt_cmd_fsm = TGT_CMD_CONFIG;
+        }
+        else                            //////////// memory access 
+        {
+            if ( p_vci_tgt.cmd.read() == vci_param_int::CMD_READ )
+            {
+                // check that the pktid is either :
+                // TYPE_READ_DATA_UNC
+                // TYPE_READ_DATA_MISS
+                // TYPE_READ_INS_UNC
+                // TYPE_READ_INS_MISS
+                // ==> bit2 must be zero with the TSAR encoding
+                // ==> mask = 0b0100 = 0x4
+                assert( ((p_vci_tgt.pktid.read() & 0x4) == 0x0) and
+                "The type specified in the pktid field is incompatible with the READ CMD");
+                r_tgt_cmd_fsm = TGT_CMD_READ;
+            }
+            else if(p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)
+            {
+                // check that the pktid is TYPE_WRITE
+                // ==> TYPE_WRITE = X100 with the TSAR encoding
+                // ==> mask = 0b0111 = 0x7
+                assert(((p_vci_tgt.pktid.read() & 0x7) == 0x4) and
+                "The type specified in the pktid field is incompatible with the WRITE CMD");
+                r_tgt_cmd_fsm = TGT_CMD_WRITE;
+            }
+            else if(p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ)
+            {
+                // check that the pktid is TYPE_LL
+                // ==> TYPE_LL = X110 with the TSAR encoding
+                // ==> mask = 0b0111 = 0x7
+                assert(((p_vci_tgt.pktid.read() & 0x7) == 0x6) and
+                "The type specified in the pktid field is incompatible with the LL CMD");
+                r_tgt_cmd_fsm = TGT_CMD_READ;
+            }
+            else if(p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP)
+            {
+                // check that the pktid is either :
+                // TYPE_CAS
+                // TYPE_SC
+                // ==> TYPE_CAS = X101 with the TSAR encoding
+                // ==> TYPE_SC  = X111 with the TSAR encoding
+                // ==> mask = 0b0101 = 0x5
+                assert(((p_vci_tgt.pktid.read() & 0x5) == 0x5) and
+                "The type specified in the pktid field is incompatible with the NOP CMD");
+
+                if((p_vci_tgt.pktid.read() & 0x7) == TYPE_CAS) r_tgt_cmd_fsm = TGT_CMD_CAS;
+                else                                           r_tgt_cmd_fsm = TGT_CMD_WRITE; 
+            }
+            else
+            {
+                r_tgt_cmd_fsm = TGT_CMD_ERROR;
+            }
+        }
+    }
+    break;
+
+    ///////////////////
+    case TGT_CMD_ERROR:  // response error must be sent
+
+    // wait if pending TGT_CMD request to TGT_RSP FSM
+    if(r_tgt_cmd_to_tgt_rsp_req.read()) break;
+
+    // consume all the command packet flits before sending response error
+    if ( p_vci_tgt.cmdval and p_vci_tgt.eop )
+    {
+        r_tgt_cmd_to_tgt_rsp_req   = true;
+        r_tgt_cmd_to_tgt_rsp_error = 1;
+        r_tgt_cmd_fsm              = TGT_CMD_IDLE;
 
 #if DEBUG_MEMC_TGT_CMD
-if(m_debug_tgt_cmd_fsm)
+if(m_debug)
   std::cout << "  <MEMC " << name()
     << " TGT_CMD_ERROR> Segmentation violation:"
@@ -993,48 +984,117 @@
     << " / plen = " << std::dec << p_vci_tgt.plen.read() << std::endl;
 #endif
-      }
-
-      break;
-
-      //////////////////
-    case TGT_CMD_READ:
-      // This test checks that the read does not cross a cache line limit.
-      // It must not be taken into account when dealing with an LL CMD.
-      if(((m_x[(addr_t) p_vci_tgt.address.read()]+ (p_vci_tgt.plen.read() >>2)) > 16) &&
+
+    }
+    break;
+
+    ////////////////////
+    case TGT_CMD_CONFIG:    // execute config request and return response
+    {
+        if ( r_tgt_cmd_to_tgt_rsp_req.read() ) break;
+
+        addr_t   seg_base = m_seg[m_seg_config]->baseAddress();
+        addr_t   address  = p_vci_tgt.address.read();
+        size_t   cell     = (address - seg_base)/vci_param_int::B;
+        bool     need_rsp = true;  // default value
+        size_t   error    = 0;     // default value
+        uint32_t rdata    = 0;     // default value
+
+        if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ)         // get lock
+             and (cell == MEMC_LOCK) )
+        {
+            rdata         = (uint32_t)r_config_lock.read();
+            r_config_lock = true;
+        }
+        else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)  // release lock
+                   and (cell == MEMC_LOCK) )
+        {
+            r_config_lock = false;
+        }
+        else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set cmd type
+                   and (cell == MEMC_CMD_TYPE) )
+        {
+            r_config_cmd = p_vci_tgt.wdata.read();
+            need_rsp     = false;
+        }
+        else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set addr_lo
+                   and (cell == MEMC_ADDR_LO) )
+        {
+            r_config_address = (r_config_address.read() & 0xFFFFFFFF00000000LL) |
+                               (addr_t)p_vci_tgt.wdata.read();
+        }
+        else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set addr_hi
+                   and (cell == MEMC_ADDR_HI) )
+        {
+            r_config_address = (r_config_address.read() & 0x00000000FFFFFFFFLL) |
+                               ((addr_t)p_vci_tgt.wdata.read())<<32;
+        }
+        else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set buf_lines
+                   and (cell == MEMC_BUF_LENGTH) )
+        {
+            size_t lines = (size_t)(p_vci_tgt.wdata.read()/(m_words*vci_param_int::B));
+            if ( r_config_address.read()/(m_words*vci_param_int::B) ) lines++;
+            r_config_nlines = lines;
+        }
+        else
+        {
+            error = 1;
+        }
+
+        if ( need_rsp )
+        {
+            // blocked if previous pending request to TGT_RSP FSM
+            if ( r_tgt_cmd_to_tgt_rsp_req.read() ) break;
+
+            r_tgt_cmd_to_tgt_rsp_req   = true;
+            r_tgt_cmd_to_tgt_rsp_error = error;
+            r_tgt_cmd_to_tgt_rsp_rdata = rdata;
+            r_tgt_cmd_fsm              = TGT_CMD_IDLE;
+        }
+        else
+        {
+            r_tgt_cmd_fsm              = TGT_CMD_IDLE;
+        }
+
+#if DEBUG_MEMC_TGT_CMD
+if(m_debug)
+std::cout << "  <MEMC " << name() << " TGT_CMD_CONFIG> Configuration request:"
+          << " address = " << std::hex << p_vci_tgt.address.read()
+          << " / wdata = " << p_vci_tgt.wdata.read()
+          << " / error = " << error << std::endl;
+#endif
+        break;
+    }
+    //////////////////
+    case TGT_CMD_READ:    // Push a read request into read fifo
+
+    // check that the read does not cross a cache line limit.
+    if ( ((m_x[(addr_t) p_vci_tgt.address.read()]+ (p_vci_tgt.plen.read() >>2)) > 16) and
           (p_vci_tgt.cmd.read() != vci_param_int::CMD_LOCKED_READ))
-      {
-        std::cout
-            << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state"
-            << std::endl;
-        std::cout
-            << " illegal address/plen combination for VCI read command" << std::endl;
+    {
+        std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state"
+                  << " illegal address/plen for VCI read command" << std::endl;
         exit(0);
-      }
-      if(!p_vci_tgt.eop.read())
-      {
-        std::cout
-            << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state"
-            << std::endl;
-        std::cout
-            << " read or ll command packets must contain one single flit"
-            << std::endl;
+    }
+    // check single flit
+    if(!p_vci_tgt.eop.read())
+    {
+        std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state"
+                  << " read command packet must contain one single flit" << std::endl;
         exit(0);
-      }
-      if((p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) && (p_vci_tgt.plen.read() != 8))
-      {
-        std::cout
-            << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state"
-            << std::endl;
-        std::cout
-            << " ll command packets must have a plen of 8"
-            << std::endl;
+    } 
+    // check plen for LL
+    if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) and 
+         (p_vci_tgt.plen.read() != 8) )
+    {
+        std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state"
+                  << " ll command packets must have a plen of 8" << std::endl;
         exit(0);
-      }
-
-      if(p_vci_tgt.cmdval && m_cmd_read_addr_fifo.wok())
-      {
+    }
+
+    if ( p_vci_tgt.cmdval and m_cmd_read_addr_fifo.wok() )
+    {
 
 #if DEBUG_MEMC_TGT_CMD
-if(m_debug_tgt_cmd_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " TGT_CMD_READ> Push into read_fifo:"
           << " address = " << std::hex << p_vci_tgt.address.read()
@@ -1045,19 +1105,17 @@
 #endif
         cmd_read_fifo_put = true;
-        if(p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ)
-          m_cpt_ll++;
-        else
-          m_cpt_read++;
+        if(p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) m_cpt_ll++;
+        else                                                       m_cpt_read++;
         r_tgt_cmd_fsm = TGT_CMD_IDLE;
-      }
-      break;
-
-      ///////////////////
+    }
+    break;
+
+    ///////////////////
     case TGT_CMD_WRITE:
-      if(p_vci_tgt.cmdval && m_cmd_write_addr_fifo.wok())
-      {
+    if(p_vci_tgt.cmdval and m_cmd_write_addr_fifo.wok())
+    {
 
 #if DEBUG_MEMC_TGT_CMD
-if(m_debug_tgt_cmd_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " TGT_CMD_WRITE> Push into write_fifo:"
           << " address = " << std::hex << p_vci_tgt.address.read()
@@ -1071,24 +1129,21 @@
         cmd_write_fifo_put = true;
         if(p_vci_tgt.eop)  r_tgt_cmd_fsm = TGT_CMD_IDLE;
-      }
-      break;
-
-      ////////////////////
+    }
+    break;
+
+    /////////////////
     case TGT_CMD_CAS:
-      if((p_vci_tgt.plen.read() != 8) && (p_vci_tgt.plen.read() != 16))
-      {
-        std::cout
-            << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_CAS state"
-            << std::endl
-            << "illegal format for CAS command " << std::endl;
-
+    if((p_vci_tgt.plen.read() != 8) and (p_vci_tgt.plen.read() != 16))
+    {
+        std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_CAS state"
+                  << "illegal format for CAS command " << std::endl;
         exit(0);
-      }
-
-      if(p_vci_tgt.cmdval && m_cmd_cas_addr_fifo.wok())
-      {
+    }
+
+    if(p_vci_tgt.cmdval and m_cmd_cas_addr_fifo.wok())
+    {
 
 #if DEBUG_MEMC_TGT_CMD
-if(m_debug_tgt_cmd_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " TGT_CMD_CAS> Pushing command into cmd_cas_fifo:"
           << " address = " << std::hex << p_vci_tgt.address.read()
@@ -1102,6 +1157,6 @@
         cmd_cas_fifo_put = true;
         if(p_vci_tgt.eop) r_tgt_cmd_fsm = TGT_CMD_IDLE;
-      }
-      break;
+    }
+    break;
   } // end switch tgt_cmd_fsm
 
@@ -1115,5 +1170,4 @@
   // It can be update or inval requests initiated by the WRITE or CAS FSM,
   // or inval requests initiated by the XRAM_RSP FSM.
-  // It can also be a direct request from the WRITE FSM.
   //
   // The FSM decrements the proper entry in UPT.
@@ -1129,7 +1183,7 @@
   switch(r_multi_ack_fsm.read())
   {
-    ///////////////////
+    ////////////////////
     case MULTI_ACK_IDLE:
-      {
+    {
         bool multi_ack_fifo_rok = m_cc_receive_to_multi_ack_fifo.rok();
 
@@ -1165,23 +1219,19 @@
 
 #if DEBUG_MEMC_MULTI_ACK
-        if(m_debug_multi_ack_fsm)
-        {
-          if (multi_ack_fifo_rok)
-          {
-            std::cout
-              << "  <MEMC " << name()
-              << " MULTI_ACK_IDLE> Response for UPT entry "
-              << updt_index
-              << std::endl;
-          }
-          else
-          {
-            std::cout
-              << "  <MEMC " << name()
-              << " MULTI_ACK_IDLE> Write FSM request to decrement UPT entry "
-              << updt_index
-              << std::endl;
-          }
-        }
+if(m_debug)
+{
+    if (multi_ack_fifo_rok)
+    {
+        std::cout << "  <MEMC " << name()
+                  << " MULTI_ACK_IDLE> Response for UPT entry "
+                  << updt_index << std::endl;
+    }
+    else
+    {
+        std::cout << "  <MEMC " << name()
+                  << " MULTI_ACK_IDLE> Write FSM request to decrement UPT entry "
+                  << updt_index << std::endl;
+    }
+}
 #endif
         break;
@@ -1190,5 +1240,5 @@
     ////////////////////////
     case MULTI_ACK_UPT_LOCK:
-      {
+    {
         // get lock to the UPDATE table
         if(r_alloc_upt_fsm.read() != ALLOC_UPT_MULTI_ACK) break;
@@ -1200,11 +1250,8 @@
         if(not valid)
         {
-          std::cout
-            << "VCI_MEM_CACHE ERROR " << name()
-            << " MULTI_ACK_UPT_LOCK state" << std::endl
-            << "unsuccessful access to decrement the UPT"
-            << std::endl;
-
-          exit(0);
+            std::cout << "VCI_MEM_CACHE ERROR " << name()
+                      << " MULTI_ACK_UPT_LOCK state" << std::endl
+                      << "unsuccessful access to decrement the UPT" << std::endl;
+            exit(0);
         }
 
@@ -1219,29 +1266,22 @@
 
 #if DEBUG_MEMC_MULTI_ACK
-        if(m_debug_multi_ack_fsm)
-        {
-          std::cout
-            << "  <MEMC " << name()
-            << " MULTI_ACK_UPT_LOCK> Decrement the responses counter for UPT:"
-            << " entry = "       << r_multi_ack_upt_index.read()
-            << " / rsp_count = " << std::dec << count
-            << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " MULTI_ACK_UPT_LOCK> Decrement the responses counter for UPT:"
+          << " entry = "       << r_multi_ack_upt_index.read()
+          << " / rsp_count = " << std::dec << count << std::endl;
 #endif
         break;
-      }
+    }
 
     /////////////////////////
-    case MULTI_ACK_UPT_CLEAR:
-      {
+    case MULTI_ACK_UPT_CLEAR:   // Clear UPT entry / Test if rsp or ack required
+    {
         if(r_alloc_upt_fsm.read() != ALLOC_UPT_MULTI_ACK)
         {
-          std::cout
-            << "VCI_MEM_CACHE ERROR " << name()
-            << " MULTI_ACK_UPT_CLEAR state"
-            << " bad UPT allocation"
-            << std::endl;
-
-          exit(0);
+            std::cout << "VCI_MEM_CACHE ERROR " << name()
+                      << " MULTI_ACK_UPT_CLEAR state"
+                      << " bad UPT allocation" << std::endl;
+            exit(0);
         }
 
@@ -1251,36 +1291,26 @@
         r_multi_ack_nline = m_upt.nline(r_multi_ack_upt_index.read());
         bool need_rsp     = m_upt.need_rsp(r_multi_ack_upt_index.read());
+        bool need_ack     = m_upt.need_ack(r_multi_ack_upt_index.read());
 
         // clear the UPT entry
         m_upt.clear(r_multi_ack_upt_index.read());
 
-        if(need_rsp)
-        {
-          r_multi_ack_fsm = MULTI_ACK_WRITE_RSP;
-        }
-        else
-        {
-          r_multi_ack_fsm = MULTI_ACK_IDLE;
-        }
+        if      ( need_rsp ) r_multi_ack_fsm = MULTI_ACK_WRITE_RSP;
+        else if ( need_ack ) r_multi_ack_fsm = MULTI_ACK_CONFIG_ACK;
+        else                 r_multi_ack_fsm = MULTI_ACK_IDLE;
 
 #if DEBUG_MEMC_MULTI_ACK
-        if(m_debug_multi_ack_fsm)
-        {
-          std::cout
-            <<  "  <MEMC " << name()
-            << " MULTI_ACK_UPT_CLEAR> Clear UPT entry "
-            << r_multi_ack_upt_index.read()
-            << std::endl;
-        }
+if(m_debug)
+std::cout <<  "  <MEMC " << name()
+          << " MULTI_ACK_UPT_CLEAR> Clear UPT entry "
+          << std::dec << r_multi_ack_upt_index.read() << std::endl;
 #endif
         break;
-      }
-
+    }
     /////////////////////////
-    case MULTI_ACK_WRITE_RSP:
-      {
-        // Post a request to TGT_RSP FSM
-        // Wait if pending request to the TGT_RSP FSM
-        if(r_multi_ack_to_tgt_rsp_req.read()) break;
+    case MULTI_ACK_WRITE_RSP:     // Post a response request to TGT_RSP FSM
+                                  // Wait if pending request 
+    {
+        if ( r_multi_ack_to_tgt_rsp_req.read() ) break;
 
         r_multi_ack_to_tgt_rsp_req   = true;
@@ -1291,16 +1321,367 @@
 
 #if DEBUG_MEMC_MULTI_ACK
-        if(m_debug_multi_ack_fsm)
-        {
-          std::cout
-            << "  <MEMC " << name()
-            << " MULTI_ACK_WRITE_RSP> Request TGT_RSP FSM to send a response to srcid "
-            << r_multi_ack_srcid.read()
-            << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " MULTI_ACK_WRITE_RSP>"
+          << " Request TGT_RSP FSM to send a response to srcid "
+          << std::hex << r_multi_ack_srcid.read() << std::endl;
 #endif
         break;
-      }
+    }
+    //////////////////////////
+    case MULTI_ACK_CONFIG_ACK:    // Signals multi-inval completion to CONFIG FSM
+                                  // Wait if pending request 
+    {
+        if ( r_multi_ack_to_config_ack.read() ) break;
+
+        r_multi_ack_to_config_ack   = true;
+        r_multi_ack_fsm              = MULTI_ACK_IDLE;
+
+#if DEBUG_MEMC_MULTI_ACK
+if(m_debug)
+std::cout << "  <MEMC " << name() << " MULTI_ACK_CONFIG_ACK>"
+          << " Signals inval completion to CONFIG FSM" << std::endl;
+#endif
+        break;
+    }
   } // end switch r_multi_ack_fsm
+
+  ////////////////////////////////////////////////////////////////////////////////////
+  //    CONFIG FSM
+  ////////////////////////////////////////////////////////////////////////////////////
+  // The CONFIG FSM handles the VCI configuration requests (INVAL & SYNC).
+  // The target buffer can have any size, and there is one single command for
+  // all cache lines covered by the target buffer. 
+  // An INVAL or SYNC configuration request is defined by the followinf registers:
+  // - bool      r_config_cmd        : INVAL / SYNC / NOP)
+  // - uint64_t  r_config_address    : buffer base address
+  // - uint32_t  r_config_nlines     : number of lines covering buffer
+  //
+  // For both INVAL and SYNC commands, the CONFIG FSM contains the loop handling 
+  // all cache lines covered by the target buffer.
+  //
+  // - INVAL request:
+  //   For each line, it access to the DIR array. 
+  //   In case of miss, it does nothing, and a response is requested to TGT_RSP FSM. 
+  //   In case of hit, with no copies in L1 caches, the line is invalidated and
+  //   a response is requested to TGT_RSP FSM.
+  //   If there is copies, a multi-inval, or a broadcast-inval coherence transaction
+  //   is launched and registered in UPT. The multi-inval transaction is signaled
+  //   by the r_multi_ack_to config_ack or r_cleanup_to_config_ack flip-flops.
+  //   The config inval response is sent only when the last line has been invalidated.
+  //
+  // - SYNC request: Not implemented yet
+  //
+  // From the software point of view, a configuration request is a sequence
+  // of 6 atomic accesses:
+  // - Read  MEMC_LOCK       : Get the lock
+  // - Write MEMC_ADDR_LO    : Set the buffer address LSB
+  // - Write MEMC_ADDR_HI    : Set the buffer address MSB
+  // - Write MEMC_BUF_LENGTH : set buffer length (bytes)
+  // - Write MEMC_CMD_TYPE   : launch the actual operation
+  // - WRITE MEMC_LOCK       : release the lock
+  ////////////////////////////////////////////////////////////////////////////////////
+
+  switch( r_config_fsm.read() )
+  {
+      /////////////////
+      case CONFIG_IDLE:  // waiting a config request 
+      {
+          if ( r_config_cmd.read() != MEMC_CMD_NOP )  
+          {
+              r_config_fsm    = CONFIG_LOOP;
+          }
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_IDLE> Config Request received" 
+          << " address = " << std::hex << r_config_address.read()
+          << " / nlines = " << std::dec << r_config_nlines.read()
+          << " / type = " << r_config_cmd.read() << std::endl;
+#endif
+          break;
+      }
+      /////////////////
+      case CONFIG_LOOP:   // test last line 
+      {
+          if ( r_config_nlines.read() == 0 )
+          {
+              r_config_cmd = MEMC_CMD_NOP;
+              r_config_fsm = CONFIG_RSP;
+          }
+          else
+          {
+              r_config_fsm = CONFIG_DIR_REQ;
+          }
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_SYNC_LOOP>" 
+          << " address = " << std::hex << r_config_address.read()    
+          << " / nlines = " << std::dec << r_config_nlines.read() 
+          << " / type = " << r_config_cmd.read() << std::endl;
+#endif
+          break;
+      }
+      ////////////////////
+      case CONFIG_DIR_REQ:  // Request directory lock
+      {
+          if ( r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG )
+          {
+              r_config_fsm = CONFIG_DIR_ACCESS;
+          }
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_INVAL_DIR_REQ>"
+          << " Request DIR access" << std::endl;
+#endif
+          break;
+      }
+      ///////////////////////
+      case CONFIG_DIR_ACCESS:   // Access directory and decode cmd
+      {
+          size_t way = 0;
+          DirectoryEntry entry = m_cache_directory.read(r_config_address.read(), way);
+
+          if ( entry.valid and                            // hit & inval command
+               (r_config_cmd.read() == MEMC_CMD_INVAL) ) 
+          {
+              r_config_way    = way;
+              r_config_is_cnt = entry.is_cnt;
+              r_config_count  = entry.count;
+              r_config_fsm    = CONFIG_DIR_INVAL;
+          }
+          else if ( entry.valid and                       // hit & sync command
+                    entry.dirty and
+                    (r_config_cmd.read() == MEMC_CMD_SYNC) )
+          { 
+              std::cout << "VCI_MEM_CACHE ERROR: "
+                        << "SYNC config request not implemented yet" << std::endl;
+              exit(0);
+          }
+          else                                            // nothing to do : return to LOOP 
+          {
+              r_config_nlines  = r_config_nlines.read() - 1;
+              r_config_address = r_config_address.read() + (m_words*vci_param_int::B);
+              r_config_fsm     = CONFIG_LOOP;
+          }
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_DIR_ACCESS> Accessing directory: "
+          << " address = " << std::hex << m_cmd_read_addr_fifo.read()
+          << " / hit = " << std::dec << entry.valid
+          << " / dirty = " <<std::dec << entry.dirty
+          << " / count = " <<std::dec << entry.count
+          << " / is_cnt = " << entry.is_cnt << std::endl;
+#endif
+          break;
+      }
+      //////////////////////
+      case CONFIG_DIR_INVAL:  // Invalidate the directory entry
+      {
+          size_t set        = m_y[(addr_t)(r_config_address.read())];
+          size_t way        = r_config_way.read();
+
+          m_cache_directory.inval( way, set );
+
+          if ( r_config_count.read() == 0 )     // return to LOOP
+          {
+              r_config_nlines  = r_config_nlines.read() - 1;
+              r_config_address = r_config_address.read() + (m_words*vci_param_int::B);
+              r_config_fsm     = CONFIG_LOOP;
+          }
+          else if ( r_config_is_cnt.read() )    // broacast required
+          {
+              r_config_fsm = CONFIG_BC_UPT_LOCK;
+          }
+          else
+          {
+              r_config_fsm = CONFIG_UPT_LOCK;
+          }
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_DIR_INVAL> Inval directory entry" << std::endl;
+#endif
+          break;
+      }
+      ////////////////////////
+      case CONFIG_BC_UPT_LOCK:  // try to register BC transaction in UPT
+      {
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_CONFIG )
+          {
+              bool        wok       = false;
+              size_t      index     = 0;
+              size_t      srcid     = r_config_srcid.read();
+              size_t      trdid     = r_config_trdid.read();
+              size_t      pktid     = r_config_pktid.read();
+              addr_t      nline     = m_nline[(addr_t)(r_config_address.read())];
+              size_t      nb_copies = r_config_count.read();
+
+              wok = m_upt.set(false,    // it's an inval transaction
+                              true,     // it's a broadcast
+                              false,    // no response required
+                              true,     // acknowledge required
+                              srcid,
+                              trdid,
+                              pktid,
+                              nline,
+                              nb_copies,
+                              index);
+              if ( wok ) 
+              {
+                  r_config_fsm       = CONFIG_BC_SEND;
+                  r_config_upt_index = index;
+
+#if DEBUG_MEMC_CONFIG
+if( m_debug )
+std::cout << "  <MEMC " << name() 
+          << " CONFIG_BC_UPT_LOCK> Register broadcast inval in UPT" << std::endl;
+#endif
+              }
+              else
+              {
+                  r_config_fsm       = CONFIG_UPT_WAIT;
+          
+#if DEBUG_MEMC_CONFIG
+if( m_debug )
+std::cout << "  <MEMC " << name() << " CONFIG_BC_UPT_LOCK>"
+          << " UPT full" << std::endl;
+#endif
+              }
+          }
+          break;
+      }
+      ////////////////////
+      case CONFIG_BC_SEND:    // Post a broadcast inval request to CC_SEND FSM
+      {
+          if( not r_config_to_cc_send_multi_req.read() and 
+              not r_config_to_cc_send_brdcast_req.read() )
+          {
+              r_config_to_cc_send_multi_req   = false;
+              r_config_to_cc_send_brdcast_req = true;
+              r_config_to_cc_send_trdid       = r_config_upt_index.read();
+              r_config_to_cc_send_nline       = m_nline[(addr_t)(r_config_address.read())];
+
+              r_cleanup_to_config_ack         = false;
+
+              r_config_fsm                    = CONFIG_BC_WAIT;
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_BC_SEND>"
+          << " Post a broadcast inval request to CC_SEND FSM" 
+          << " / address = " << r_config_address.read() <<std::endl;
+#endif
+          }
+          break;
+      }
+      ////////////////////
+      case CONFIG_BC_WAIT:      // wait broadcast completion to return to LOOP
+      {
+          if ( r_cleanup_to_config_ack.read() ) r_config_fsm = CONFIG_LOOP;
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_BC_WAIT>"
+          << " Waiting broadcast inval completion" << std::endl; 
+#endif
+          break;
+      }
+      /////////////////////
+      case CONFIG_UPT_LOCK:  // Try to register multi-update in UPT
+      {
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_CONFIG )
+          {
+              bool        wok       = false;
+              size_t      index     = 0;
+              size_t      srcid     = r_config_srcid.read();
+              size_t      trdid     = r_config_trdid.read();
+              size_t      pktid     = r_config_pktid.read();
+              addr_t      nline     = m_nline[(addr_t)(r_config_address.read())];
+              size_t      nb_copies = r_config_count.read();
+
+              wok = m_upt.set(false,    // it's an inval transaction
+                              false,    // not a broadcast
+                              false,    // no response required
+                              true,     // acknowledge required
+                              srcid,
+                              trdid,
+                              pktid,
+                              nline,
+                              nb_copies,
+                              index);
+              if ( wok ) 
+              {
+                  r_config_fsm       = CONFIG_BC_SEND;
+                  r_config_upt_index = index;
+
+#if DEBUG_MEMC_CONFIG
+if( m_debug )
+std::cout << "  <MEMC " << name() 
+          << " CONFIG_BC_UPT_LOCK> Register broadcast inval in UPT" << std::endl;
+#endif
+              }
+              else
+              {
+                  r_config_fsm       = CONFIG_UPT_WAIT;
+          
+#if DEBUG_MEMC_CONFIG
+if( m_debug )
+std::cout << "  <MEMC " << name() << " CONFIG_BC_UPT_LOCK>"
+          << " UPT full" << std::endl;
+#endif
+              }
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_UPT_LOCK> Request access to UPT" << std::endl;
+#endif
+          }
+          break; 
+      }
+      /////////////////////
+      case CONFIG_HEAP_REQ:  // request access to the heap
+      {
+          break; 
+      }
+
+      ////////////////
+      case CONFIG_RSP:  // request TGT_RSP FSM to return response 
+      {
+          if ( not r_config_to_tgt_rsp_req )
+          {
+              r_config_to_tgt_rsp_srcid  = r_config_srcid.read();
+              r_config_to_tgt_rsp_trdid  = r_config_trdid.read();
+              r_config_to_tgt_rsp_pktid  = r_config_pktid.read();
+              r_config_to_tgt_rsp_error  = false;
+              r_config_to_tgt_rsp_req    = true;
+              r_config_fsm               = CONFIG_IDLE;
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_RSP> Request TGT_RSP FSM to return response:"
+          << " error = " << r_config_to_tgt_rsp_error.read()
+          << " / rsrcid = " << std::hex << m_cmd_read_srcid_fifo.read() << std::endl;
+#endif
+          }
+          break;
+
+      }
+      /////////////////////
+      case CONFIG_UPT_WAIT:    // release the lock on UPT for one cycle, and retry
+      {
+          if ( r_config_is_cnt.read() ) r_config_fsm = CONFIG_BC_UPT_LOCK;
+          else                          r_config_fsm = CONFIG_UPT_LOCK;
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_UPT_WAIT>"
+          << " Release UPT lock" << std::endl;
+#endif
+          break;
+      }
+  }  // end switch r_config_fsm
 
   ////////////////////////////////////////////////////////////////////////////////////
@@ -1329,13 +1710,12 @@
   switch(r_read_fsm.read())
   {
-    ///////////////
-    case READ_IDLE:
-      // waiting a read request
-    {
+      ///////////////
+      case READ_IDLE:  // waiting a read request
+      {
       if(m_cmd_read_addr_fifo.rok())
       {
 
 #if DEBUG_MEMC_READ
-if(m_debug_read_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " READ_IDLE> Read request"
           << " : address = " << std::hex << m_cmd_read_addr_fifo.read()
@@ -1350,23 +1730,21 @@
     }
 
+    //////////////////
+    case READ_DIR_REQ:  // Get the lock to the directory
+    {
+      if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ)
+      {
+        r_read_fsm = READ_DIR_LOCK;
+      }
+
+#if DEBUG_MEMC_READ
+if(m_debug)
+std::cout << "  <MEMC " << name() << " READ_DIR_REQ> Requesting DIR lock " << std::endl;
+#endif
+      break;
+    }
+
     ///////////////////
-    case READ_DIR_REQ:
-      // Get the lock to the directory
-    {
-      if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ)
-      {
-        r_read_fsm = READ_DIR_LOCK;
-      }
-
-#if DEBUG_MEMC_READ
-if(m_debug_read_fsm)
-std::cout << "  <MEMC " << name() << " READ_DIR_REQ> Requesting DIR lock " << std::endl;
-#endif
-      break;
-    }
-
-    ///////////////////
-    case READ_DIR_LOCK:
-      // check directory for hit / miss
+    case READ_DIR_LOCK:  // check directory for hit / miss
     {
       if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ)
@@ -1400,5 +1778,5 @@
         {
           // test if we need to register a new copy in the heap
-          if(entry.is_cnt || (entry.count == 0) || !cached_read)
+          if(entry.is_cnt or (entry.count == 0) or !cached_read)
           {
             r_read_fsm = READ_DIR_HIT;
@@ -1415,5 +1793,5 @@
 
 #if DEBUG_MEMC_READ
-if(m_debug_read_fsm)
+if(m_debug)
 {
 std::cout << "  <MEMC " << name() << " READ_DIR_LOCK> Accessing directory: "
@@ -1503,5 +1881,5 @@
 
 #if DEBUG_MEMC_READ
-if(m_debug_read_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " READ_DIR_HIT> Update directory entry:"
           << " addr = " << std::hex << m_cmd_read_addr_fifo.read()
@@ -1539,5 +1917,5 @@
 
 #if DEBUG_MEMC_READ
-if(m_debug_read_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " READ_HEAP_REQ>"
           << " Requesting HEAP lock " << std::endl;
@@ -1553,5 +1931,5 @@
       {
         // enter counter mode when we reach the limit of copies or the heap is full
-        bool go_cnt = (r_read_count.read() >= m_max_copies) || m_heap.is_full();
+        bool go_cnt = (r_read_count.read() >= m_max_copies) or m_heap.is_full();
 
         // read data in the cache
@@ -1626,5 +2004,5 @@
 
 #if DEBUG_MEMC_READ
-if(m_debug_read_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " READ_HEAP_LOCK> Update directory:"
           << " tag = " << std::hex << entry.tag
@@ -1670,5 +2048,5 @@
 
 #if DEBUG_MEMC_READ
-if(m_debug_read_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " READ_HEAP_WRITE> Add an entry in the heap:"
           << " owner_id = " << std::hex << heap_entry.owner.srcid
@@ -1758,5 +2136,5 @@
 
 #if DEBUG_MEMC_READ
-if(m_debug_read_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " READ_RSP> Request TGT_RSP FSM to return data:"
           << " rsrcid = " << std::hex << m_cmd_read_srcid_fifo.read()
@@ -1778,8 +2156,8 @@
         bool        wok       = !m_trt.full(index);
 
-        if(hit_read || !wok || hit_write)    // missing line already requested or no space
+        if(hit_read or !wok or hit_write)    // missing line already requested or no space
         {
           if(!wok)      m_cpt_trt_full++;
-          if(hit_read || hit_write)   m_cpt_trt_rb++;
+          if(hit_read or hit_write)   m_cpt_trt_rb++;
           r_read_fsm = READ_IDLE;
         }
@@ -1792,5 +2170,5 @@
 
 #if DEBUG_MEMC_READ
-if(m_debug_read_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " READ_TRT_LOCK> Check TRT:"
           << " hit_read = " << hit_read
@@ -1820,8 +2198,8 @@
                               r_read_ll_key.read());
 #if DEBUG_MEMC_READ
-if(m_debug_read_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " READ_TRT_SET> Write in Transaction Table:"
           << " address = " << std::hex << m_cmd_read_addr_fifo.read()
-          << " / srcid = " << std::dec << m_cmd_read_srcid_fifo.read() << std::endl;
+          << " / srcid = " << std::hex << m_cmd_read_srcid_fifo.read() << std::endl;
 #endif
         r_read_fsm = READ_TRT_REQ;
@@ -1842,5 +2220,5 @@
 
 #if DEBUG_MEMC_READ
-if(m_debug_read_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " READ_TRT_REQ> Request GET transaction for address "
           << std::hex << m_cmd_read_addr_fifo.read() << std::endl;
@@ -1884,5 +2262,5 @@
   switch(r_write_fsm.read())
   {
-      ////////////////
+    ////////////////
     case WRITE_IDLE:  // copy first word of a write burst in local buffer
     {
@@ -1917,5 +2295,5 @@
         }
 
-        if (m_cmd_write_eop_fifo.read() || ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC))
+        if (m_cmd_write_eop_fifo.read() or ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC))
         {
           r_write_fsm = WRITE_DIR_REQ;
@@ -1927,5 +2305,5 @@
 
 #if DEBUG_MEMC_WRITE
-        if(m_debug_write_fsm)
+        if(m_debug)
         {
           std::cout << "  <MEMC " << name() << " WRITE_IDLE> Write request "
@@ -1946,5 +2324,5 @@
 
 #if DEBUG_MEMC_WRITE
-        if(m_debug_write_fsm)
+        if(m_debug)
         {
           std::cout << "  <MEMC " << name()
@@ -1999,5 +2377,5 @@
           if(not m_cmd_write_addr_fifo.rok()) break;
 
-          assert(m_cmd_write_eop_fifo.read() &&
+          assert(m_cmd_write_eop_fifo.read() and
                  "Error in VCI_MEM_CACHE : "
                  "invalid packet format for SC command");
@@ -2030,5 +2408,5 @@
 
 #if DEBUG_MEMC_WRITE
-      if(m_debug_write_fsm)
+      if(m_debug)
       {
         std::cout
@@ -2065,5 +2443,5 @@
           r_write_way        = way;
 
-          if(entry.is_cnt && entry.count)
+          if(entry.is_cnt and entry.count)
           {
             r_write_fsm = WRITE_DIR_READ;
@@ -2080,5 +2458,5 @@
 
 #if DEBUG_MEMC_WRITE
-        if(m_debug_write_fsm)
+        if(m_debug)
         {
           std::cout << "  <MEMC " << name() << " WRITE_DIR_LOCK> Check the directory: "
@@ -2130,5 +2508,5 @@
 
 #if DEBUG_MEMC_WRITE
-      if(m_debug_write_fsm)
+      if(m_debug)
       {
         std::cout << "  <MEMC " << name() << " WRITE_DIR_READ> Read the cache to complete local buffer" << std::endl;
@@ -2172,5 +2550,6 @@
       // no_update is true when there is no need for coherence transaction
       // (tests for sc requests)
-      bool no_update = ((r_write_count.read() ==0) || (owner && (r_write_count.read() ==1) && (r_write_pktid.read() != TYPE_SC)));
+      bool no_update = ( (r_write_count.read() == 0) or
+                         (owner and (r_write_count.read() ==1) and (r_write_pktid.read() != TYPE_SC)));
 
       // write data in the cache if no coherence transaction
@@ -2205,5 +2584,5 @@
       // coherence update required
       {
-        if(!r_write_to_cc_send_multi_req.read() &&
+        if(!r_write_to_cc_send_multi_req.read() and
            !r_write_to_cc_send_brdcast_req.read())
         {
@@ -2217,20 +2596,20 @@
 
 #if DEBUG_MEMC_WRITE
-      if(m_debug_write_fsm)
-      {
-        if(no_update)
-        {
-          std::cout << "  <MEMC " << name() << " WRITE_DIR_HIT> Write into cache / No coherence transaction"
-                    << std::endl;
-        }
-        else
-        {
-          std::cout << "  <MEMC " << name() << " WRITE_DIR_HIT> Coherence update required:"
-                    << " is_cnt = " << r_write_is_cnt.read()
-                    << " nb_copies = " << std::dec << r_write_count.read() << std::endl;
-          if(owner)
-            std::cout << "       ... but the first copy is the writer" << std::endl;
-        }
-      }
+if(m_debug)
+{
+    if(no_update)
+    {
+        std::cout << "  <MEMC " << name() 
+                  << " WRITE_DIR_HIT> Write into cache / No coherence transaction"
+                  << std::endl;
+    }
+    else
+    {
+        std::cout << "  <MEMC " << name() << " WRITE_DIR_HIT> Coherence update required:"
+                  << " is_cnt = " << r_write_is_cnt.read()
+                  << " nb_copies = " << std::dec << r_write_count.read() << std::endl;
+        if(owner) std::cout << "       ... but the first copy is the writer" << std::endl;
+    }
+}
 #endif
       break;
@@ -2253,12 +2632,13 @@
 
         wok = m_upt.set(true,  // it's an update transaction
-                               false,    // it's not a broadcast
-                               true,     // it needs a response
-                               srcid,
-                               trdid,
-                               pktid,
-                               nline,
-                               nb_copies,
-                               index);
+                        false,    // it's not a broadcast
+                        true,     // response required
+                        false,    // no acknowledge required
+                        srcid,    
+                        trdid,
+                        pktid,
+                        nline,
+                        nb_copies,
+                        index);
         if(wok)       // write data in cache
         {
@@ -2282,12 +2662,13 @@
 
 #if DEBUG_MEMC_WRITE
-        if(m_debug_write_fsm)
-        {
-          if(wok)
-          {
-            std::cout << "  <MEMC " << name() << " WRITE_UPT_LOCK> Register the multicast update in UPT / "
-                      << " nb_copies = " << r_write_count.read() << std::endl;
-          }
-        }
+if(m_debug)
+{
+    if(wok)
+    {
+        std::cout << "  <MEMC " << name() 
+                  << " WRITE_UPT_LOCK> Register the multicast update in UPT / "
+                  << " nb_copies = " << r_write_count.read() << std::endl;
+    }
+}
 #endif
         r_write_upt_index = index;
@@ -2306,8 +2687,7 @@
 
 #if DEBUG_MEMC_WRITE
-        if(m_debug_write_fsm)
-        {
-          std::cout << "  <MEMC " << name() << " WRITE_UPT_HEAP_LOCK> Get acces to the HEAP" << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name() 
+          << " WRITE_UPT_HEAP_LOCK> Get acces to the HEAP" << std::endl;
 #endif
         r_write_fsm = WRITE_UPT_REQ;
@@ -2317,10 +2697,8 @@
 
     //////////////////
-    case WRITE_UPT_REQ:
-    {
-      // prepare the coherence transaction for the CC_SEND FSM
-      // and write the first copy in the FIFO
-      // send the request if only one copy
-
+    case WRITE_UPT_REQ:    // prepare the coherence transaction for the CC_SEND FSM
+                           // and write the first copy in the FIFO
+                           // send the request if only one copy
+    {
       assert(not r_write_to_cc_send_multi_req.read()   and
              not r_write_to_cc_send_brdcast_req.read() and
@@ -2373,5 +2751,5 @@
 
 #if DEBUG_MEMC_WRITE
-      if(m_debug_write_fsm)
+      if(m_debug)
       {
         std::cout
@@ -2404,5 +2782,5 @@
       bool dec_upt_counter;
 
-      if(((entry.owner.srcid != r_write_srcid.read()) || (r_write_pktid.read() == TYPE_SC)) or
+      if(((entry.owner.srcid != r_write_srcid.read()) or (r_write_pktid.read() == TYPE_SC)) or
 #if L1_MULTI_CACHE
           (entry.owner.cache_id != r_write_pktid.read()) or
@@ -2419,5 +2797,5 @@
 
 #if DEBUG_MEMC_WRITE
-        if(m_debug_write_fsm)
+        if(m_debug)
         {
           std::cout << "  <MEMC " << name() << " WRITE_UPT_NEXT> Post another request to CC_SEND FSM"
@@ -2435,5 +2813,5 @@
 
 #if DEBUG_MEMC_WRITE
-        if(m_debug_write_fsm)
+        if(m_debug)
         {
           std::cout << "  <MEMC " << name() << " WRITE_UPT_NEXT> Skip one entry in heap matching the writer"
@@ -2533,5 +2911,5 @@
           }
 
-          if(m_cmd_write_eop_fifo.read() || ((m_cmd_write_pktid_fifo.read() & 0x7)  == TYPE_SC))
+          if(m_cmd_write_eop_fifo.read() or ((m_cmd_write_pktid_fifo.read() & 0x7)  == TYPE_SC))
           {
             r_write_fsm = WRITE_DIR_REQ;
@@ -2548,5 +2926,5 @@
 
 #if DEBUG_MEMC_WRITE
-if(m_debug_write_fsm)
+if(m_debug)
 {
     std::cout << "  <MEMC " << name() << " WRITE_RSP> Post a request to TGT_RSP FSM"
@@ -2572,5 +2950,5 @@
 
 #if DEBUG_MEMC_WRITE
-if(m_debug_write_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " WRITE_MISS_TRT_LOCK> Check the TRT" << std::endl;
 #endif
@@ -2588,5 +2966,5 @@
           m_cpt_write_miss++;
         }
-        else if(wok && !hit_write)      // set a new entry in TRT
+        else if(wok and !hit_write)      // set a new entry in TRT
         {
           r_write_trt_index = wok_index;
@@ -2608,5 +2986,5 @@
 
 #if DEBUG_MEMC_WRITE
-if(m_debug_write_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " WRITE_WAIT> Releases the locks before retry" << std::endl;
 #endif
@@ -2643,5 +3021,5 @@
 
 #if DEBUG_MEMC_WRITE
-if(m_debug_write_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " WRITE_MISS_TRT_SET> Set a new entry in TRT" << std::endl;
 #endif
@@ -2670,5 +3048,5 @@
 
 #if DEBUG_MEMC_WRITE
-if(m_debug_write_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " WRITE_MISS_TRT_DATA> Modify an existing entry in TRT" << std::endl;
 #endif
@@ -2689,5 +3067,5 @@
 
 #if DEBUG_MEMC_WRITE
-if(m_debug_write_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " WRITE_MISS_XRAM_REQ> Post a GET request to the IXR_CMD FSM" << std::endl;
 #endif
@@ -2714,5 +3092,5 @@
 
 #if DEBUG_MEMC_WRITE
-if(m_debug_write_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " WRITE_BC_TRT_LOCK> Check TRT"
           << " : wok = " << wok << " / index = " << wok_index << std::endl;
@@ -2735,16 +3113,17 @@
         size_t      nb_copies = r_write_count.read();
 
-        wok =m_upt.set(false,  // it's an inval transaction
-                              true,     // it's a broadcast
-                              true,     // it needs a response
-                              srcid,
-                              trdid,
-                              pktid,
-                              nline,
-                              nb_copies,
-                              index);
+        wok = m_upt.set(false,  // it's an inval transaction
+                        true,     // it's a broadcast
+                        true,     // response required
+                        false,    // no acknowledge required
+                        srcid,
+                        trdid,
+                        pktid,
+                        nline,
+                        nb_copies,
+                        index);
 
 #if DEBUG_MEMC_WRITE
-if( m_debug_write_fsm and wok )
+if( m_debug and wok )
 std::cout << "  <MEMC " << name() << " WRITE_BC_UPT_LOCK> Register broadcast inval in UPT"
           << " / nb_copies = " << r_write_count.read() << std::endl;
@@ -2763,6 +3142,6 @@
       // Register a put transaction to XRAM in TRT
       // and invalidate the line in directory
-      if((r_alloc_trt_fsm.read() != ALLOC_TRT_WRITE) ||
-          (r_alloc_upt_fsm.read() != ALLOC_UPT_WRITE) ||
+      if((r_alloc_trt_fsm.read() != ALLOC_TRT_WRITE) or
+          (r_alloc_upt_fsm.read() != ALLOC_UPT_WRITE) or
           (r_alloc_dir_fsm.read() != ALLOC_DIR_WRITE))
       {
@@ -2805,5 +3184,5 @@
 
 #if DEBUG_MEMC_WRITE
-if(m_debug_write_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " WRITE_BC_DIR_INVAL> Invalidate the directory entry: @ = "
           << r_write_address.read() << " / register the put transaction in TRT:" << std::endl;
@@ -2816,5 +3195,5 @@
     case WRITE_BC_CC_SEND:    // Post a coherence broadcast request to CC_SEND FSM
     {
-      if(!r_write_to_cc_send_multi_req.read() && !r_write_to_cc_send_brdcast_req.read())
+      if(!r_write_to_cc_send_multi_req.read() and !r_write_to_cc_send_brdcast_req.read())
       {
         r_write_to_cc_send_multi_req   = false;
@@ -2833,9 +3212,7 @@
 
 #if DEBUG_MEMC_WRITE
-if(m_debug_write_fsm)
-{
-    std::cout << "  <MEMC " << name()
-              << " WRITE_BC_CC_SEND> Post a broadcast request to CC_SEND FSM" << std::endl;
-}
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " WRITE_BC_CC_SEND> Post a broadcast request to CC_SEND FSM" << std::endl;
 #endif
       }
@@ -2858,9 +3235,7 @@
 
 #if DEBUG_MEMC_WRITE
-if(m_debug_write_fsm)
-{
-     std::cout << "  <MEMC " << name()
-               << " WRITE_BC_XRAM_REQ> Post a put request to IXR_CMD FSM" << std::endl;
-}
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " WRITE_BC_XRAM_REQ> Post a put request to IXR_CMD FSM" << std::endl;
 #endif
       }
@@ -2934,5 +3309,5 @@
 
 #if DEBUG_MEMC_IXR_CMD
-if(m_debug_ixr_cmd_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " IXR_CMD_READ>"
           << " Send a get request to xram / address = " << std::hex
@@ -2961,5 +3336,5 @@
 
 #if DEBUG_MEMC_IXR_CMD
-if(m_debug_ixr_cmd_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " IXR_CMD_WRITE>"
           << " Send a put request to xram / address = " << std::hex
@@ -2974,5 +3349,5 @@
 
 #if DEBUG_MEMC_IXR_CMD
-if(m_debug_ixr_cmd_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " IXR_CMD_WRITE>"
           << " Send a get request to xram / address = " << std::hex
@@ -3002,5 +3377,5 @@
 
 #if DEBUG_MEMC_IXR_CMD
-if(m_debug_ixr_cmd_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " IXR_CMD_CAS>"
           << " Send a put request to xram / address = " << std::hex
@@ -3015,5 +3390,5 @@
 
 #if DEBUG_MEMC_IXR_CMD
-if(m_debug_ixr_cmd_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " IXR_CMD_CAS>"
           << " Send a get request to xram / address = " << std::hex
@@ -3041,5 +3416,5 @@
 
 #if DEBUG_MEMC_IXR_CMD
-if(m_debug_ixr_cmd_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " IXR_CMD_XRAM>"
           << " Send a put request to xram / address = " << std::hex
@@ -3081,14 +3456,12 @@
         r_ixr_rsp_cpt   = 0;
         r_ixr_rsp_trt_index = p_vci_ixr.rtrdid.read();
-        if(p_vci_ixr.reop.read() && !(p_vci_ixr.rerror.read() &0x1))   // PUT transaction
+        if(p_vci_ixr.reop.read() and !(p_vci_ixr.rerror.read() &0x1))   // PUT transaction
         {
           r_ixr_rsp_fsm = IXR_RSP_ACK;
 
 #if DEBUG_MEMC_IXR_RSP
-if(m_debug_ixr_rsp_fsm)
-{
-    std::cout << "  <MEMC " << name()
-              << " IXR_RSP_IDLE> Response from XRAM to a put transaction" << std::endl;
-}
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " IXR_RSP_IDLE> Response from XRAM to a put transaction" << std::endl;
 #endif
         }
@@ -3098,9 +3471,7 @@
 
 #if DEBUG_MEMC_IXR_RSP
-if(m_debug_ixr_rsp_fsm)
-{
-    std::cout << "  <MEMC " << name()
-              << " IXR_RSP_IDLE> Response from XRAM to a get transaction" << std::endl;
-}
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " IXR_RSP_IDLE> Response from XRAM to a get transaction" << std::endl;
 #endif
         }
@@ -3114,8 +3485,6 @@
 
 #if DEBUG_MEMC_IXR_RSP
-if(m_debug_ixr_rsp_fsm)
-{
-    std::cout << "  <MEMC " << name() << " IXR_RSP_ACK>" << std::endl;
-}
+if(m_debug)
+std::cout << "  <MEMC " << name() << " IXR_RSP_ACK>" << std::endl;
 #endif
       break;
@@ -3130,9 +3499,7 @@
 
 #if DEBUG_MEMC_IXR_RSP
-if(m_debug_ixr_rsp_fsm)
-{
-          std::cout << "  <MEMC " << name() << " IXR_RSP_TRT_ERASE> Erase TRT entry "
-                    << r_ixr_rsp_trt_index.read() << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " IXR_RSP_TRT_ERASE> Erase TRT entry "
+          << r_ixr_rsp_trt_index.read() << std::endl;
 #endif
       }
@@ -3142,5 +3509,5 @@
     case IXR_RSP_TRT_READ:    // write a 64 bits data in the TRT
     {
-      if((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) &&  p_vci_ixr.rspval)
+      if((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) and  p_vci_ixr.rspval)
       {
         size_t      index    = r_ixr_rsp_trt_index.read();
@@ -3149,5 +3516,5 @@
         bool        error    = ((p_vci_ixr.rerror.read() & 0x1) == 1);
 
-        assert(((eop == (r_ixr_rsp_cpt.read() == (m_words-2))) || p_vci_ixr.rerror.read())
+        assert(((eop == (r_ixr_rsp_cpt.read() == (m_words-2))) or p_vci_ixr.rerror.read())
                and "Error in VCI_MEM_CACHE : invalid length for a response from XRAM");
 
@@ -3166,11 +3533,9 @@
 
 #if DEBUG_MEMC_IXR_RSP
-if(m_debug_ixr_rsp_fsm)
-{
-    std::cout << "  <MEMC " << name() << " IXR_RSP_TRT_READ> Writing a word in TRT : "
-              << " index = " << std::dec << index
-              << " / word = " << r_ixr_rsp_cpt.read()
-              << " / data = " << std::hex << data << std::endl;
-}
+if(m_debug)
+std::cout << "  <MEMC " << name() << " IXR_RSP_TRT_READ> Writing a word in TRT : "
+          << " index = " << std::dec << index
+          << " / word = " << r_ixr_rsp_cpt.read()
+          << " / data = " << std::hex << data << std::endl;
 #endif
       }
@@ -3219,5 +3584,5 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-if(m_debug_xram_rsp_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " XRAM_RSP_IDLE>"
           << " Available cache line in TRT:"
@@ -3233,5 +3598,5 @@
                             // Copy the TRT entry in a local buffer
     {
-      if((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) &&
+      if((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and
           (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP))
       {
@@ -3242,9 +3607,6 @@
         r_xram_rsp_fsm = XRAM_RSP_TRT_COPY;
 
-//        TransactionTabEntry trt_entry(m_trt.read(index));
-//        r_xram_rsp_trt_buf.copy(trt_entry);           // TRT entry local buffer
-
 #if DEBUG_MEMC_XRAM_RSP
-if(m_debug_xram_rsp_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " XRAM_RSP_DIR_LOCK>"
           << " Get access to DIR and TRT" << std::endl;
@@ -3266,5 +3628,5 @@
         DirectoryEntry victim(m_cache_directory.select(set, way));
 
-        bool inval = (victim.count && victim.valid) ;
+        bool inval = (victim.count and victim.valid) ;
 
         // copy the victim line in a local buffer
@@ -3296,5 +3658,5 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-if(m_debug_xram_rsp_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " XRAM_RSP_TRT_COPY>"
           << " Select a slot: "
@@ -3323,5 +3685,5 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-if(m_debug_xram_rsp_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL_LOCK>"
           << " Get acces to UPT, but line invalidation registered"
@@ -3331,10 +3693,10 @@
 
         }
-        else if(m_upt.is_full() && r_xram_rsp_victim_inval.read()) // UPT full
+        else if(m_upt.is_full() and r_xram_rsp_victim_inval.read()) // UPT full
         {
           r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
 
 #if DEBUG_MEMC_XRAM_RSP
-if(m_debug_xram_rsp_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL_LOCK>"
           << " Get acces to UPT, but inval required and UPT full" << std::endl;
@@ -3346,5 +3708,5 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-if(m_debug_xram_rsp_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL_LOCK>"
           << " Get acces to UPT" << std::endl;
@@ -3359,5 +3721,5 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-if(m_debug_xram_rsp_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL_WAIT>"
           << " Release all locks and retry" << std::endl;
@@ -3373,10 +3735,10 @@
       // TYPE_READ_INS_UNC   0bX010 with TSAR encoding
       // TYPE_READ_INS_MISS  0bX011 with TSAR encoding
-      bool inst_read = (r_xram_rsp_trt_buf.pktid & 0x2) && r_xram_rsp_trt_buf.proc_read;
+      bool inst_read = (r_xram_rsp_trt_buf.pktid & 0x2) and r_xram_rsp_trt_buf.proc_read;
 
       // check if this is a cached read, this means pktid is either
       // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding
       // TYPE_READ_INS_MISS  0bX011 with TSAR encoding
-      bool cached_read = (r_xram_rsp_trt_buf.pktid & 0x1) && r_xram_rsp_trt_buf.proc_read;
+      bool cached_read = (r_xram_rsp_trt_buf.pktid & 0x1) and r_xram_rsp_trt_buf.proc_read;
 
       bool dirty = false;
@@ -3389,5 +3751,5 @@
         m_cache_data.write(way, set, word, r_xram_rsp_trt_buf.wdata[word]);
 
-        dirty = dirty || (r_xram_rsp_trt_buf.wdata_be[word] != 0);
+        dirty = dirty or (r_xram_rsp_trt_buf.wdata_be[word] != 0);
 
         if(m_monitor_ok)
@@ -3435,5 +3797,6 @@
         bool   wok = m_upt.set(false,      // it's an inval transaction
                                broadcast,  // set broadcast bit
-                               false,      // it does not need a response
+                               false,      // no response required 
+                               false,      // no acknowledge required 
                                0,          // srcid
                                0,          // trdid
@@ -3454,5 +3817,5 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-if(m_debug_xram_rsp_fsm)
+if(m_debug)
 {
 std::cout << "  <MEMC " << name() << " XRAM_RSP_DIR_UPDT>"
@@ -3500,5 +3863,5 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-if(m_debug_xram_rsp_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " XRAM_RSP_TRT_DIRTY>"
           << " Set TRT entry for the put transaction"
@@ -3534,5 +3897,5 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-if(m_debug_xram_rsp_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " XRAM_RSP_DIR_RSP>"
           << " Request the TGT_RSP FSM to return data:"
@@ -3547,10 +3910,10 @@
     case XRAM_RSP_INVAL:  // send invalidate request to CC_SEND FSM
     {
-      if(!r_xram_rsp_to_cc_send_multi_req.read() &&
+      if(!r_xram_rsp_to_cc_send_multi_req.read() and
           !r_xram_rsp_to_cc_send_brdcast_req.read())
       {
         bool multi_req = !r_xram_rsp_victim_is_cnt.read();
-        bool last_multi_req  = multi_req && (r_xram_rsp_victim_count.read() == 1);
-        bool not_last_multi_req = multi_req && (r_xram_rsp_victim_count.read() != 1);
+        bool last_multi_req  = multi_req and (r_xram_rsp_victim_count.read() == 1);
+        bool not_last_multi_req = multi_req and (r_xram_rsp_victim_count.read() != 1);
 
         r_xram_rsp_to_cc_send_multi_req    = last_multi_req;
@@ -3571,5 +3934,5 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-if(m_debug_xram_rsp_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL>"
           << " Send an inval request to CC_SEND FSM"
@@ -3593,6 +3956,6 @@
         m_cpt_write_dirty++;
 
-        bool multi_req = !r_xram_rsp_victim_is_cnt.read() && r_xram_rsp_victim_inval.read();
-        bool not_last_multi_req = multi_req && (r_xram_rsp_victim_count.read() != 1);
+        bool multi_req = !r_xram_rsp_victim_is_cnt.read() and r_xram_rsp_victim_inval.read();
+        bool not_last_multi_req = multi_req and (r_xram_rsp_victim_count.read() != 1);
 
         if(not_last_multi_req)   r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ;
@@ -3600,5 +3963,5 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-if(m_debug_xram_rsp_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " XRAM_RSP_WRITE_DIRTY>"
           << " Send the put request to IXR_CMD FSM"
@@ -3617,5 +3980,5 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-if(m_debug_xram_rsp_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " XRAM_RSP_HEAP_REQ>"
           << " Requesting HEAP lock" << std::endl;
@@ -3655,8 +4018,8 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-if(m_debug_xram_rsp_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " XRAM_RSP_HEAP_ERASE>"
           << " Erase copy:"
-          << " srcid = " << std::dec << entry.owner.srcid
+          << " srcid = " << std::hex << entry.owner.srcid
           << " / inst = " << std::dec << entry.owner.inst << std::endl;
 #endif
@@ -3697,5 +4060,5 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-if(m_debug_xram_rsp_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " XRAM_RSP_HEAP_LAST>"
           << " Heap housekeeping" << std::endl;
@@ -3713,5 +4076,5 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-if(m_debug_xram_rsp_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " XRAM_RSP_ERROR_ERASE>"
           << " Error reported by XRAM / erase the TRT entry" << std::endl;
@@ -3739,8 +4102,8 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-if(m_debug_xram_rsp_fsm)
-    std::cout << "  <MEMC " << name()
-              << " XRAM_RSP_ERROR_RSP> Request a response error to TGT_RSP FSM:"
-              << " srcid = " << std::dec << r_xram_rsp_trt_buf.srcid << std::endl;
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " XRAM_RSP_ERROR_RSP> Request a response error to TGT_RSP FSM:"
+          << " srcid = " << std::dec << r_xram_rsp_trt_buf.srcid << std::endl;
 #endif
       }
@@ -3803,13 +4166,9 @@
 
 #if DEBUG_MEMC_CLEANUP
-      if(m_debug_cleanup_fsm)
-      {
-        std::cout
-            << "  <MEMC "         << name()
-            << " CLEANUP_IDLE> Cleanup request:" << std::hex
-            << " / owner_id = "   << srcid
-            << " / owner_ins = "  << (type == DspinDhccpParam::TYPE_CLEANUP_INST)
-            << std::endl;
-      }
+if(m_debug)
+std::cout << "  <MEMC "         << name()
+          << " CLEANUP_IDLE> Cleanup request:" << std::hex
+          << " / owner_id = "   << srcid
+          << " / owner_ins = "  << (type == DspinDhccpParam::TYPE_CLEANUP_INST) << std::endl;
 #endif
       break;
@@ -3831,13 +4190,8 @@
 
 #if DEBUG_MEMC_CLEANUP
-      if(m_debug_cleanup_fsm)
-      {
-        std::cout
-            << "  <MEMC "         << name()
-            << " CLEANUP_GET_NLINE> Cleanup request:"
-            << std::hex
-            << " / address = "    << nline * m_words * 4
-            << std::endl;
-      }
+if(m_debug)
+std::cout << "  <MEMC "         << name()
+          << " CLEANUP_GET_NLINE> Cleanup request:"
+          << " / address = " << std::hex << nline * m_words * 4 << std::endl;
 #endif
       break;
@@ -3845,7 +4199,6 @@
 
     /////////////////////
-    case CLEANUP_DIR_REQ:
-    {
-      // Get the lock to the directory
+    case CLEANUP_DIR_REQ:   // Get the lock to the directory
+    {
       if(r_alloc_dir_fsm.read() != ALLOC_DIR_CLEANUP) break;
 
@@ -3853,10 +4206,6 @@
 
 #if DEBUG_MEMC_CLEANUP
-      if(m_debug_cleanup_fsm)
-      {
-        std::cout
-            << "  <MEMC " << name() << " CLEANUP_DIR_REQ> Requesting DIR lock "
-            << std::endl;
-      }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CLEANUP_DIR_REQ> Requesting DIR lock" << std::endl;
 #endif
       break;
@@ -3895,10 +4244,8 @@
 #endif
 
-      // hit :
-      // the copy must be cleared
-      if(entry.valid)
+      if(entry.valid)      // hit : the copy must be cleared
       {
         assert(
-            (entry.count > 0) &&
+            (entry.count > 0) and
             "VCI MEM CACHE ERROR: "
             "In CLEANUP_DIR_LOCK, CLEANUP command on a valid entry "
@@ -3906,5 +4253,5 @@
 
         // no access to the heap
-        if((entry.count == 1) || (entry.is_cnt))
+        if((entry.count == 1) or (entry.is_cnt))
         {
           r_cleanup_fsm = CLEANUP_DIR_WRITE;
@@ -3916,8 +4263,5 @@
         }
       }
-      // miss :
-      // we must check the update table for a pending
-      // invalidation transaction
-      else
+      else                // miss : check UPT for a pending invalidation transaction
       {
         r_cleanup_fsm = CLEANUP_UPT_LOCK;
@@ -3925,5 +4269,5 @@
 
 #if DEBUG_MEMC_CLEANUP
-      if(m_debug_cleanup_fsm)
+      if(m_debug)
       {
         std::cout
@@ -3968,5 +4312,5 @@
 
       bool   match_inst  = (r_cleanup_copy_inst.read() == r_cleanup_inst.read());
-      bool   match       = match_srcid && match_inst;
+      bool   match       = match_srcid and match_inst;
 
       if(not r_cleanup_is_cnt.read() and not match)
@@ -3999,8 +4343,8 @@
       m_cache_directory.write(set, way, entry);
 
-      r_cleanup_fsm = CLEANUP_SEND_ACK;
+      r_cleanup_fsm = CLEANUP_SEND_CLACK;
 
 #if DEBUG_MEMC_CLEANUP
-      if(m_debug_cleanup_fsm)
+      if(m_debug)
       {
         std::cout
@@ -4029,5 +4373,5 @@
 
 #if DEBUG_MEMC_CLEANUP
-      if(m_debug_cleanup_fsm)
+      if(m_debug)
       {
         std::cout
@@ -4182,5 +4526,5 @@
 
 #if DEBUG_MEMC_CLEANUP
-      if(m_debug_cleanup_fsm)
+      if(m_debug)
       {
         std::cout
@@ -4220,5 +4564,5 @@
       bool match_heap_srcid = (heap_entry.owner.srcid == r_cleanup_srcid.read());
       bool match_heap_inst  = (heap_entry.owner.inst  == r_cleanup_inst.read());
-      bool match_heap       = match_heap_srcid && match_heap_inst;
+      bool match_heap       = match_heap_srcid and match_heap_inst;
 
 #if L1_MULTI_CACHE
@@ -4260,5 +4604,5 @@
 
 #if DEBUG_MEMC_CLEANUP
-      if(m_debug_cleanup_fsm)
+      if(m_debug)
       {
         if(not match_heap)
@@ -4289,8 +4633,7 @@
       break;
     }
-
-    case CLEANUP_HEAP_CLEAN:
-    {
-      // remove a copy in the linked list
+    ////////////////////////
+    case CLEANUP_HEAP_CLEAN:    // remove a copy in the linked list
+    {
       if(r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP)
       {
@@ -4329,19 +4672,14 @@
 
 #if DEBUG_MEMC_CLEANUP
-      if(m_debug_cleanup_fsm)
-      {
-        std::cout
-            << "  <MEMC " << name()
-            << " CLEANUP_HEAP_SEARCH> Remove the copy in the linked list"
-            << std::endl;
-      }
-#endif
-      break;
-    }
-
-    case CLEANUP_HEAP_FREE:
-    {
-      // The heap entry pointed by r_cleanup_next_ptr is freed
-      // and becomes the head of the list of free entries
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CLEANUP_HEAP_SEARCH>"
+          << " Remove the copy in the linked list" << std::endl;
+#endif
+      break;
+    }
+    ///////////////////////
+    case CLEANUP_HEAP_FREE:   // The heap entry pointed by r_cleanup_next_ptr is freed
+                              // and becomes the head of the list of free entries
+    {
       if(r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP)
       {
@@ -4375,22 +4713,17 @@
       m_heap.unset_full();
 
-      r_cleanup_fsm = CLEANUP_SEND_ACK;
+      r_cleanup_fsm = CLEANUP_SEND_CLACK;
 
 #if DEBUG_MEMC_CLEANUP
-      if(m_debug_cleanup_fsm)
-      {
-        std::cout
-            << "  <MEMC " << name()
-            << " CLEANUP_HEAP_SEARCH> Update the list of free entries"
-            << std::endl;
-      }
-#endif
-      break;
-    }
-
-    case CLEANUP_UPT_LOCK:
-    {
-      // search pending invalidate transaction matching the Cleanup NLINE in the UPDATE TABLE
-      // get the lock in the UPDATE_TABLE
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CLEANUP_HEAP_FREE>"
+          << " Update the list of free entries" << std::endl;
+#endif
+      break;
+    }
+    //////////////////////
+    case CLEANUP_UPT_LOCK:   // get the lock protecting the UPT to search a pending
+                             // invalidate transaction matching the cleanup 
+    {
       if(r_alloc_upt_fsm.read() != ALLOC_UPT_CLEANUP) break;
 
@@ -4400,52 +4733,43 @@
       match_inval = m_upt.search_inval(r_cleanup_nline.read(), index);
 
-      // no pending inval
-      if(not match_inval)
-      {
-        r_cleanup_fsm = CLEANUP_SEND_ACK;
+      if ( not match_inval )     // no pending inval
+      {
+          r_cleanup_fsm = CLEANUP_SEND_CLACK;
 
 #if DEBUG_MEMC_CLEANUP
-        if(m_debug_cleanup_fsm)
-        {
-          std::cout
-              << "  <MEMC " << name()
-              << " CLEANUP_UPT_LOCK> Unexpected cleanup"
-              << " with no corresponding UPT entry:"
-              << " address = " << std::hex
-              << (r_cleanup_nline.read() *4*m_words)
-              << std::endl;
-        }
-#endif
-        break;
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " CLEANUP_UPT_LOCK> Unexpected cleanup"
+          << " with no corresponding UPT entry:"
+          << " address = " << std::hex
+          << (r_cleanup_nline.read() *4*m_words)
+          << std::endl;
+#endif
+          break;
       }
 
       // pending inval
-      r_cleanup_write_srcid    = m_upt.srcid(index);
-      r_cleanup_write_trdid    = m_upt.trdid(index);
-      r_cleanup_write_pktid    = m_upt.pktid(index);
-      r_cleanup_write_need_rsp = m_upt.need_rsp(index);
-      r_cleanup_index          = index;
+      r_cleanup_write_srcid = m_upt.srcid(index);
+      r_cleanup_write_trdid = m_upt.trdid(index);
+      r_cleanup_write_pktid = m_upt.pktid(index);
+      r_cleanup_need_rsp    = m_upt.need_rsp(index);
+      r_cleanup_need_ack    = m_upt.need_ack(index);
+      r_cleanup_index       = index;
 
       r_cleanup_fsm         = CLEANUP_UPT_DECREMENT;
 
 #if DEBUG_MEMC_CLEANUP
-      if(m_debug_cleanup_fsm)
-      {
-        std::cout
-            << "  <MEMC " << name()
-            << " CLEANUP_UPT_LOCK> Cleanup matching pending"
-            << " invalidate transaction on UPT:"
-            << std::hex
-            << " address = "   << r_cleanup_nline.read() * m_words * 4
-            << " upt_entry = " << index
-            << std::endl;
-      }
-#endif
-      break;
-    }
-
-    case CLEANUP_UPT_DECREMENT:
-    {
-      // decrement response counter in UPT matching entry
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " CLEANUP_UPT_LOCK> Cleanup matching pending"
+          << " invalidate transaction on UPT:"
+          << " address = " << std::hex << r_cleanup_nline.read() * m_words * 4
+          << " / upt_entry = " << index << std::endl;
+#endif
+      break;
+    }
+    ///////////////////////////
+    case CLEANUP_UPT_DECREMENT:   // decrement response counter in UPT matching entry
+    {
       if(r_alloc_upt_fsm.read() != ALLOC_UPT_CLEANUP)
       {
@@ -4462,33 +4786,25 @@
       m_upt.decrement(r_cleanup_index.read(), count);
 
-      // invalidation transaction finished
-      // (all acknowledgements received)
-      if(count == 0)
+      if(count == 0)   // multi inval transaction completed
       {
         r_cleanup_fsm = CLEANUP_UPT_CLEAR;
       }
-      // invalidation transaction not finished
-      else
-      {
-        r_cleanup_fsm = CLEANUP_SEND_ACK ;
+      else             // multi inval transaction not completed
+      {
+        r_cleanup_fsm = CLEANUP_SEND_CLACK ;
       }
 
 #if DEBUG_MEMC_CLEANUP
-      if(m_debug_cleanup_fsm)
-      {
-        std::cout
-            << "  <MEMC "      << name()
-            << " CLEANUP_UPT_DECREMENT> Decrement response counter in UPT:"
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CLEANUP_UPT_DECREMENT>"
+          << " Decrement response counter in UPT:"
             << " UPT_index = " << r_cleanup_index.read()
-            << " rsp_count = " << count
-            << std::endl;
-      }
-#endif
-      break;
-    }
-
-    case CLEANUP_UPT_CLEAR:
-    {
-      // Clear UPT entry of finished invalidation transaction
+            << " / rsp_count = " << count << std::endl;
+#endif
+      break;
+    }
+    ///////////////////////
+    case CLEANUP_UPT_CLEAR:    // Clear UPT entry 
+    {
       if(r_alloc_upt_fsm.read() != ALLOC_UPT_CLEANUP)
       {
@@ -4504,30 +4820,20 @@
       m_upt.clear(r_cleanup_index.read());
 
-      if(r_cleanup_write_need_rsp.read())
-      {
-        r_cleanup_fsm = CLEANUP_WRITE_RSP;
-      }
-      else
-      {
-        r_cleanup_fsm = CLEANUP_SEND_ACK;
-      }
+      if      ( r_cleanup_need_rsp.read() ) r_cleanup_fsm = CLEANUP_WRITE_RSP;
+      else if ( r_cleanup_need_ack.read() ) r_cleanup_fsm = CLEANUP_CONFIG_ACK;
+      else                                  r_cleanup_fsm = CLEANUP_SEND_CLACK;
 
 #if DEBUG_MEMC_CLEANUP
-      if(m_debug_cleanup_fsm)
-      {
-        std::cout
-            << "  <MEMC "      << name()
-            << " CLEANUP_UPT_CLEAR> Clear entry in UPT:"
-            << " UPT_index = " << r_cleanup_index.read()
-            << std::endl;
-      }
-#endif
-      break;
-    }
-
-    case CLEANUP_WRITE_RSP:
-    {
-      // response to a previous write on the direct network
-      // wait if pending request to the TGT_RSP FSM
+if(m_debug)
+std::cout << "  <MEMC "      << name()
+          << " CLEANUP_UPT_CLEAR> Clear entry in UPT:"
+          << " UPT_index = " << r_cleanup_index.read() << std::endl;
+#endif
+      break;
+    }
+    ///////////////////////
+    case CLEANUP_WRITE_RSP:    // response to a previous write on the direct network
+                               // wait if pending request to the TGT_RSP FSM
+    {
       if(r_cleanup_to_tgt_rsp_req.read()) break;
 
@@ -4538,26 +4844,37 @@
       r_cleanup_to_tgt_rsp_pktid   = r_cleanup_write_pktid.read();
 
-      r_cleanup_fsm                = CLEANUP_SEND_ACK;
+      r_cleanup_fsm                = CLEANUP_SEND_CLACK;
 
 #if DEBUG_MEMC_CLEANUP
-      if(m_debug_cleanup_fsm)
-      {
-        std::cout
-            << "  <MEMC " << name()
-            << " CLEANUP_WRITE_RSP> Send a response to a previous"
-            << " write request waiting for coherence transaction completion: "
-            << " rsrcid = "   << std::hex << r_cleanup_write_srcid.read()
-            << " / rtrdid = " << std::hex << r_cleanup_write_trdid.read()
-            << std::endl;
-      }
-#endif
-      break;
-    }
-
-    case CLEANUP_SEND_ACK:
-    {
-      // acknowledgement to a cleanup command
-      // on the coherence network (request to the CC_SEND FSM).
-      // wait if pending request to the CC_SEND FSM
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CLEANUP_WRITE_RSP>"
+          << " Send a response to a previous write request: "
+          << " rsrcid = "   << std::hex << r_cleanup_write_srcid.read()
+          << " / rtrdid = " << r_cleanup_write_trdid.read()
+          << " / rpktid = " << r_cleanup_write_pktid.read() << std::endl;
+#endif
+      break;
+    }
+    ////////////////////////
+    case CLEANUP_CONFIG_ACK:   // signals inval completion to CONFIG FSM
+                               // wait if pending request
+    {
+      if ( r_cleanup_to_config_ack.read() ) break;
+
+      r_cleanup_to_config_ack      = true;
+      r_cleanup_fsm                = CLEANUP_SEND_CLACK;
+
+#if DEBUG_MEMC_CLEANUP
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CLEANUP_CONFIG_ACK>"
+          << " Acknowledge broacast inval completion" << std::endl;
+#endif
+      break;
+    }
+    ////////////////////////
+    case CLEANUP_SEND_CLACK:    // acknowledgement to a cleanup command
+                              // on the coherence network (request to the CC_SEND FSM).
+                              // wait if pending request to the CC_SEND FSM
+    {
       if(r_cleanup_to_cc_send_req.read()) break;
 
@@ -4571,12 +4888,8 @@
 
 #if DEBUG_MEMC_CLEANUP
-      if(m_debug_cleanup_fsm)
-      {
-        std::cout
-            << "  <MEMC " << name()
-            << " CLEANUP_SEND_ACK> Send the response to a cleanup request:"
-            << " srcid = " << std::dec << r_cleanup_srcid.read()
-            << std::endl;
-      }
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " CLEANUP_SEND_CLACK> Send the response to a cleanup request:"
+          << " srcid = " << std::dec << r_cleanup_srcid.read() << std::endl;
 #endif
       break;
@@ -4618,5 +4931,5 @@
 
 #if DEBUG_MEMC_CAS
-        if(m_debug_cas_fsm)
+        if(m_debug)
         {
           std::cout << "  <MEMC " << name() << " CAS_IDLE> CAS command: " << std::hex
@@ -4641,5 +4954,5 @@
           r_cas_rdata[r_cas_cpt.read()] = m_cmd_cas_wdata_fifo.read();
 
-        if((r_cas_cpt.read() == 1) && m_cmd_cas_eop_fifo.read())
+        if((r_cas_cpt.read() == 1) and m_cmd_cas_eop_fifo.read())
           r_cas_wdata = m_cmd_cas_wdata_fifo.read();
 
@@ -4668,5 +4981,5 @@
 
 #if DEBUG_MEMC_CAS
-      if(m_debug_cas_fsm)
+      if(m_debug)
       {
         std::cout
@@ -4702,5 +5015,5 @@
 
 #if DEBUG_MEMC_CAS
-        if(m_debug_cas_fsm)
+        if(m_debug)
         {
           std::cout << "  <MEMC " << name() << " CAS_DIR_LOCK> Directory acces"
@@ -4754,5 +5067,5 @@
 
 #if DEBUG_MEMC_CAS
-if(m_debug_cas_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " CAS_DIR_HIT_READ> Read data from "
           << " cache and store it in buffer" << std::endl;
@@ -4772,5 +5085,5 @@
 
       // to avoid livelock, force the atomic access to fail pseudo-randomly
-      bool forced_fail = ((r_cas_lfsr % (64) == 0) && RANDOMIZE_CAS);
+      bool forced_fail = ((r_cas_lfsr % (64) == 0) and RANDOMIZE_CAS);
       r_cas_lfsr = (r_cas_lfsr >> 1) ^ ((- (r_cas_lfsr & 1)) & 0xd0000001);
 
@@ -4787,5 +5100,5 @@
 
 #if DEBUG_MEMC_CAS
-if(m_debug_cas_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " CAS_DIR_HIT_COMPARE> Compare the old"
           << " and the new data"
@@ -4810,5 +5123,5 @@
           r_cas_fsm = CAS_BC_TRT_LOCK;    // broadcast invalidate required
         }
-        else if(!r_cas_to_cc_send_multi_req.read() &&
+        else if(!r_cas_to_cc_send_multi_req.read() and
                 !r_cas_to_cc_send_brdcast_req.read())
         {
@@ -4847,5 +5160,5 @@
 
 #if DEBUG_MEMC_CAS
-if(m_debug_cas_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " CAS_DIR_HIT_WRITE> Update cache:"
           << " way = " << std::dec << way
@@ -4874,13 +5187,14 @@
         size_t      nb_copies  = r_cas_count.read();
 
-        wok = m_upt.set(true,  // it's an update transaction
-                               false,   // it's not a broadcast
-                               true,    // it needs a response
-                               srcid,
-                               trdid,
-                               pktid,
-                               nline,
-                               nb_copies,
-                               index);
+        wok = m_upt.set(true,    // it's an update transaction
+                        false,   // it's not a broadcast
+                        true,    // response required  
+                        false,   // no acknowledge required
+                        srcid,
+                        trdid,
+                        pktid,
+                        nline,
+                        nb_copies,
+                        index);
         if(wok)   // coherence transaction registered in UPT
         {
@@ -4916,5 +5230,5 @@
 
 #if DEBUG_MEMC_CAS
-if(m_debug_cas_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name()
           << " CAS_UPT_LOCK> Register multi-update transaction in UPT"
@@ -4931,5 +5245,5 @@
 
 #if DEBUG_MEMC_CAS
-      if(m_debug_cas_fsm)
+      if(m_debug)
       {
         std::cout << "  <MEMC " << name()
@@ -4947,5 +5261,5 @@
 
 #if DEBUG_MEMC_CAS
-        if(m_debug_cas_fsm)
+        if(m_debug)
         {
           std::cout << "  <MEMC " << name()
@@ -4963,5 +5277,5 @@
              "VCI_MEM_CACHE ERROR : bad HEAP allocation");
 
-      if(!r_cas_to_cc_send_multi_req.read() && !r_cas_to_cc_send_brdcast_req.read())
+      if(!r_cas_to_cc_send_multi_req.read() and !r_cas_to_cc_send_brdcast_req.read())
       {
         r_cas_to_cc_send_brdcast_req  = false;
@@ -5003,5 +5317,5 @@
 
 #if DEBUG_MEMC_CAS
-        if(m_debug_cas_fsm)
+        if(m_debug)
         {
           std::cout << "  <MEMC " << name() << " CAS_UPT_REQ> Send the first update request to CC_SEND FSM "
@@ -5043,5 +5357,5 @@
 
 #if DEBUG_MEMC_CAS
-      if(m_debug_cas_fsm)
+      if(m_debug)
       {
         std::cout << "  <MEMC " << name() << " CAS_UPT_NEXT> Send the next update request to CC_SEND FSM "
@@ -5069,5 +5383,5 @@
               r_cas_to_ixr_cmd_data[i] = r_cas_wdata.read();
             }
-            else if((i == word+1) && (r_cas_cpt.read() == 4))   // 64 bit CAS
+            else if((i == word+1) and (r_cas_cpt.read() == 4))   // 64 bit CAS
             {
               r_cas_to_ixr_cmd_data[i] = m_cmd_cas_wdata_fifo.read();
@@ -5113,12 +5427,13 @@
         // register a broadcast inval transaction in UPT
         wok = m_upt.set(false,  // it's an inval transaction
-                               true,    // it's a broadcast
-                               true,    // it needs a response
-                               srcid,
-                               trdid,
-                               pktid,
-                               nline,
-                               nb_copies,
-                               index);
+                        true,    // it's a broadcast
+                        true,    // response required
+                        false,   // no acknowledge required
+                        srcid,
+                        trdid,
+                        pktid,
+                        nline,
+                        nb_copies,
+                        index);
 
         if(wok)     // UPT not full
@@ -5148,5 +5463,5 @@
 
 #if DEBUG_MEMC_CAS
-if(m_debug_cas_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name()
           << " CAS_BC_UPT_LOCK> Register a broadcast inval transaction in UPT"
@@ -5166,6 +5481,6 @@
     case CAS_BC_DIR_INVAL:  // Register the PUT transaction in TRT, and inval the DIR entry
     {
-      if((r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) &&
-          (r_alloc_upt_fsm.read() == ALLOC_UPT_CAS) &&
+      if((r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and
+          (r_alloc_upt_fsm.read() == ALLOC_UPT_CAS) and
           (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS))
       {
@@ -5204,5 +5519,5 @@
 
 #if DEBUG_MEMC_CAS
-if(m_debug_cas_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name()
           << " CAS_BC_DIR_INVAL> Register the PUT in TRT and invalidate DIR entry"
@@ -5220,5 +5535,5 @@
     case CAS_BC_CC_SEND:  // Request the broadcast inval to CC_SEND FSM
     {
-      if(!r_cas_to_cc_send_multi_req.read() &&
+      if(!r_cas_to_cc_send_multi_req.read() and
           !r_cas_to_cc_send_brdcast_req.read())
       {
@@ -5248,5 +5563,5 @@
 
 #if DEBUG_MEMC_CAS
-if(m_debug_cas_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name()
           << " CAS_BC_XRAM_REQ> Request a PUT transaction to IXR_CMD FSM" << std::hex
@@ -5277,5 +5592,5 @@
 
 #if DEBUG_MEMC_CAS
-if(m_debug_cas_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name()
           << " CAS_RSP_FAIL> Request TGT_RSP to send a failure response" << std::endl;
@@ -5299,5 +5614,5 @@
 
 #if DEBUG_MEMC_CAS
-if(m_debug_cas_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name()
           << " CAS_RSP_SUCCESS> Request TGT_RSP to send a success response" << std::endl;
@@ -5319,5 +5634,5 @@
 
 #if DEBUG_MEMC_CAS
-        if(m_debug_cas_fsm)
+        if(m_debug)
         {
           std::cout << "  <MEMC " << name() << " CAS_MISS_TRT_LOCK> Check TRT state"
@@ -5329,5 +5644,5 @@
 #endif
 
-        if(hit_read || !wok || hit_write)    // missing line already requested or no space in TRT
+        if(hit_read or !wok or hit_write)    // missing line already requested or no space in TRT
         {
           r_cas_fsm = CAS_WAIT;
@@ -5370,5 +5685,5 @@
 
 #if DEBUG_MEMC_CAS
-        if(m_debug_cas_fsm)
+        if(m_debug)
         {
           std::cout << "  <MEMC " << name() << " CAS_MISS_TRT_SET> Register a GET transaction in TRT" << std::hex
@@ -5392,5 +5707,5 @@
 
 #if DEBUG_MEMC_CAS
-        if(m_debug_cas_fsm)
+        if(m_debug)
         {
           std::cout << "  <MEMC " << name() << " CAS_MISS_XRAM_REQ> Request a GET transaction to IXR_CMD FSM" << std::hex
@@ -5438,5 +5753,5 @@
       {
         // XRAM_RSP FSM has highest priority
-        if(m_xram_rsp_to_cc_send_inst_fifo.rok() ||
+        if(m_xram_rsp_to_cc_send_inst_fifo.rok() or
             r_xram_rsp_to_cc_send_multi_req.read())
         {
@@ -5453,5 +5768,5 @@
         }
 
-        if(m_cas_to_cc_send_inst_fifo.rok() ||
+        if(m_cas_to_cc_send_inst_fifo.rok() or
             r_cas_to_cc_send_multi_req.read())
         {
@@ -5474,5 +5789,5 @@
         }
 
-        if(m_write_to_cc_send_inst_fifo.rok() ||
+        if(m_write_to_cc_send_inst_fifo.rok() or
             r_write_to_cc_send_multi_req.read())
         {
@@ -5493,5 +5808,5 @@
       {
         // CAS FSM has highest priority
-        if(m_cas_to_cc_send_inst_fifo.rok() ||
+        if(m_cas_to_cc_send_inst_fifo.rok() or
             r_cas_to_cc_send_multi_req.read())
         {
@@ -5514,5 +5829,5 @@
         }
 
-        if(m_write_to_cc_send_inst_fifo.rok() ||
+        if(m_write_to_cc_send_inst_fifo.rok() or
             r_write_to_cc_send_multi_req.read())
         {
@@ -5529,5 +5844,5 @@
         }
 
-        if(m_xram_rsp_to_cc_send_inst_fifo.rok() ||
+        if(m_xram_rsp_to_cc_send_inst_fifo.rok() or
             r_xram_rsp_to_cc_send_multi_req.read())
         {
@@ -5555,5 +5870,5 @@
         }
 
-        if(m_write_to_cc_send_inst_fifo.rok() ||
+        if(m_write_to_cc_send_inst_fifo.rok() or
             r_write_to_cc_send_multi_req.read())
         {
@@ -5570,5 +5885,5 @@
         }
 
-        if(m_xram_rsp_to_cc_send_inst_fifo.rok() ||
+        if(m_xram_rsp_to_cc_send_inst_fifo.rok() or
             r_xram_rsp_to_cc_send_multi_req.read())
         {
@@ -5585,5 +5900,5 @@
         }
 
-        if(m_cas_to_cc_send_inst_fifo.rok() ||
+        if(m_cas_to_cc_send_inst_fifo.rok() or
             r_cas_to_cc_send_multi_req.read())
         {
@@ -5604,5 +5919,5 @@
       {
         // WRITE FSM has highest priority
-        if(m_write_to_cc_send_inst_fifo.rok() ||
+        if(m_write_to_cc_send_inst_fifo.rok() or
             r_write_to_cc_send_multi_req.read())
         {
@@ -5619,5 +5934,5 @@
         }
 
-        if(m_xram_rsp_to_cc_send_inst_fifo.rok() ||
+        if(m_xram_rsp_to_cc_send_inst_fifo.rok() or
             r_xram_rsp_to_cc_send_multi_req.read())
         {
@@ -5634,5 +5949,5 @@
         }
 
-        if(m_cas_to_cc_send_inst_fifo.rok() ||
+        if(m_cas_to_cc_send_inst_fifo.rok() or
             r_cas_to_cc_send_multi_req.read())
         {
@@ -5666,5 +5981,5 @@
 
 #if DEBUG_MEMC_CC_SEND
-if(m_debug_cc_send_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name()
           << " CC_SEND_CLEANUP_ACK> Cleanup Ack for srcid "
@@ -5705,5 +6020,5 @@
 
 #if DEBUG_MEMC_CC_SEND
-if(m_debug_cc_send_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name()
           << " CC_SEND_XRAM_RSP_INVAL_NLINE> BC-Inval for line "
@@ -5733,5 +6048,5 @@
 
 #if DEBUG_MEMC_CC_SEND
-if(m_debug_cc_send_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name()
           << " CC_SEND_XRAM_RSP_BRDCAST_NLINE> BC-Inval for line "
@@ -5761,5 +6076,5 @@
 
 #if DEBUG_MEMC_CC_SEND
-if(m_debug_cc_send_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name()
           << " CC_SEND_WRITE_BRDCAST_NLINE> BC-Inval for line "
@@ -5800,5 +6115,5 @@
 
 #if DEBUG_MEMC_CC_SEND
-        if(m_debug_cc_send_fsm)
+        if(m_debug)
         {
           std::cout
@@ -5848,5 +6163,5 @@
 
 #if DEBUG_MEMC_CC_SEND
-        if(m_debug_cc_send_fsm)
+        if(m_debug)
         {
           std::cout
@@ -5892,12 +6207,8 @@
 
 #if DEBUG_MEMC_CC_SEND
-        if(m_debug_cc_send_fsm)
-        {
-          std::cout
-            << "  <MEMC " << name()
-            << " CC_SEND_CAS_UPDT_NLINE> Multicast-Update for line "
-            << r_cas_to_cc_send_nline.read()
-            << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " CC_SEND_CAS_UPDT_NLINE> Multicast-Update for line "
+          << r_cas_to_cc_send_nline.read() << std::endl;
 #endif
         break;
@@ -5951,5 +6262,5 @@
               DspinDhccpParam::FROM_L1_TYPE);
 
-        if((type == DspinDhccpParam::TYPE_CLEANUP_DATA) ||
+        if((type == DspinDhccpParam::TYPE_CLEANUP_DATA) or
            (type == DspinDhccpParam::TYPE_CLEANUP_INST))
         {
@@ -5964,5 +6275,5 @@
         }
 
-        assert(false &&
+        assert(false and
             "VCI_MEM_CACHE ERROR in CC_RECEIVE : "
             "Illegal type in coherence request");
@@ -6049,6 +6360,12 @@
         r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
       }
-      else if(r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE;
-      else if(r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS  ;
+      else if(r_write_to_tgt_rsp_req)
+      {
+        r_tgt_rsp_fsm = TGT_RSP_WRITE;
+      }
+      else if(r_cas_to_tgt_rsp_req) 
+      {
+        r_tgt_rsp_fsm = TGT_RSP_CAS  ;
+      }
       else if(r_xram_rsp_to_tgt_rsp_req)
       {
@@ -6056,7 +6373,16 @@
         r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
       }
-      else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK;
-      else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
-      else if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
+      else if(r_multi_ack_to_tgt_rsp_req) 
+      {
+        r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK;
+      }
+      else if(r_cleanup_to_tgt_rsp_req) 
+      {
+        r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+      }
+      else if(r_tgt_cmd_to_tgt_rsp_req) 
+      {
+        r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
+      }
       break;
     }
@@ -6185,4 +6511,5 @@
     /////////////////////
     case TGT_RSP_TGT_CMD: // send the response after a segmentation violation
+                          // or after a config transaction  
     {
       if ( p_vci_tgt.rspack )
@@ -6192,9 +6519,9 @@
 
 #if DEBUG_MEMC_TGT_RSP
-if( m_debug_tgt_rsp_fsm )
+if( m_debug )
 {
   std::cout
     << "  <MEMC " << name()
-    << " TGT_RSP_TGT_CMD> Segmentation violation from TGT_CMD response"
+    << " TGT_RSP_TGT_CMD> Segmentation violation ior config access response"
     << " / rsrcid = " << std::hex << r_tgt_cmd_to_tgt_rsp_srcid.read()
     << " / rtrdid = " << r_tgt_cmd_to_tgt_rsp_trdid.read()
@@ -6214,5 +6541,5 @@
 
 #if DEBUG_MEMC_TGT_RSP
-if( m_debug_tgt_rsp_fsm )
+if( m_debug )
 {
   std::cout
@@ -6260,5 +6587,5 @@
 
 #if DEBUG_MEMC_TGT_RSP
-if(m_debug_tgt_rsp_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " TGT_RSP_WRITE> Write response"
           << " / rsrcid = " << std::hex << r_write_to_tgt_rsp_srcid.read()
@@ -6271,5 +6598,5 @@
       break;
     }
-    ///////////////////
+    /////////////////////
     case TGT_RSP_CLEANUP:   // pas clair pour moi (AG)
     {
@@ -6278,5 +6605,5 @@
 
 #if DEBUG_MEMC_TGT_RSP
-if(m_debug_tgt_rsp_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " TGT_RSP_CLEANUP> Cleanup response"
           << " / rsrcid = " << std::hex << r_cleanup_to_tgt_rsp_srcid.read()
@@ -6289,5 +6616,5 @@
       break;
     }
-    //////////////////
+    /////////////////
     case TGT_RSP_CAS:    // send one atomic word response
     {
@@ -6296,5 +6623,5 @@
 
 #if DEBUG_MEMC_TGT_RSP
-if(m_debug_tgt_rsp_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " TGT_RSP_CAS> CAS response"
           << " / rsrcid = " << std::hex << r_cas_to_tgt_rsp_srcid.read()
@@ -6308,5 +6635,5 @@
     }
 
-    ///////////////////////
+    //////////////////
     case TGT_RSP_XRAM:    // send the response after XRAM access
     {
@@ -6315,5 +6642,5 @@
 
 #if DEBUG_MEMC_TGT_RSP
-if( m_debug_tgt_rsp_fsm )
+if( m_debug )
 std::cout << "  <MEMC " << name() << " TGT_RSP_XRAM> Response following XRAM access"
           << " / rsrcid = " << std::hex << r_xram_rsp_to_tgt_rsp_srcid.read()
@@ -6351,5 +6678,5 @@
       break;
     }
-    //////////////////
+    ///////////////////////
     case TGT_RSP_MULTI_ACK:    // send the write response after coherence transaction
     {
@@ -6358,5 +6685,5 @@
 
 #if DEBUG_MEMC_TGT_RSP
-if(m_debug_tgt_rsp_fsm)
+if(m_debug)
 std::cout << "  <MEMC " << name() << " TGT_RSP_MULTI_ACK> Write response after coherence transaction"
           << " / rsrcid = " << std::hex << r_multi_ack_to_tgt_rsp_srcid.read()
@@ -6374,10 +6701,13 @@
   //    ALLOC_UPT FSM
   ////////////////////////////////////////////////////////////////////////////////////
-  // The ALLOC_UPT FSM allocates the access to the Update/Inval Table (UPT).
-  // with a round robin priority between three FSMs : MULTI_ACK > WRITE > XRAM_RSP > CLEANUP
-  // - The WRITE FSM initiates update transactions and sets  new entry in UPT.
-  // - The XRAM_RSP FSM initiates inval transactions and sets  new entry in UPT.
+  // The ALLOC_UPT FSM allocates the access to the Update/Inval Table (UPT),
+  // with a round robin priority between six FSMs, with the following order:
+  //  CONFIG > MULTI_ACK > WRITE > XRAM_RSP > CLEANUP > CAS
+  // - The CONFIG FSM initiates an inval transaction and sets a new entry in UPT.
   // - The MULTI_ACK FSM complete those trasactions and erase the UPT entry.
+  // - The WRITE FSM initiates update transaction and sets a new entry in UPT.
+  // - The XRAM_RSP FSM initiates an inval transactions and sets a new entry in UPT.
   // - The CLEANUP  FSM decrement an entry in UPT.
+  // - The CAS FSM does the same thing as the WRITE FSM.
   // The resource is always allocated.
   /////////////////////////////////////////////////////////////////////////////////////
@@ -6385,11 +6715,34 @@
   switch(r_alloc_upt_fsm.read())
   {
-
-      ////////////////////////
-    case ALLOC_UPT_MULTI_ACK:
-      if((r_multi_ack_fsm.read() != MULTI_ACK_UPT_LOCK) &&
+      //////////////////////
+      case ALLOC_UPT_CONFIG:   // allocated to CONFIG FSM
+      if ( (r_config_fsm.read() != CONFIG_UPT_LOCK) and
+           (r_config_fsm.read() != CONFIG_BC_UPT_LOCK) )
+      {
+        if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK)
+          r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK;
+               
+        else if((r_write_fsm.read() == WRITE_UPT_LOCK) or
+                (r_write_fsm.read() == WRITE_BC_UPT_LOCK))
+          r_alloc_upt_fsm = ALLOC_UPT_WRITE;
+
+        else if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)
+          r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
+
+        else if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK)
+          r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
+
+        else if((r_cas_fsm.read() == CAS_UPT_LOCK) or
+                (r_cas_fsm.read() == CAS_BC_UPT_LOCK))
+          r_alloc_upt_fsm = ALLOC_UPT_CAS;
+      }
+      break;
+
+      /////////////////////////
+      case ALLOC_UPT_MULTI_ACK:   // allocated to MULTI_ACK FSM
+      if( (r_multi_ack_fsm.read() != MULTI_ACK_UPT_LOCK) and
           (r_multi_ack_fsm.read() != MULTI_ACK_UPT_CLEAR))
       {
-        if((r_write_fsm.read() == WRITE_UPT_LOCK) ||
+        if((r_write_fsm.read() == WRITE_UPT_LOCK) or
             (r_write_fsm.read() == WRITE_BC_UPT_LOCK))
           r_alloc_upt_fsm = ALLOC_UPT_WRITE;
@@ -6401,13 +6754,17 @@
           r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
 
-        else if((r_cas_fsm.read() == CAS_UPT_LOCK) ||
+        else if((r_cas_fsm.read() == CAS_UPT_LOCK) or
                 (r_cas_fsm.read() == CAS_BC_UPT_LOCK))
           r_alloc_upt_fsm = ALLOC_UPT_CAS;
+
+        else if((r_config_fsm.read() == CONFIG_UPT_LOCK) or
+                (r_config_fsm.read() == CONFIG_BC_UPT_LOCK))
+          r_alloc_upt_fsm = ALLOC_UPT_CONFIG;
       }
       break;
 
       /////////////////////
-    case ALLOC_UPT_WRITE:
-      if((r_write_fsm.read() != WRITE_UPT_LOCK) &&
+      case ALLOC_UPT_WRITE:   // allocated to WRITE FSM
+      if((r_write_fsm.read() != WRITE_UPT_LOCK) and
           (r_write_fsm.read() != WRITE_BC_UPT_LOCK))
       {
@@ -6418,8 +6775,12 @@
           r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
 
-        else if((r_cas_fsm.read() == CAS_UPT_LOCK) ||
+        else if((r_cas_fsm.read() == CAS_UPT_LOCK) or
                 (r_cas_fsm.read() == CAS_BC_UPT_LOCK))
           r_alloc_upt_fsm = ALLOC_UPT_CAS;
 
+        else if((r_config_fsm.read() == CONFIG_UPT_LOCK) or
+                (r_config_fsm.read() == CONFIG_BC_UPT_LOCK))
+          r_alloc_upt_fsm = ALLOC_UPT_CONFIG;
+
         else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK)
           r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK;
@@ -6428,5 +6789,5 @@
 
       ////////////////////////
-    case ALLOC_UPT_XRAM_RSP:
+      case ALLOC_UPT_XRAM_RSP:
       if(r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK)
       {
@@ -6434,12 +6795,16 @@
           r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
 
-        else if((r_cas_fsm.read() == CAS_UPT_LOCK) ||
+        else if((r_cas_fsm.read() == CAS_UPT_LOCK) or
                 (r_cas_fsm.read() == CAS_BC_UPT_LOCK))
           r_alloc_upt_fsm = ALLOC_UPT_CAS;
 
+        else if((r_config_fsm.read() == CONFIG_UPT_LOCK) or
+                (r_config_fsm.read() == CONFIG_BC_UPT_LOCK))
+          r_alloc_upt_fsm = ALLOC_UPT_CONFIG;
+
         else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK)
           r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK;
 
-        else if((r_write_fsm.read() == WRITE_UPT_LOCK)   ||
+        else if((r_write_fsm.read() == WRITE_UPT_LOCK)   or
                 (r_write_fsm.read() == WRITE_BC_UPT_LOCK))
           r_alloc_upt_fsm = ALLOC_UPT_WRITE;
@@ -6448,16 +6813,20 @@
 
       //////////////////////////
-    case ALLOC_UPT_CLEANUP:
-      if((r_cleanup_fsm.read() != CLEANUP_UPT_LOCK     ) &&
+      case ALLOC_UPT_CLEANUP:
+      if((r_cleanup_fsm.read() != CLEANUP_UPT_LOCK     ) and
          (r_cleanup_fsm.read() != CLEANUP_UPT_DECREMENT))
       {
-        if((r_cas_fsm.read() == CAS_UPT_LOCK) ||
+        if((r_cas_fsm.read() == CAS_UPT_LOCK) or
             (r_cas_fsm.read() == CAS_BC_UPT_LOCK))
           r_alloc_upt_fsm = ALLOC_UPT_CAS;
 
+        else if((r_config_fsm.read() == CONFIG_UPT_LOCK) or
+                (r_config_fsm.read() == CONFIG_BC_UPT_LOCK))
+          r_alloc_upt_fsm = ALLOC_UPT_CONFIG;
+
         else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK)
           r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK;
 
-        else if((r_write_fsm.read() == WRITE_UPT_LOCK) ||
+        else if((r_write_fsm.read() == WRITE_UPT_LOCK) or
                 (r_write_fsm.read() == WRITE_BC_UPT_LOCK))
           r_alloc_upt_fsm = ALLOC_UPT_WRITE;
@@ -6469,12 +6838,16 @@
 
       //////////////////////////
-    case ALLOC_UPT_CAS:
-      if((r_cas_fsm.read() != CAS_UPT_LOCK) &&
+      case ALLOC_UPT_CAS:
+      if((r_cas_fsm.read() != CAS_UPT_LOCK) and
           (r_cas_fsm.read() != CAS_BC_UPT_LOCK))
       {
-        if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK)
+        if((r_config_fsm.read() == CONFIG_UPT_LOCK) or
+                (r_config_fsm.read() == CONFIG_BC_UPT_LOCK))
+          r_alloc_upt_fsm = ALLOC_UPT_CONFIG;
+
+        else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK)
           r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK;
 
-        else if((r_write_fsm.read() == WRITE_UPT_LOCK) ||
+        else if((r_write_fsm.read() == WRITE_UPT_LOCK) or
                 (r_write_fsm.read() == WRITE_BC_UPT_LOCK))
           r_alloc_upt_fsm = ALLOC_UPT_WRITE;
@@ -6494,6 +6867,6 @@
   ////////////////////////////////////////////////////////////////////////////////////
   // The ALLOC_DIR FSM allocates the access to the directory and
-  // the data cache with a round robin priority between 5 user FSMs :
-  // The cyclic ordering is READ > WRITE > CAS > CLEANUP > XRAM_RSP
+  // the data cache with a round robin priority between 6 user FSMs :
+  // The cyclic ordering is CONFIG > READ > WRITE > CAS > CLEANUP > XRAM_RSP
   // The ressource is always allocated.
   /////////////////////////////////////////////////////////////////////////////////////
@@ -6501,4 +6874,5 @@
   switch(r_alloc_dir_fsm.read())
   {
+    /////////////////////
     case ALLOC_DIR_RESET: // Initializes the directory one SET per cycle.
                           // All the WAYS of a SET initialized in parallel
@@ -6513,14 +6887,37 @@
       break;
 
+    //////////////////////
+    case ALLOC_DIR_CONFIG:    // allocated to CONFIG FSM
+    if ( (r_config_fsm.read()    != CONFIG_DIR_REQ) and
+         (r_config_fsm.read()    != CONFIG_DIR_ACCESS) and
+         (r_config_fsm.read()    != CONFIG_DIR_INVAL) )
+    {
+        if(r_read_fsm.read() == READ_DIR_REQ)
+          r_alloc_dir_fsm = ALLOC_DIR_READ;
+
+        else if(r_write_fsm.read() == WRITE_DIR_REQ)
+          r_alloc_dir_fsm = ALLOC_DIR_WRITE;
+
+        else if(r_cas_fsm.read() == CAS_DIR_REQ)
+          r_alloc_dir_fsm = ALLOC_DIR_CAS;
+
+        else if(r_cleanup_fsm.read() == CLEANUP_DIR_REQ)
+          r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
+
+        else if(r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)
+          r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
+    }
+    break;
+
     ////////////////////
-    case ALLOC_DIR_READ:
-      if(((r_read_fsm.read()        != READ_DIR_REQ)   &&
-          (r_read_fsm.read()        != READ_DIR_LOCK)   &&
-          (r_read_fsm.read()        != READ_TRT_LOCK)   &&
-          (r_read_fsm.read()        != READ_HEAP_REQ))
-          ||
-          ((r_read_fsm.read()       == READ_TRT_LOCK)   &&
-           (r_alloc_trt_fsm.read()  == ALLOC_TRT_READ)))
-      {
+    case ALLOC_DIR_READ:    // allocated to READ FSM
+    if( ((r_read_fsm.read()      != READ_DIR_REQ)   and
+         (r_read_fsm.read()      != READ_DIR_LOCK)   and
+         (r_read_fsm.read()      != READ_TRT_LOCK)   and
+         (r_read_fsm.read()      != READ_HEAP_REQ))
+         or
+         ((r_read_fsm.read()       == READ_TRT_LOCK)   and
+          (r_alloc_trt_fsm.read()  == ALLOC_TRT_READ)) )
+    {
         if(r_write_fsm.read() == WRITE_DIR_REQ)
           r_alloc_dir_fsm = ALLOC_DIR_WRITE;
@@ -6534,25 +6931,28 @@
         else if(r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)
           r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
-      }
-      break;
-
-      /////////////////////
-    case ALLOC_DIR_WRITE:
-      if(((r_write_fsm.read()       != WRITE_DIR_REQ)  &&
-          (r_write_fsm.read()       != WRITE_DIR_LOCK)  &&
-          (r_write_fsm.read()       != WRITE_DIR_READ)  &&
-          (r_write_fsm.read()       != WRITE_DIR_HIT)  &&
-          (r_write_fsm.read()       != WRITE_BC_TRT_LOCK)  &&
-          (r_write_fsm.read()       != WRITE_BC_UPT_LOCK)  &&
-          (r_write_fsm.read()       != WRITE_MISS_TRT_LOCK)  &&
-          (r_write_fsm.read()       != WRITE_UPT_LOCK)  &&
-          (r_write_fsm.read()       != WRITE_UPT_HEAP_LOCK))
-          ||
-          ((r_write_fsm.read()      == WRITE_UPT_HEAP_LOCK)  &&
-           (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE))
-          ||
-          ((r_write_fsm.read()      == WRITE_MISS_TRT_LOCK)  &&
-           (r_alloc_trt_fsm.read()  == ALLOC_TRT_WRITE)))
-      {
+
+        else if(r_config_fsm.read() == CONFIG_DIR_REQ)
+          r_alloc_dir_fsm = ALLOC_DIR_CONFIG;
+    }
+    break;
+
+    /////////////////////
+    case ALLOC_DIR_WRITE:    // allocated to WRITE FSM
+    if(((r_write_fsm.read()       != WRITE_DIR_REQ)  and
+        (r_write_fsm.read()       != WRITE_DIR_LOCK)  and
+        (r_write_fsm.read()       != WRITE_DIR_READ)  and
+        (r_write_fsm.read()       != WRITE_DIR_HIT)  and
+        (r_write_fsm.read()       != WRITE_BC_TRT_LOCK)  and
+        (r_write_fsm.read()       != WRITE_BC_UPT_LOCK)  and
+        (r_write_fsm.read()       != WRITE_MISS_TRT_LOCK)  and
+        (r_write_fsm.read()       != WRITE_UPT_LOCK)  and
+        (r_write_fsm.read()       != WRITE_UPT_HEAP_LOCK))
+        or
+        ((r_write_fsm.read()      == WRITE_UPT_HEAP_LOCK)  and
+         (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE))
+        or
+        ((r_write_fsm.read()      == WRITE_MISS_TRT_LOCK)  and
+         (r_alloc_trt_fsm.read()  == ALLOC_TRT_WRITE)))
+    {
         if(r_cas_fsm.read() == CAS_DIR_REQ)
           r_alloc_dir_fsm = ALLOC_DIR_CAS;
@@ -6564,28 +6964,31 @@
           r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
 
+        else if(r_config_fsm.read() == CONFIG_DIR_REQ)
+          r_alloc_dir_fsm = ALLOC_DIR_CONFIG;
+
         else if(r_read_fsm.read() == READ_DIR_REQ)
           r_alloc_dir_fsm = ALLOC_DIR_READ;
-      }
-      break;
-
-      ////////////////////
-    case ALLOC_DIR_CAS:
-      if(((r_cas_fsm.read()         != CAS_DIR_REQ)  &&
-          (r_cas_fsm.read()         != CAS_DIR_LOCK)  &&
-          (r_cas_fsm.read()         != CAS_DIR_HIT_READ)  &&
-          (r_cas_fsm.read()         != CAS_DIR_HIT_COMPARE)  &&
-          (r_cas_fsm.read()         != CAS_DIR_HIT_WRITE)  &&
-          (r_cas_fsm.read()         != CAS_BC_TRT_LOCK)  &&
-          (r_cas_fsm.read()         != CAS_BC_UPT_LOCK)  &&
-          (r_cas_fsm.read()         != CAS_MISS_TRT_LOCK)  &&
-          (r_cas_fsm.read()         != CAS_UPT_LOCK)  &&
-          (r_cas_fsm.read()         != CAS_UPT_HEAP_LOCK))
-          ||
-          ((r_cas_fsm.read()        == CAS_UPT_HEAP_LOCK)  &&
-           (r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS))
-          ||
-          ((r_cas_fsm.read()        == CAS_MISS_TRT_LOCK)  &&
-           (r_alloc_trt_fsm.read()  == ALLOC_TRT_CAS)))
-      {
+    }
+    break;
+
+    ///////////////////
+    case ALLOC_DIR_CAS:    // allocated to CAS FSM
+    if(((r_cas_fsm.read()         != CAS_DIR_REQ)  and
+        (r_cas_fsm.read()         != CAS_DIR_LOCK)  and
+        (r_cas_fsm.read()         != CAS_DIR_HIT_READ)  and
+        (r_cas_fsm.read()         != CAS_DIR_HIT_COMPARE)  and
+        (r_cas_fsm.read()         != CAS_DIR_HIT_WRITE)  and
+        (r_cas_fsm.read()         != CAS_BC_TRT_LOCK)  and
+        (r_cas_fsm.read()         != CAS_BC_UPT_LOCK)  and
+        (r_cas_fsm.read()         != CAS_MISS_TRT_LOCK)  and
+        (r_cas_fsm.read()         != CAS_UPT_LOCK)  and
+        (r_cas_fsm.read()         != CAS_UPT_HEAP_LOCK))
+        or
+        ((r_cas_fsm.read()        == CAS_UPT_HEAP_LOCK)  and
+         (r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS))
+        or
+        ((r_cas_fsm.read()        == CAS_MISS_TRT_LOCK)  and
+         (r_alloc_trt_fsm.read()  == ALLOC_TRT_CAS)))
+    {
         if(r_cleanup_fsm.read() == CLEANUP_DIR_REQ)
           r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
@@ -6594,4 +6997,7 @@
           r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
 
+        else if(r_config_fsm.read() == CONFIG_DIR_REQ)
+          r_alloc_dir_fsm = ALLOC_DIR_CONFIG;
+
         else if(r_read_fsm.read() == READ_DIR_REQ)
           r_alloc_dir_fsm = ALLOC_DIR_READ;
@@ -6599,17 +7005,20 @@
         else if(r_write_fsm.read() == WRITE_DIR_REQ)
           r_alloc_dir_fsm = ALLOC_DIR_WRITE;
-      }
-      break;
-
-      ///////////////////////
-    case ALLOC_DIR_CLEANUP:
-      if((r_cleanup_fsm.read() != CLEANUP_DIR_REQ) &&
-          (r_cleanup_fsm.read() != CLEANUP_DIR_LOCK) &&
-          (r_cleanup_fsm.read() != CLEANUP_HEAP_REQ) &&
-          (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK))
-      {
+    }
+      break;
+
+    ///////////////////////
+    case ALLOC_DIR_CLEANUP:    // allocated to CLEANUP FSM
+    if((r_cleanup_fsm.read() != CLEANUP_DIR_REQ) and
+        (r_cleanup_fsm.read() != CLEANUP_DIR_LOCK) and
+        (r_cleanup_fsm.read() != CLEANUP_HEAP_REQ) and
+        (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK))
+    {
         if(r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)
           r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
 
+        else if(r_config_fsm.read() == CONFIG_DIR_REQ)
+          r_alloc_dir_fsm = ALLOC_DIR_CONFIG;
+
         else if(r_read_fsm.read() == READ_DIR_REQ)
           r_alloc_dir_fsm = ALLOC_DIR_READ;
@@ -6620,14 +7029,17 @@
         else if(r_cas_fsm.read() == CAS_DIR_REQ)
           r_alloc_dir_fsm = ALLOC_DIR_CAS;
-      }
-      break;
-
-      ////////////////////////
-    case ALLOC_DIR_XRAM_RSP:
-      if((r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) &&
-          (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) &&
-          (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK))
-      {
-        if(r_read_fsm.read() == READ_DIR_REQ)
+    }
+    break;
+
+    ////////////////////////
+    case ALLOC_DIR_XRAM_RSP:    // allocated to XRAM_RSP FSM
+    if( (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) and
+        (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) and
+        (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK))
+    {
+        if(r_config_fsm.read() == CONFIG_DIR_REQ)
+          r_alloc_dir_fsm = ALLOC_DIR_CONFIG;
+
+        else if(r_read_fsm.read() == READ_DIR_REQ)
           r_alloc_dir_fsm = ALLOC_DIR_READ;
 
@@ -6640,6 +7052,6 @@
         else if(r_cleanup_fsm.read() == CLEANUP_DIR_REQ)
           r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
-      }
-      break;
+    }
+    break;
 
   } // end switch alloc_dir_fsm
@@ -6660,17 +7072,17 @@
       if(r_read_fsm.read() != READ_TRT_LOCK)
       {
-        if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) ||
+        if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or
             (r_write_fsm.read() == WRITE_BC_TRT_LOCK))
           r_alloc_trt_fsm = ALLOC_TRT_WRITE;
 
-        else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) ||
+        else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or
                 (r_cas_fsm.read() == CAS_BC_TRT_LOCK))
           r_alloc_trt_fsm = ALLOC_TRT_CAS;
 
-        else if((r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK) &&
+        else if((r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK) and
                 (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP))
           r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
 
-        else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
+        else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or
                 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))
           r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
@@ -6680,17 +7092,17 @@
     /////////////////////
     case ALLOC_TRT_WRITE:
-      if((r_write_fsm.read() != WRITE_MISS_TRT_LOCK) &&
-          (r_write_fsm.read() != WRITE_BC_TRT_LOCK) &&
+      if((r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and
+          (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and
           (r_write_fsm.read() != WRITE_BC_UPT_LOCK))
       {
-        if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) ||
+        if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or
             (r_cas_fsm.read() == CAS_BC_TRT_LOCK))
           r_alloc_trt_fsm = ALLOC_TRT_CAS;
 
-        else if((r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK) &&
+        else if((r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK) and
                 (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP))
           r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
 
-        else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
+        else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or
                 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))
           r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
@@ -6703,13 +7115,13 @@
     ////////////////////
     case ALLOC_TRT_CAS:
-      if((r_cas_fsm.read() != CAS_MISS_TRT_LOCK) &&
-          (r_cas_fsm.read() != CAS_BC_TRT_LOCK) &&
+      if((r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and
+          (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and
           (r_cas_fsm.read() != CAS_BC_UPT_LOCK))
       {
-        if((r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK) &&
+        if((r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK) and
             (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP))
           r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
 
-        else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
+        else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or
                 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))
           r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
@@ -6718,5 +7130,5 @@
           r_alloc_trt_fsm = ALLOC_TRT_READ;
 
-        else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) ||
+        else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or
                 (r_write_fsm.read() == WRITE_BC_TRT_LOCK))
           r_alloc_trt_fsm = ALLOC_TRT_WRITE;
@@ -6726,11 +7138,11 @@
     ////////////////////////
     case ALLOC_TRT_XRAM_RSP:
-      if(((r_xram_rsp_fsm.read()  != XRAM_RSP_DIR_LOCK)  ||
-          (r_alloc_dir_fsm.read() != ALLOC_DIR_XRAM_RSP)) &&
-          (r_xram_rsp_fsm.read()  != XRAM_RSP_TRT_COPY)  &&
-          (r_xram_rsp_fsm.read()  != XRAM_RSP_DIR_UPDT)  &&
+      if(((r_xram_rsp_fsm.read()  != XRAM_RSP_DIR_LOCK)  or
+          (r_alloc_dir_fsm.read() != ALLOC_DIR_XRAM_RSP)) and
+          (r_xram_rsp_fsm.read()  != XRAM_RSP_TRT_COPY)  and
+          (r_xram_rsp_fsm.read()  != XRAM_RSP_DIR_UPDT)  and
           (r_xram_rsp_fsm.read()  != XRAM_RSP_INVAL_LOCK))
       {
-        if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
+        if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or
             (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))
           r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
@@ -6739,9 +7151,9 @@
           r_alloc_trt_fsm = ALLOC_TRT_READ;
 
-        else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) ||
+        else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or
                 (r_write_fsm.read() == WRITE_BC_TRT_LOCK))
           r_alloc_trt_fsm = ALLOC_TRT_WRITE;
 
-        else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) ||
+        else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or
                 (r_cas_fsm.read() == CAS_BC_TRT_LOCK))
           r_alloc_trt_fsm = ALLOC_TRT_CAS;
@@ -6751,5 +7163,5 @@
     ////////////////////////
     case ALLOC_TRT_IXR_RSP:
-      if((r_ixr_rsp_fsm.read() != IXR_RSP_TRT_ERASE) &&
+      if((r_ixr_rsp_fsm.read() != IXR_RSP_TRT_ERASE) and
           (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ))
       {
@@ -6757,13 +7169,13 @@
           r_alloc_trt_fsm = ALLOC_TRT_READ;
 
-        else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) ||
+        else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or
                 (r_write_fsm.read() == WRITE_BC_TRT_LOCK))
           r_alloc_trt_fsm = ALLOC_TRT_WRITE;
 
-        else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) ||
+        else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or
                 (r_cas_fsm.read() == CAS_BC_TRT_LOCK))
           r_alloc_trt_fsm = ALLOC_TRT_CAS;
 
-        else if((r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK) &&
+        else if((r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK) and
                 (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP))
           r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
@@ -6800,6 +7212,6 @@
       ////////////////////
     case ALLOC_HEAP_READ:
-      if((r_read_fsm.read() != READ_HEAP_REQ) &&
-          (r_read_fsm.read() != READ_HEAP_LOCK) &&
+      if((r_read_fsm.read() != READ_HEAP_REQ) and
+          (r_read_fsm.read() != READ_HEAP_LOCK) and
           (r_read_fsm.read() != READ_HEAP_ERASE))
       {
@@ -6820,6 +7232,6 @@
       /////////////////////
     case ALLOC_HEAP_WRITE:
-      if((r_write_fsm.read() != WRITE_UPT_HEAP_LOCK) &&
-          (r_write_fsm.read() != WRITE_UPT_REQ) &&
+      if((r_write_fsm.read() != WRITE_UPT_HEAP_LOCK) and
+          (r_write_fsm.read() != WRITE_UPT_REQ) and
           (r_write_fsm.read() != WRITE_UPT_NEXT))
       {
@@ -6840,6 +7252,6 @@
       ////////////////////
     case ALLOC_HEAP_CAS:
-      if((r_cas_fsm.read() != CAS_UPT_HEAP_LOCK) &&
-          (r_cas_fsm.read() != CAS_UPT_REQ) &&
+      if((r_cas_fsm.read() != CAS_UPT_HEAP_LOCK) and
+          (r_cas_fsm.read() != CAS_UPT_REQ) and
           (r_cas_fsm.read() != CAS_UPT_NEXT))
       {
@@ -6860,7 +7272,7 @@
       ///////////////////////
     case ALLOC_HEAP_CLEANUP:
-      if((r_cleanup_fsm.read() != CLEANUP_HEAP_REQ) &&
-          (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK) &&
-          (r_cleanup_fsm.read() != CLEANUP_HEAP_SEARCH) &&
+      if((r_cleanup_fsm.read() != CLEANUP_HEAP_REQ) and
+          (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK) and
+          (r_cleanup_fsm.read() != CLEANUP_HEAP_SEARCH) and
           (r_cleanup_fsm.read() != CLEANUP_HEAP_CLEAN))
       {
@@ -6881,5 +7293,5 @@
       ////////////////////////
     case ALLOC_HEAP_XRAM_RSP:
-      if((r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_REQ) &&
+      if((r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_REQ) and
           (r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_ERASE))
       {
@@ -6901,39 +7313,19 @@
   } // end switch alloc_heap_fsm
 
-
-  ////////////////////////////////////////////////////////////////////////////////////
+  /////////////////////////////////////////////////////////////////////
   //    TGT_CMD to READ FIFO
-  ////////////////////////////////////////////////////////////////////////////////////
-
-  if(cmd_read_fifo_put)
-  {
-    if(cmd_read_fifo_get)
-    {
-      m_cmd_read_addr_fifo.put_and_get((addr_t)(p_vci_tgt.address.read()));
-      m_cmd_read_length_fifo.put_and_get(p_vci_tgt.plen.read() >>2);
-      m_cmd_read_srcid_fifo.put_and_get(p_vci_tgt.srcid.read());
-      m_cmd_read_trdid_fifo.put_and_get(p_vci_tgt.trdid.read());
-      m_cmd_read_pktid_fifo.put_and_get(p_vci_tgt.pktid.read());
-    }
-    else
-    {
-      m_cmd_read_addr_fifo.simple_put((addr_t)(p_vci_tgt.address.read()));
-      m_cmd_read_length_fifo.simple_put(p_vci_tgt.plen.read() >>2);
-      m_cmd_read_srcid_fifo.simple_put(p_vci_tgt.srcid.read());
-      m_cmd_read_trdid_fifo.simple_put(p_vci_tgt.trdid.read());
-      m_cmd_read_pktid_fifo.simple_put(p_vci_tgt.pktid.read());
-    }
-  }
-  else
-  {
-    if(cmd_read_fifo_get)
-    {
-      m_cmd_read_addr_fifo.simple_get();
-      m_cmd_read_length_fifo.simple_get();
-      m_cmd_read_srcid_fifo.simple_get();
-      m_cmd_read_trdid_fifo.simple_get();
-      m_cmd_read_pktid_fifo.simple_get();
-    }
-  }
+  /////////////////////////////////////////////////////////////////////
+
+  m_cmd_read_addr_fifo.update(   cmd_read_fifo_get, cmd_read_fifo_put, 
+                                 p_vci_tgt.address.read() );
+  m_cmd_read_length_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, 
+                                 p_vci_tgt.plen.read()>>2 );
+  m_cmd_read_srcid_fifo.update(  cmd_read_fifo_get, cmd_read_fifo_put, 
+                                 p_vci_tgt.srcid.read() );
+  m_cmd_read_trdid_fifo.update(  cmd_read_fifo_get, cmd_read_fifo_put, 
+                                 p_vci_tgt.trdid.read() );
+  m_cmd_read_pktid_fifo.update(  cmd_read_fifo_get, cmd_read_fifo_put, 
+                                 p_vci_tgt.pktid.read() );
+
   /////////////////////////////////////////////////////////////////////
   //    TGT_CMD to WRITE FIFO
@@ -7264,6 +7656,6 @@
   ////////////////////////////////////////////////////
 
-  if(((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) &&
-      (r_ixr_rsp_fsm.read()   == IXR_RSP_TRT_READ)) ||
+  if(((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) and
+      (r_ixr_rsp_fsm.read()   == IXR_RSP_TRT_READ)) or
       (r_ixr_rsp_fsm.read()   == IXR_RSP_ACK))
 
@@ -7333,5 +7725,5 @@
       p_vci_tgt.rtrdid  = r_tgt_cmd_to_tgt_rsp_trdid.read();
       p_vci_tgt.rpktid  = r_tgt_cmd_to_tgt_rsp_pktid.read();
-      p_vci_tgt.rerror  = 0x1;
+      p_vci_tgt.rerror  = r_tgt_cmd_to_tgt_rsp_error.read();
       p_vci_tgt.reop    = true;
 
@@ -7368,5 +7760,5 @@
     case TGT_RSP_WRITE:
       p_vci_tgt.rspval   = true;
-      if(((r_write_to_tgt_rsp_pktid.read() & 0x7) == TYPE_SC) && r_write_to_tgt_rsp_sc_fail.read())
+      if(((r_write_to_tgt_rsp_pktid.read() & 0x7) == TYPE_SC) and r_write_to_tgt_rsp_sc_fail.read())
         p_vci_tgt.rdata  = 1;
       else
