- Timestamp:
- Jul 17, 2013, 9:24:48 AM (11 years ago)
- Location:
- branches/v5/modules/vci_mem_cache
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caba/source/include/vci_mem_cache.h (modified) (30 diffs)
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branches/v5/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r362 r440 52 52 #include "dspin_dhccp_param.h" 53 53 54 #define TRANSACTION_TAB_LINES 4 // Number of lines in the transaction tab 55 #define UPDATE_TAB_LINES 4 // Number of lines in the update tab 54 #define TRT_ENTRIES 4 // Number of entries in TRT 55 #define UPT_ENTRIES 4 // Number of entries in UPT 56 #define HEAP_ENTRIES 1024 // Number of entries in HEAP 56 57 57 58 namespace soclib { namespace caba { 59 58 60 using namespace sc_core; 59 61 60 template<typename vci_param> 62 template<typename vci_param_int, 63 typename vci_param_ext, 64 size_t dspin_in_width, 65 size_t dspin_out_width> 61 66 class VciMemCache 62 67 : public soclib::caba::BaseModule 63 68 { 64 typedef sc_dt::sc_uint<40> addr_t; 65 typedef typename vci_param::fast_addr_t vci_addr_t; 69 typedef typename vci_param_int::fast_addr_t addr_t; 70 71 typedef typename sc_dt::sc_uint<64> wide_data_t; 72 66 73 typedef uint32_t data_t; 67 74 typedef uint32_t tag_t; 68 typedef uint32_t size_t;69 75 typedef uint32_t be_t; 70 76 typedef uint32_t copy_t; 71 77 72 78 /* States of the TGT_CMD fsm */ 73 enum tgt_cmd_fsm_state_e{ 79 enum tgt_cmd_fsm_state_e 80 { 74 81 TGT_CMD_IDLE, 82 TGT_CMD_ERROR, 75 83 TGT_CMD_READ, 76 84 TGT_CMD_WRITE, 77 TGT_CMD_CAS 85 TGT_CMD_CAS, 86 TGT_CMD_CONFIG 78 87 }; 79 88 80 89 /* States of the TGT_RSP fsm */ 81 enum tgt_rsp_fsm_state_e{ 90 enum tgt_rsp_fsm_state_e 91 { 92 TGT_RSP_CONFIG_IDLE, 93 TGT_RSP_TGT_CMD_IDLE, 82 94 TGT_RSP_READ_IDLE, 83 95 TGT_RSP_WRITE_IDLE, 84 96 TGT_RSP_CAS_IDLE, 85 97 TGT_RSP_XRAM_IDLE, 86 TGT_RSP_ INIT_IDLE,98 TGT_RSP_MULTI_ACK_IDLE, 87 99 TGT_RSP_CLEANUP_IDLE, 100 TGT_RSP_CONFIG, 101 TGT_RSP_TGT_CMD, 88 102 TGT_RSP_READ, 89 103 TGT_RSP_WRITE, 90 104 TGT_RSP_CAS, 91 105 TGT_RSP_XRAM, 92 TGT_RSP_ INIT,106 TGT_RSP_MULTI_ACK, 93 107 TGT_RSP_CLEANUP 94 108 }; 95 109 96 110 /* States of the DSPIN_TGT fsm */ 97 enum cc_receive_fsm_state_e{ 111 enum cc_receive_fsm_state_e 112 { 98 113 CC_RECEIVE_IDLE, 99 114 CC_RECEIVE_CLEANUP, 115 CC_RECEIVE_CLEANUP_EOP, 100 116 CC_RECEIVE_MULTI_ACK 101 117 }; 102 118 103 119 /* States of the CC_SEND fsm */ 104 enum cc_send_fsm_state_e{ 120 enum cc_send_fsm_state_e 121 { 122 CC_SEND_CONFIG_IDLE, 105 123 CC_SEND_XRAM_RSP_IDLE, 106 124 CC_SEND_WRITE_IDLE, 107 125 CC_SEND_CAS_IDLE, 108 126 CC_SEND_CLEANUP_IDLE, 127 CC_SEND_CONFIG_INVAL_HEADER, 128 CC_SEND_CONFIG_INVAL_NLINE, 129 CC_SEND_CONFIG_BRDCAST_HEADER, 130 CC_SEND_CONFIG_BRDCAST_NLINE, 109 131 CC_SEND_CLEANUP_ACK, 110 132 CC_SEND_XRAM_RSP_BRDCAST_HEADER, … … 126 148 127 149 /* States of the MULTI_ACK fsm */ 128 enum multi_ack_fsm_state_e{ 150 enum multi_ack_fsm_state_e 151 { 129 152 MULTI_ACK_IDLE, 130 153 MULTI_ACK_UPT_LOCK, 131 154 MULTI_ACK_UPT_CLEAR, 132 MULTI_ACK_WRITE_RSP 155 MULTI_ACK_WRITE_RSP, 156 MULTI_ACK_CONFIG_ACK 157 }; 158 159 /* States of the CONFIG fsm */ 160 enum config_fsm_state_e 161 { 162 CONFIG_IDLE, 163 CONFIG_LOOP, 164 CONFIG_RSP, 165 CONFIG_DIR_REQ, 166 CONFIG_DIR_ACCESS, 167 CONFIG_DIR_UPT_LOCK, 168 CONFIG_BC_SEND, 169 CONFIG_BC_WAIT, 170 CONFIG_INV_SEND, 171 CONFIG_HEAP_REQ, 172 CONFIG_HEAP_SCAN, 173 CONFIG_HEAP_LAST, 174 CONFIG_INV_WAIT 133 175 }; 134 176 135 177 /* States of the READ fsm */ 136 enum read_fsm_state_e{ 178 enum read_fsm_state_e 179 { 137 180 READ_IDLE, 138 181 READ_DIR_REQ, … … 151 194 152 195 /* States of the WRITE fsm */ 153 enum write_fsm_state_e{ 196 enum write_fsm_state_e 197 { 154 198 WRITE_IDLE, 155 199 WRITE_NEXT, … … 177 221 178 222 /* States of the IXR_RSP fsm */ 179 enum ixr_rsp_fsm_state_e{ 223 enum ixr_rsp_fsm_state_e 224 { 180 225 IXR_RSP_IDLE, 181 226 IXR_RSP_ACK, … … 185 230 186 231 /* States of the XRAM_RSP fsm */ 187 enum xram_rsp_fsm_state_e{ 232 enum xram_rsp_fsm_state_e 233 { 188 234 XRAM_RSP_IDLE, 189 235 XRAM_RSP_TRT_COPY, … … 204 250 205 251 /* States of the IXR_CMD fsm */ 206 enum ixr_cmd_fsm_state_e{ 252 enum ixr_cmd_fsm_state_e 253 { 207 254 IXR_CMD_READ_IDLE, 208 255 IXR_CMD_WRITE_IDLE, 209 256 IXR_CMD_CAS_IDLE, 210 257 IXR_CMD_XRAM_IDLE, 211 IXR_CMD_READ _NLINE,212 IXR_CMD_WRITE _NLINE,213 IXR_CMD_CAS _NLINE,214 IXR_CMD_XRAM _DATA258 IXR_CMD_READ, 259 IXR_CMD_WRITE, 260 IXR_CMD_CAS, 261 IXR_CMD_XRAM 215 262 }; 216 263 217 264 /* States of the CAS fsm */ 218 enum cas_fsm_state_e{ 265 enum cas_fsm_state_e 266 { 219 267 CAS_IDLE, 220 268 CAS_DIR_REQ, … … 241 289 242 290 /* States of the CLEANUP fsm */ 243 enum cleanup_fsm_state_e{ 291 enum cleanup_fsm_state_e 292 { 244 293 CLEANUP_IDLE, 245 294 CLEANUP_GET_NLINE, … … 256 305 CLEANUP_UPT_CLEAR, 257 306 CLEANUP_WRITE_RSP, 258 CLEANUP_SEND_ACK 307 CLEANUP_CONFIG_ACK, 308 CLEANUP_SEND_CLACK 259 309 }; 260 310 261 311 /* States of the ALLOC_DIR fsm */ 262 enum alloc_dir_fsm_state_e{ 312 enum alloc_dir_fsm_state_e 313 { 263 314 ALLOC_DIR_RESET, 315 ALLOC_DIR_CONFIG, 264 316 ALLOC_DIR_READ, 265 317 ALLOC_DIR_WRITE, … … 270 322 271 323 /* States of the ALLOC_TRT fsm */ 272 enum alloc_trt_fsm_state_e{ 324 enum alloc_trt_fsm_state_e 325 { 273 326 ALLOC_TRT_READ, 274 327 ALLOC_TRT_WRITE, … … 279 332 280 333 /* States of the ALLOC_UPT fsm */ 281 enum alloc_upt_fsm_state_e{ 334 enum alloc_upt_fsm_state_e 335 { 336 ALLOC_UPT_CONFIG, 282 337 ALLOC_UPT_WRITE, 283 338 ALLOC_UPT_XRAM_RSP, … … 288 343 289 344 /* States of the ALLOC_HEAP fsm */ 290 enum alloc_heap_fsm_state_e{ 345 enum alloc_heap_fsm_state_e 346 { 291 347 ALLOC_HEAP_RESET, 292 348 ALLOC_HEAP_READ, … … 294 350 ALLOC_HEAP_CAS, 295 351 ALLOC_HEAP_CLEANUP, 296 ALLOC_HEAP_XRAM_RSP 352 ALLOC_HEAP_XRAM_RSP, 353 ALLOC_HEAP_CONFIG 297 354 }; 298 355 … … 325 382 }; 326 383 384 /* Configuration commands */ 385 enum cmd_config_type_e 386 { 387 CMD_CONFIG_INVAL = 0, 388 CMD_CONFIG_SYNC = 1 389 }; 390 327 391 // debug variables (for each FSM) 328 bool m_debug_global; 329 bool m_debug_tgt_cmd_fsm; 330 bool m_debug_tgt_rsp_fsm; 331 bool m_debug_cc_send_fsm; 332 bool m_debug_cc_receive_fsm; 333 bool m_debug_multi_ack_fsm; 334 bool m_debug_read_fsm; 335 bool m_debug_write_fsm; 336 bool m_debug_cas_fsm; 337 bool m_debug_cleanup_fsm; 338 bool m_debug_ixr_cmd_fsm; 339 bool m_debug_ixr_rsp_fsm; 340 bool m_debug_xram_rsp_fsm; 392 bool m_debug; 341 393 bool m_debug_previous_hit; 342 394 size_t m_debug_previous_count; 343 395 344 396 bool m_monitor_ok; 345 vci_addr_tm_monitor_base;346 vci_addr_tm_monitor_length;397 addr_t m_monitor_base; 398 addr_t m_monitor_length; 347 399 348 400 // instrumentation counters 349 401 uint32_t m_cpt_cycles; // Counter of cycles 402 350 403 uint32_t m_cpt_read; // Number of READ transactions 404 uint32_t m_cpt_read_remote; // number of remote READ transactions 405 uint32_t m_cpt_read_flits; // number of flits for READs 406 uint32_t m_cpt_read_cost; // Number of (flits * distance) for READs 407 351 408 uint32_t m_cpt_read_miss; // Number of MISS READ 409 352 410 uint32_t m_cpt_write; // Number of WRITE transactions 411 uint32_t m_cpt_write_remote; // number of remote WRITE transactions 412 uint32_t m_cpt_write_flits; // number of flits for WRITEs 413 uint32_t m_cpt_write_cost; // Number of (flits * distance) for WRITEs 414 353 415 uint32_t m_cpt_write_miss; // Number of MISS WRITE 354 416 uint32_t m_cpt_write_cells; // Cumulated length for WRITE transactions … … 366 428 uint32_t m_cpt_cas; // Number of CAS transactions 367 429 430 uint32_t m_cpt_cleanup_cost; // Number of (flits * distance) for CLEANUPs 431 432 uint32_t m_cpt_update_flits; // Number of flits for UPDATEs 433 uint32_t m_cpt_update_cost; // Number of (flits * distance) for UPDATEs 434 435 uint32_t m_cpt_inval_cost; // Number of (flits * distance) for INVALs 436 437 uint32_t m_cpt_get; 438 439 uint32_t m_cpt_put; 440 368 441 size_t m_prev_count; 369 442 … … 373 446 374 447 public: 375 sc_in<bool> p_clk;376 sc_in<bool> p_resetn;377 soclib::caba::VciTarget<vci_param >p_vci_tgt;378 soclib::caba::VciInitiator<vci_param >p_vci_ixr;379 soclib::caba::DspinInput< 33>p_dspin_in;380 soclib::caba::DspinOutput< 40>p_dspin_out;448 sc_in<bool> p_clk; 449 sc_in<bool> p_resetn; 450 soclib::caba::VciTarget<vci_param_int> p_vci_tgt; 451 soclib::caba::VciInitiator<vci_param_ext> p_vci_ixr; 452 soclib::caba::DspinInput<dspin_in_width> p_dspin_in; 453 soclib::caba::DspinOutput<dspin_out_width> p_dspin_out; 381 454 382 455 VciMemCache( 383 456 sc_module_name name, // Instance Name 384 const soclib::common::MappingTable &mtp, // Mapping table for directnetwork385 const soclib::common::MappingTable &mtx, // Mapping table for externalnetwork386 const soclib::common::IntTab &srcid_x, // global index on externalnetwork387 const soclib::common::IntTab &tgtid_d, // global index on directnetwork388 const size_t cc_global_id, // global index on ccnetwork457 const soclib::common::MappingTable &mtp, // Mapping table INT network 458 const soclib::common::MappingTable &mtx, // Mapping table RAM network 459 const soclib::common::IntTab &srcid_x, // global index RAM network 460 const soclib::common::IntTab &tgtid_d, // global index INT network 461 const size_t cc_global_id, // global index CC network 389 462 const size_t nways, // Number of ways per set 390 463 const size_t nsets, // Number of sets 391 464 const size_t nwords, // Number of words per line 392 const size_t max_copies, // max number of copies in heap393 const size_t heap_size= 1024, // number of heap entries394 const size_t trt_lines=TR ANSACTION_TAB_LINES,395 const size_t upt_lines=UP DATE_TAB_LINES,465 const size_t max_copies, // max number of copies 466 const size_t heap_size=HEAP_ENTRIES, 467 const size_t trt_lines=TRT_ENTRIES, 468 const size_t upt_lines=UPT_ENTRIES, 396 469 const size_t debug_start_cycle=0, 397 470 const bool debug_ok=false ); … … 401 474 void print_stats(); 402 475 void print_trace(); 403 void copies_monitor( vci_addr_t addr);404 void start_monitor( vci_addr_t addr, vci_addr_t length);476 void copies_monitor(addr_t addr); 477 void start_monitor(addr_t addr, addr_t length); 405 478 void stop_monitor(); 406 479 … … 409 482 void transition(); 410 483 void genMoore(); 411 void check_monitor( const char *buf, vci_addr_t addr, data_t data); 412 void check_monitor_read( const char *buf, vci_addr_t addr); 484 void check_monitor( const char *buf, addr_t addr, data_t data, bool read); 413 485 414 486 // Component attributes 415 std::list<soclib::common::Segment> m_seglist; // segments allocated to memcache487 std::list<soclib::common::Segment> m_seglist; // segments allocated 416 488 size_t m_nseg; // number of segments 417 489 soclib::common::Segment **m_seg; // array of segments pointers 418 const size_t m_srcid_x; // global index on external network 490 size_t m_seg_config; // config segment index 491 const size_t m_srcid_x; // global index on RAM network 419 492 const size_t m_initiators; // Number of initiators 420 493 const size_t m_heap_size; // Size of the heap … … 434 507 size_t m_max_copies; // max number of copies in heap 435 508 GenericLLSCGlobalTable 436 < 32 , // number of slots 437 4096, // number of processors in the system 438 8000, // registratioçn life span (in # of LL operations) 439 typename vci_param::fast_addr_t > // address type 440 m_llsc_table; // ll/sc global registration table 509 < 32 , // number of slots 510 4096, // number of processors in the system 511 8000, // registration life (# of LL operations) 512 addr_t > m_llsc_table; // ll/sc registration table 441 513 442 514 // adress masks 443 const soclib::common::AddressMaskingTable< vci_addr_t> m_x;444 const soclib::common::AddressMaskingTable< vci_addr_t> m_y;445 const soclib::common::AddressMaskingTable< vci_addr_t> m_z;446 const soclib::common::AddressMaskingTable< vci_addr_t> m_nline;515 const soclib::common::AddressMaskingTable<addr_t> m_x; 516 const soclib::common::AddressMaskingTable<addr_t> m_y; 517 const soclib::common::AddressMaskingTable<addr_t> m_z; 518 const soclib::common::AddressMaskingTable<addr_t> m_nline; 447 519 448 520 // broadcast address 449 uint32_t m_broadcast_address;521 uint32_t m_broadcast_boundaries; 450 522 451 523 ////////////////////////////////////////////////// … … 453 525 ////////////////////////////////////////////////// 454 526 527 sc_signal<int> r_tgt_cmd_fsm; 528 455 529 // Fifo between TGT_CMD fsm and READ fsm 456 GenericFifo< uint64_t>m_cmd_read_addr_fifo;530 GenericFifo<addr_t> m_cmd_read_addr_fifo; 457 531 GenericFifo<size_t> m_cmd_read_length_fifo; 458 532 GenericFifo<size_t> m_cmd_read_srcid_fifo; … … 461 535 462 536 // Fifo between TGT_CMD fsm and WRITE fsm 463 GenericFifo< uint64_t>m_cmd_write_addr_fifo;537 GenericFifo<addr_t> m_cmd_write_addr_fifo; 464 538 GenericFifo<bool> m_cmd_write_eop_fifo; 465 539 GenericFifo<size_t> m_cmd_write_srcid_fifo; … … 470 544 471 545 // Fifo between TGT_CMD fsm and CAS fsm 472 GenericFifo< uint64_t>m_cmd_cas_addr_fifo;546 GenericFifo<addr_t> m_cmd_cas_addr_fifo; 473 547 GenericFifo<bool> m_cmd_cas_eop_fifo; 474 548 GenericFifo<size_t> m_cmd_cas_srcid_fifo; … … 477 551 GenericFifo<data_t> m_cmd_cas_wdata_fifo; 478 552 479 // Fifo between INIT_RSPfsm and CLEANUP fsm553 // Fifo between CC_RECEIVE fsm and CLEANUP fsm 480 554 GenericFifo<uint64_t> m_cc_receive_to_cleanup_fifo; 481 555 482 // Fifo between INIT_RSPfsm and MULTI_ACK fsm556 // Fifo between CC_RECEIVE fsm and MULTI_ACK fsm 483 557 GenericFifo<uint64_t> m_cc_receive_to_multi_ack_fifo; 484 558 485 sc_signal<int> r_tgt_cmd_fsm; 559 // Buffer between TGT_CMD fsm and TGT_RSP fsm 560 // (segmentation violation response request) 561 sc_signal<bool> r_tgt_cmd_to_tgt_rsp_req; 562 563 sc_signal<uint32_t> r_tgt_cmd_to_tgt_rsp_rdata; 564 sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_error; 565 sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_srcid; 566 sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_trdid; 567 sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_pktid; 568 569 sc_signal<addr_t> r_tgt_cmd_config_addr; 570 sc_signal<size_t> r_tgt_cmd_config_cmd; 571 572 /////////////////////////////////////////////////////// 573 // Registers controlled by the CONFIG fsm 574 /////////////////////////////////////////////////////// 575 576 sc_signal<int> r_config_fsm; // FSM state 577 sc_signal<bool> r_config_lock; // lock protecting exclusive access 578 sc_signal<int> r_config_cmd; // config request status 579 sc_signal<addr_t> r_config_address; // target buffer physical address 580 sc_signal<size_t> r_config_srcid; // config request srcid 581 sc_signal<size_t> r_config_trdid; // config request trdid 582 sc_signal<size_t> r_config_pktid; // config request pktid 583 sc_signal<size_t> r_config_nlines; // number of lines covering the buffer 584 sc_signal<size_t> r_config_dir_way; // DIR: selected way 585 sc_signal<size_t> r_config_dir_count; // DIR: number of copies 586 sc_signal<bool> r_config_dir_is_cnt; // DIR: counter mode (broadcast required) 587 sc_signal<size_t> r_config_dir_copy_srcid; // DIR: first copy SRCID 588 sc_signal<bool> r_config_dir_copy_inst; // DIR: first copy L1 type 589 sc_signal<size_t> r_config_dir_next_ptr; // DIR: index of next copy in HEAP 590 sc_signal<size_t> r_config_heap_next; // current pointer to scan HEAP 591 592 sc_signal<size_t> r_config_upt_index; // UPT index 593 594 // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache) 595 sc_signal<bool> r_config_to_tgt_rsp_req; // valid request 596 sc_signal<bool> r_config_to_tgt_rsp_error; // error response 597 sc_signal<size_t> r_config_to_tgt_rsp_srcid; // Transaction srcid 598 sc_signal<size_t> r_config_to_tgt_rsp_trdid; // Transaction trdid 599 sc_signal<size_t> r_config_to_tgt_rsp_pktid; // Transaction pktid 600 601 // Buffer between CONFIG fsm and CC_SEND fsm (multi-inval / broadcast-inval) 602 sc_signal<bool> r_config_to_cc_send_multi_req; // multi-inval request 603 sc_signal<bool> r_config_to_cc_send_brdcast_req; // broadcast-inval request 604 sc_signal<addr_t> r_config_to_cc_send_nline; // line index 605 sc_signal<size_t> r_config_to_cc_send_trdid; // UPT index 606 GenericFifo<bool> m_config_to_cc_send_inst_fifo; // fifo for the L1 type 607 GenericFifo<size_t> m_config_to_cc_send_srcid_fifo; // fifo for owners srcid 608 609 #if L1_MULTI_CACHE 610 GenericFifo<size_t> m_config_to_cc_send_cache_id_fifo; // fifo for cache_id 611 #endif 486 612 487 613 /////////////////////////////////////////////////////// … … 489 615 /////////////////////////////////////////////////////// 490 616 491 sc_signal<int> r_read_fsm; // FSM state 492 sc_signal<size_t> r_read_copy; // Srcid of the first copy 493 sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy 494 sc_signal<bool> r_read_copy_inst; // Type of the first copy 495 sc_signal<tag_t> r_read_tag; // cache line tag (in directory) 496 sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory) 497 sc_signal<bool> r_read_lock; // lock bit (in directory) 498 sc_signal<bool> r_read_dirty; // dirty bit (in directory) 499 sc_signal<size_t> r_read_count; // number of copies 500 sc_signal<size_t> r_read_ptr; // pointer to the heap 501 sc_signal<data_t> * r_read_data; // data (one cache line) 502 sc_signal<size_t> r_read_way; // associative way (in cache) 503 sc_signal<size_t> r_read_trt_index; // Transaction Table index 504 sc_signal<size_t> r_read_next_ptr; // Next entry to point to 505 sc_signal<bool> r_read_last_free; // Last free entry 506 sc_signal<typename vci_param::fast_addr_t> 507 r_read_ll_key; // LL key returned by the llsc_global_table 617 sc_signal<int> r_read_fsm; // FSM state 618 sc_signal<size_t> r_read_copy; // Srcid of the first copy 619 sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy 620 sc_signal<bool> r_read_copy_inst; // Type of the first copy 621 sc_signal<tag_t> r_read_tag; // cache line tag (in directory) 622 sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory) 623 sc_signal<bool> r_read_lock; // lock bit (in directory) 624 sc_signal<bool> r_read_dirty; // dirty bit (in directory) 625 sc_signal<size_t> r_read_count; // number of copies 626 sc_signal<size_t> r_read_ptr; // pointer to the heap 627 sc_signal<data_t> * r_read_data; // data (one cache line) 628 sc_signal<size_t> r_read_way; // associative way (in cache) 629 sc_signal<size_t> r_read_trt_index; // Transaction Table index 630 sc_signal<size_t> r_read_next_ptr; // Next entry to point to 631 sc_signal<bool> r_read_last_free; // Last free entry 632 sc_signal<addr_t> r_read_ll_key; // LL key from the llsc_global_table 508 633 509 634 // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM) … … 520 645 sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response 521 646 sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response 522 sc_signal<typename vci_param::fast_addr_t> 523 r_read_to_tgt_rsp_ll_key; // LL key returned by the llsc_global_table 647 sc_signal<addr_t> r_read_to_tgt_rsp_ll_key; // LL key from the llsc_global_table 524 648 525 649 /////////////////////////////////////////////////////////////// … … 578 702 GenericFifo<bool> m_write_to_cc_send_inst_fifo; // fifo for the L1 type 579 703 GenericFifo<size_t> m_write_to_cc_send_srcid_fifo; // fifo for srcids 704 580 705 #if L1_MULTI_CACHE 581 706 GenericFifo<size_t> m_write_to_cc_send_cache_id_fifo; // fifo for srcids … … 596 721 sc_signal<size_t> r_multi_ack_pktid; // pending write pktid 597 722 sc_signal<addr_t> r_multi_ack_nline; // pending write nline 723 724 // signaling completion of multi-inval to CONFIG fsm 725 sc_signal<bool> r_multi_ack_to_config_ack; 598 726 599 727 // Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction) … … 633 761 sc_signal<size_t> r_cleanup_way; // associative way (in cache) 634 762 635 sc_signal<size_t> r_cleanup_write_srcid; // srcid of write r esponse763 sc_signal<size_t> r_cleanup_write_srcid; // srcid of write rsp 636 764 sc_signal<size_t> r_cleanup_write_trdid; // trdid of write rsp 637 765 sc_signal<size_t> r_cleanup_write_pktid; // pktid of write rsp 638 sc_signal<bool> r_cleanup_write_need_rsp;// needs a write rsp 766 767 sc_signal<bool> r_cleanup_need_rsp; // write response required 768 sc_signal<bool> r_cleanup_need_ack; // config acknowledge required 639 769 640 770 sc_signal<size_t> r_cleanup_index; // index of the INVAL line (in the UPT) 641 771 772 // signaling completion of broadcast-inval to CONFIG fsm 773 sc_signal<bool> r_cleanup_to_config_ack; 774 642 775 // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1) 643 776 sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request … … 703 836 GenericFifo<bool> m_cas_to_cc_send_inst_fifo; // fifo for the L1 type 704 837 GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo; // fifo for srcids 838 705 839 #if L1_MULTI_CACHE 706 840 GenericFifo<size_t> m_cas_to_cc_send_cache_id_fifo; // fifo for srcids … … 749 883 sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length; // length of the response 750 884 sc_signal<bool> r_xram_rsp_to_tgt_rsp_rerror; // send error to requester 751 sc_signal<typename vci_param::fast_addr_t> 752 r_xram_rsp_to_tgt_rsp_ll_key; // LL key returned by the llsc_global_table 885 sc_signal<addr_t> r_xram_rsp_to_tgt_rsp_ll_key; // LL key from llsc_global_table 753 886 754 887 // Buffer between XRAM_RSP fsm and CC_SEND fsm (Inval L1 Caches) … … 759 892 GenericFifo<bool> m_xram_rsp_to_cc_send_inst_fifo; // fifo for the L1 type 760 893 GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo; // fifo for srcids 894 761 895 #if L1_MULTI_CACHE 762 896 GenericFifo<size_t> m_xram_rsp_to_cc_send_cache_id_fifo; // fifo for srcids
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