Index: branches/v5/modules/vci_cc_vcache_wrapper/caba/metadata/vci_cc_vcache_wrapper.sd
===================================================================
--- branches/v5/modules/vci_cc_vcache_wrapper/caba/metadata/vci_cc_vcache_wrapper.sd	(revision 369)
+++ branches/v5/modules/vci_cc_vcache_wrapper/caba/metadata/vci_cc_vcache_wrapper.sd	(revision 443)
@@ -7,4 +7,6 @@
 	    tmpl_parameters = [
             parameter.Module('vci_param', default = 'caba:vci_param'),
+            parameter.Int('dspin_in_width'),
+            parameter.Int('dspin_out_width'),
 	        parameter.Module('iss_t')
         ],
@@ -20,28 +22,23 @@
 	        Uses('caba:multi_write_buffer'),
 	        Uses('caba:generic_fifo'),
-	        Uses(
-                'caba:generic_cache_tsar',
+	        Uses('caba:generic_cache_tsar',
                 addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', 
-                parameter.Reference('addr_size'))
-            ),
-            Uses(
-                'caba:generic_tlb', 
+                parameter.Reference('addr_size'))),
+            Uses('caba:generic_tlb', 
                 addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', 
-                parameter.Reference('addr_size'))
-            ),
-            Uses(
-                'common:address_masking_table', 
+                parameter.Reference('addr_size'))),
+            Uses('common:address_masking_table', 
                 data_t = parameter.StringExt('sc_dt::sc_uint<%d> ', 
                 parameter.Reference('addr_size'))
             ),
-			Uses(
-                'caba:dspin_dhccp_param'
-			  ),
+			Uses('caba:dspin_dhccp_param'),
         ],
 
 	    ports = [
-            Port('caba:vci_initiator', 'p_vci_ini_d'),
-            Port('caba:dspin_input', 'p_dspin_in', dspin_data_size = 40),
-            Port('caba:dspin_output', 'p_dspin_out', dspin_data_size = 33),
+            Port('caba:vci_initiator', 'p_vci'),
+            Port('caba:dspin_input', 'p_dspin_in', 
+                  dspin_data_size = parameter.Reference('dspin_in_width')),
+            Port('caba:dspin_output', 'p_dspin_out', 
+                  dspin_data_size = parameter.Reference('dspin_out_width')),
 	        Port('caba:bit_in','p_irq', parameter.Constant('n_irq')),
 	        Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
Index: branches/v5/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
===================================================================
--- branches/v5/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 369)
+++ branches/v5/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 443)
@@ -55,23 +55,17 @@
 
 ////////////////////////////////////////////
-template<typename vci_param, typename iss_t>
+template<typename vci_param, 
+         size_t   dspin_in_width,
+         size_t   dspin_out_width,
+         typename iss_t>
 class VciCcVCacheWrapper
 ////////////////////////////////////////////
     : public soclib::caba::BaseModule
 {
-    typedef uint32_t vaddr_t;
-    typedef uint32_t tag_t;
-    typedef uint32_t type_t;
-    typedef typename iss_t::DataOperationType data_op_t;
-
-    typedef typename vci_param::addr_t  paddr_t;
-    typedef typename vci_param::data_t  vci_data_t;
-    typedef typename vci_param::be_t    vci_be_t;
-    typedef typename vci_param::srcid_t vci_srcid_t;
-    typedef typename vci_param::trdid_t vci_trdid_t;
-    typedef typename vci_param::pktid_t vci_pktid_t;
-    typedef typename vci_param::plen_t  vci_plen_t;
-
-    enum icache_fsm_state_e {
+
+    typedef typename vci_param::fast_addr_t  paddr_t;
+
+    enum icache_fsm_state_e 
+    {
         ICACHE_IDLE,
         // handling XTN processor requests
@@ -101,5 +95,6 @@
     };
 
-    enum dcache_fsm_state_e {
+    enum dcache_fsm_state_e 
+    {
         DCACHE_IDLE,
         // handling itlb & dtlb miss
@@ -151,5 +146,6 @@
     };
 
-    enum cmd_fsm_state_e {
+    enum cmd_fsm_state_e 
+    {
         CMD_IDLE,
         CMD_INS_MISS,
@@ -163,5 +159,6 @@
     };
 
-    enum rsp_fsm_state_e {
+    enum rsp_fsm_state_e 
+    {
         RSP_IDLE,
         RSP_INS_MISS,
@@ -173,5 +170,6 @@
     };
 
-    enum cc_receive_fsm_state_e {
+    enum cc_receive_fsm_state_e 
+    {
         CC_RECEIVE_IDLE,
         CC_RECEIVE_CLACK,
@@ -185,5 +183,6 @@
     };
 
-    enum cc_send_fsm_state_e {
+    enum cc_send_fsm_state_e 
+    {
         CC_SEND_IDLE,
         CC_SEND_CLEANUP_1,
@@ -221,5 +220,6 @@
 
     // cc_send_type
-    typedef enum {
+    typedef enum 
+    {
         CC_TYPE_CLEANUP,
         CC_TYPE_MULTI_ACK,
@@ -227,5 +227,6 @@
 
     // cc_receive_type
-    typedef enum {
+    typedef enum 
+    {
         CC_TYPE_CLACK,
         CC_TYPE_BRDCAST,
@@ -235,5 +236,6 @@
 
     // TLB Mode : ITLB / DTLB / ICACHE / DCACHE
-    enum {
+    enum 
+    {
         INS_TLB_MASK    = 0x8,
         DATA_TLB_MASK   = 0x4,
@@ -283,10 +285,10 @@
 
 public:
-    sc_in<bool>                             p_clk;
-    sc_in<bool>                             p_resetn;
-    sc_in<bool>                             p_irq[iss_t::n_irq];
-    soclib::caba::VciInitiator<vci_param>   p_vci;
-    soclib::caba::DspinInput <40>           p_dspin_in;
-    soclib::caba::DspinOutput<33>           p_dspin_out;
+    sc_in<bool>                                 p_clk;
+    sc_in<bool>                                 p_resetn;
+    sc_in<bool>                                 p_irq[iss_t::n_irq];
+    soclib::caba::VciInitiator<vci_param>       p_vci;
+    soclib::caba::DspinInput <dspin_in_width>   p_dspin_in;
+    soclib::caba::DspinOutput<dspin_out_width>  p_dspin_out;
 
 private:
@@ -295,5 +297,5 @@
     soclib::common::AddressDecodingTable<uint32_t, bool> m_cacheability_table;
 
-    const vci_srcid_t                   m_srcid;
+    const size_t                        m_srcid;
     const size_t                        m_cc_global_id;
     const size_t                        m_nline_width;
@@ -327,12 +329,9 @@
 
     /////////////////////////////////////////////
-    // debug variables (for each FSM)
+    // debug variables 
     /////////////////////////////////////////////
-    bool                                m_debug_previous_hit;
-    bool                                m_idebug_previous_hit;
-    bool                                m_debug_dcache_fsm;
-    bool                                m_debug_icache_fsm;
-    bool                                m_debug_inval_itlb_fsm;
-    bool                                m_debug_inval_dtlb_fsm;
+    bool                                m_debug_previous_i_hit;
+    bool                                m_debug_previous_d_hit;
+    bool                                m_debug_activated;
 
     ///////////////////////////////
@@ -401,5 +400,5 @@
     sc_signal<uint32_t>     r_dcache_save_vaddr;        // virtual address (from proc)
     sc_signal<uint32_t>     r_dcache_save_wdata;        // write data (from proc)
-    sc_signal<vci_be_t>     r_dcache_save_be;           // byte enable (from proc)
+    sc_signal<uint32_t>     r_dcache_save_be;           // byte enable (from proc)
     sc_signal<paddr_t>      r_dcache_save_paddr;        // physical address
     sc_signal<bool>         r_dcache_save_cacheable;	// address cacheable
@@ -416,5 +415,5 @@
     sc_signal<bool>         r_dcache_vci_miss_req;      // read miss request
     sc_signal<bool>         r_dcache_vci_unc_req;       // uncacheable read request
-    sc_signal<bool>         r_dcache_vci_unc_be;        // uncacheable read byte enable
+    sc_signal<uint32_t>     r_dcache_vci_unc_be;        // uncacheable read byte enable
     sc_signal<bool>         r_dcache_vci_cas_req;       // atomic write request CAS
     sc_signal<uint32_t>     r_dcache_vci_cas_old;       // previous data value for a CAS
@@ -422,5 +421,5 @@
     sc_signal<bool>         r_dcache_vci_ll_req;        // atomic read request LL
     sc_signal<bool>         r_dcache_vci_sc_req;        // atomic write request SC
-    sc_signal<vci_data_t>   r_dcache_vci_sc_data;       // SC data (command)
+    sc_signal<uint32_t>     r_dcache_vci_sc_data;       // SC data (command)
 
     // register used for XTN inval
@@ -479,6 +478,9 @@
 
     // dcache directory extension
-    bool                    *r_dcache_in_tlb;           // copy exist in dtlb or itlb
-    bool                    *r_dcache_contains_ptd;     // cache line contains a PTD
+    bool                    *r_dcache_in_tlb;               // copy exist in dtlb or itlb
+    bool                    *r_dcache_contains_ptd;         // cache line contains a PTD
+
+    // Physical address extension for data access
+    sc_signal<uint32_t>     r_dcache_paddr_ext;             // CP2 register (if vci_address > 32)
 
     ///////////////////////////////////
@@ -486,8 +488,8 @@
     ///////////////////////////////////
     sc_signal<int>          r_vci_cmd_fsm;
-    sc_signal<size_t>       r_vci_cmd_min;      	    // used for write bursts
-    sc_signal<size_t>       r_vci_cmd_max;      	    // used for write bursts
-    sc_signal<size_t>       r_vci_cmd_cpt;    		    // used for write bursts
-    sc_signal<bool>         r_vci_cmd_imiss_prio;	    // round-robin between imiss & dmiss
+    sc_signal<size_t>       r_vci_cmd_min;      	        // used for write bursts
+    sc_signal<size_t>       r_vci_cmd_max;      	        // used for write bursts
+    sc_signal<size_t>       r_vci_cmd_cpt;    		        // used for write bursts
+    sc_signal<bool>         r_vci_cmd_imiss_prio;	        // round-robin between imiss & dmiss
 
     ///////////////////////////////////
@@ -498,21 +500,21 @@
     sc_signal<bool>         r_vci_rsp_ins_error;
     sc_signal<bool>         r_vci_rsp_data_error;
-    GenericFifo<uint32_t>   r_vci_rsp_fifo_icache;	    // response FIFO to ICACHE FSM
-    GenericFifo<uint32_t>   r_vci_rsp_fifo_dcache;	    // response FIFO to DCACHE FSM
+    GenericFifo<uint32_t>   r_vci_rsp_fifo_icache;	        // response FIFO to ICACHE FSM
+    GenericFifo<uint32_t>   r_vci_rsp_fifo_dcache;	        // response FIFO to DCACHE FSM
 
     ///////////////////////////////////
     //  CC_SEND FSM REGISTER
     ///////////////////////////////////
-    sc_signal<int>          r_cc_send_fsm;          // state register
-    sc_signal<bool>         r_cc_send_last_client;  // round robin flip-flop : 0 dcache / 1 icache
+    sc_signal<int>          r_cc_send_fsm;                  // state register
+    sc_signal<bool>         r_cc_send_last_client;          // 0 dcache / 1 icache
 
     ///////////////////////////////////
     //  CC_RECEIVE FSM REGISTER
     ///////////////////////////////////
-    sc_signal<int>          r_cc_receive_fsm;          // state register
-    sc_signal<bool>         r_cc_receive_data_ins;     // request concerning : 0 dcache / 1 icache
-
-    // communication cc updt FIFO between CC_RECEIVE FSM and ICACHE/DCACHE FSM
-    sc_signal<size_t>       r_cc_receive_word_idx;  // word index
+    sc_signal<int>          r_cc_receive_fsm;               // state register
+    sc_signal<bool>         r_cc_receive_data_ins;          // request to : 0 dcache / 1 icache
+
+    // communication between CC_RECEIVE FSM and ICACHE/DCACHE FSM
+    sc_signal<size_t>       r_cc_receive_word_idx;          // word index
     GenericFifo<uint32_t>   r_cc_receive_updt_fifo_be;
     GenericFifo<uint32_t>   r_cc_receive_updt_fifo_data;
@@ -520,18 +522,18 @@
 
     // communication between CC_RECEIVE FSM and ICACHE FSM
-    sc_signal<bool>         r_cc_receive_icache_req;       // cc_receive to icache request
-    sc_signal<cc_receive_t> r_cc_receive_icache_type;      // cc_receive type of coherence request
-    sc_signal<size_t>       r_cc_receive_icache_way;       // cc_receive to icache way
-    sc_signal<size_t>       r_cc_receive_icache_set;       // cc_receive to icache set
+    sc_signal<bool>         r_cc_receive_icache_req;        // cc_receive to icache request
+    sc_signal<cc_receive_t> r_cc_receive_icache_type;       // cc_receive type of request
+    sc_signal<size_t>       r_cc_receive_icache_way;        // cc_receive to icache way
+    sc_signal<size_t>       r_cc_receive_icache_set;        // cc_receive to icache set
     sc_signal<size_t>       r_cc_receive_icache_updt_tab_idx;  // cc_receive update table index
-    sc_signal<paddr_t>      r_cc_receive_icache_nline;	   // cache line physical address
+    sc_signal<paddr_t>      r_cc_receive_icache_nline;	    // cache line physical address
 
     // communication between CC_RECEIVE FSM and DCACHE FSM
-    sc_signal<bool>         r_cc_receive_dcache_req;       // cc_receive to dcache request
-    sc_signal<cc_receive_t> r_cc_receive_dcache_type;      // cc_receive type of coherence request
-    sc_signal<size_t>       r_cc_receive_dcache_way;       // cc_receive to dcache way
-    sc_signal<size_t>       r_cc_receive_dcache_set;       // cc_receive to dcache set
+    sc_signal<bool>         r_cc_receive_dcache_req;        // cc_receive to dcache request
+    sc_signal<cc_receive_t> r_cc_receive_dcache_type;       // cc_receive type of request
+    sc_signal<size_t>       r_cc_receive_dcache_way;        // cc_receive to dcache way
+    sc_signal<size_t>       r_cc_receive_dcache_set;        // cc_receive to dcache set
     sc_signal<size_t>       r_cc_receive_dcache_updt_tab_idx;  // cc_receive update table index
-    sc_signal<paddr_t>      r_cc_receive_dcache_nline;	   // cache line physical address
+    sc_signal<paddr_t>      r_cc_receive_dcache_nline;	    // cache line physical address
 
     //////////////////////////////////////////////////////////////////
@@ -675,4 +677,7 @@
 
     uint32_t m_cpt_stop_simulation;		// used to stop simulation if frozen
+    bool     m_monitor_ok;		        // used to debug cache output  
+    uint32_t m_monitor_base;		    
+    uint32_t m_monitor_length;		    
 
 protected:
@@ -711,6 +716,9 @@
     void print_trace(size_t mode = 0);
     void cache_monitor(paddr_t addr);
-    inline void iss_set_debug_mask(uint v) {
-	r_iss.set_debug_mask(v);
+    void start_monitor(paddr_t,paddr_t);
+    void stop_monitor();
+    inline void iss_set_debug_mask(uint v) 
+    {
+	    r_iss.set_debug_mask(v);
     }
 
Index: branches/v5/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
===================================================================
--- branches/v5/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 369)
+++ branches/v5/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 443)
@@ -34,5 +34,5 @@
 #define DEBUG_DCACHE		1
 #define DEBUG_ICACHE		1
-#define DEBUG_CLEANUP		1
+#define DEBUG_CMD   		0
 
 namespace soclib {
@@ -96,5 +96,5 @@
         "DCACHE_XTN_DT_INVAL",
 
-        "DCACHE_DIRTY_PTE_GET",
+        "DCACHE_DIRTY_GET_PTE",
         "DCACHE_DIRTY_WAIT",
 
@@ -130,4 +130,22 @@
     };
 
+const char *vci_pktid_type_str[] = {
+        "TYPE_READ_DATA_UNC",
+        "TYPE_READ_DATA_MISS",            
+        "TYPE_READ_INS_UNC",          
+        "TYPE_READ_INS_MISS",
+        "TYPE_WRITE",
+        "TYPE_CAS",
+        "TYPE_LL",
+        "TYPE_SC",
+    };
+
+const char *vci_cmd_type_str[] = {
+        "NOP or STORE_COND",
+        "READ",
+        "WRITE",
+        "LOCKED_READ"
+    };
+
 const char *rsp_fsm_state_str[] = {
         "RSP_IDLE",
@@ -160,5 +178,10 @@
 }
 
-#define tmpl(...)  template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapper<vci_param, iss_t>
+#define tmpl(...) \
+   template<typename vci_param, \
+            size_t   dspin_in_width, \
+            size_t   dspin_out_width, \
+            typename iss_t> __VA_ARGS__ \
+   VciCcVCacheWrapper<vci_param, dspin_in_width, dspin_out_width, iss_t>
 
 using namespace soclib::common;
@@ -375,4 +398,6 @@
       r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
 {
+    std::cout << "  - Building VciCcVcacheWrapper : " << name << std::endl;
+
     assert( ((icache_words*vci_param::B) < (1<<vci_param::K)) and
              "Need more PLEN bits.");
@@ -459,5 +484,6 @@
               << " | " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
               << " | " << cc_receive_fsm_state_str[r_cc_receive_fsm.read()]
-              << " | " << cc_send_fsm_state_str[r_cc_send_fsm.read()];
+              << " | " << cc_send_fsm_state_str[r_cc_send_fsm.read()]
+              << " | MMU = " << r_mmu_mode.read();
     if (r_dcache_updt_req.read() ) std::cout << " | P1_UPDT";
     if (r_dcache_wbuf_req.read() ) std::cout << " | P1_WBUF";
@@ -494,33 +520,42 @@
 //////////////////////////////////////////
 {
-    size_t	cache_way;
-    size_t	cache_set;
-    size_t	cache_word;
-    uint32_t	cache_rdata;
-    bool	cache_hit = r_dcache.read_neutral( addr,
-                                           &cache_rdata,
-                                           &cache_way,
-                                           &cache_set,
-                                           &cache_word );
-    bool	icache_hit = r_icache.read_neutral( addr,
-                                           &cache_rdata,
-                                           &cache_way,
-                                           &cache_set,
-                                           &cache_word );
-    if ( cache_hit != m_debug_previous_hit )
-    {
-        std::cout << "PROC " << name()
-                  << " dcache change at cycle " << std::dec << m_cpt_total_cycles
-                  << " for adresse " << std::hex << addr
-                  << " / HIT = " << std::dec << cache_hit << std::endl;
-	m_debug_previous_hit = cache_hit;
-    }
-    if ( icache_hit != m_idebug_previous_hit )
-    {
-        std::cout << "PROC " << name()
-                  << " icache change at cycle " << std::dec << m_cpt_total_cycles
-                  << " for adresse " << std::hex << addr
-                  << " / HIT = " << icache_hit << std::endl;
-	m_idebug_previous_hit = icache_hit;
+    bool        cache_hit;
+    size_t	    cache_way = 0;
+    size_t	    cache_set = 0;
+    size_t	    cache_word = 0;
+    uint32_t	cache_rdata = 0;
+
+    cache_hit = r_dcache.read_neutral( addr,
+                                       &cache_rdata,
+                                       &cache_way,
+                                       &cache_set,
+                                       &cache_word );
+
+    if ( cache_hit != m_debug_previous_d_hit )
+    {
+        std::cout << "Monitor PROC " << name()
+                  << " DCACHE at cycle " << std::dec << m_cpt_total_cycles
+                  << " / HIT = " << cache_hit 
+                  << " / PADDR = " << std::hex << addr
+                  << " / DATA = " << cache_rdata 
+                  << " / WAY = " << cache_way << std::endl;
+	    m_debug_previous_d_hit = cache_hit;
+    }
+
+    cache_hit = r_icache.read_neutral( addr,
+                                       &cache_rdata,
+                                       &cache_way,
+                                       &cache_set,
+                                       &cache_word );
+
+    if ( cache_hit != m_debug_previous_i_hit )
+    {
+        std::cout << "Monitor PROC " << name()
+                  << " ICACHE at cycle " << std::dec << m_cpt_total_cycles
+                  << " / HIT = " << cache_hit 
+                  << " / PADDR = " << std::hex << addr
+                  << " / DATA = " << cache_rdata 
+                  << " / WAY = " << cache_way << std::endl;
+	    m_debug_previous_i_hit = cache_hit;
     }
 }
@@ -676,5 +711,4 @@
 /////////////////////////
 {
-    #define LLSCLocalTable GenericLLSCLocalTable<8000, 1, paddr_t, vci_trdid_t, vci_data_t>
     if ( not p_resetn.read() )
     {
@@ -693,4 +727,7 @@
         r_cc_send_fsm     = CC_SEND_IDLE;
 
+        // reset data physical address extension
+        r_dcache_paddr_ext = 0;
+
         // reset dcache directory extension
         for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++)
@@ -705,4 +742,5 @@
 
         // ICACHE & DCACHE activated
+        // ITLB & DTLB desactivated
         r_mmu_mode = 0x3;
 
@@ -757,8 +795,7 @@
 
         // Debug variables
-        m_debug_previous_hit       = false;
-        m_idebug_previous_hit      = false;
-        m_debug_dcache_fsm	       = false;
-        m_debug_icache_fsm	       = false;
+        m_debug_previous_i_hit     = false;
+        m_debug_previous_d_hit     = false;
+        m_debug_activated	       = false;
 
         // activity counters
@@ -869,4 +906,5 @@
         // init the llsc reservation buffer
         r_dcache_llsc_valid = false;
+        m_monitor_ok = false;
 
         return;
@@ -900,6 +938,5 @@
     m_cpt_total_cycles++;
 
-    m_debug_icache_fsm     = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
-    m_debug_dcache_fsm     = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
+    m_debug_activated = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
 
     /////////////////////////////////////////////////////////////////////
@@ -1151,5 +1188,10 @@
                     // we request a VCI transaction
                     r_icache_fsm      = ICACHE_MISS_SELECT;
-                    r_icache_miss_req = true;
+#if DEBUG_ICACHE
+if ( m_debug_activated )
+std::cout << "  <PROC " << name() << " ICACHE_IDLE> READ MISS in icache" 
+          << " : PADDR = " << std::hex << paddr << std::endl;
+#endif
+                   r_icache_miss_req = true;
                 }
                 else if (cache_state == CACHE_SLOT_STATE_ZOMBI )	// pending cleanup
@@ -1168,4 +1210,9 @@
                     m_irsp.instruction = cache_inst;
                     r_icache_fsm       = ICACHE_IDLE;
+#if DEBUG_ICACHE
+if ( m_debug_activated )
+std::cout << "  <PROC " << name() << " ICACHE_IDLE> READ HIT in icache" 
+          << " : PADDR = " << std::hex << paddr << std::endl;
+#endif
                 }
             }
@@ -1174,4 +1221,13 @@
                 r_icache_unc_req  = true;
                 r_icache_fsm      = ICACHE_UNC_WAIT;
+
+#if DEBUG_ICACHE
+if ( m_debug_activated )
+{
+    std::cout << "  <PROC " << name()
+              << " ICACHE_IDLE> READ UNCACHEABLE in icache" 
+              << " : PADDR = " << std::hex << paddr << std::endl;
+}
+#endif
             }
         }    // end if m_ireq.valid
@@ -1230,8 +1286,16 @@
                        		        // A cleanup request is generated for each valid line
     {
+        // coherence request (from CC_RECEIVE FSM)
+        if ( r_cc_receive_icache_req.read() )
+        {
+            r_icache_fsm = ICACHE_CC_CHECK;
+            r_icache_fsm_save = r_icache_fsm.read();
+            break;
+        }
+
         if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request is sent
         {
             int       state;
-            uint32_t  tag;
+            paddr_t   tag;
             size_t	  way = r_icache_flush_count.read()/m_icache_sets;
             size_t	  set = r_icache_flush_count.read()%m_icache_sets;
@@ -1249,5 +1313,5 @@
                 // request cleanup
                 r_icache_cc_send_req   = true;
-                r_icache_cc_send_nline = tag * m_icache_sets;
+                r_icache_cc_send_nline = tag * m_icache_sets + set;
                 r_icache_cc_send_way   = way;
                 r_icache_cc_send_type  = CC_TYPE_CLEANUP;
@@ -1467,5 +1531,5 @@
 
 #if DEBUG_ICACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -1493,5 +1557,5 @@
                             CACHE_SLOT_STATE_ZOMBI);
 #if DEBUG_ICACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -1550,5 +1614,5 @@
                             r_vci_rsp_fifo_icache.read() );
 #if DEBUG_ICACHE
-if ( m_debug_icache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -1610,5 +1674,5 @@
                                         CACHE_SLOT_STATE_ZOMBI );
 #if DEBUG_ICACHE
-if ( m_debug_icache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -1634,5 +1698,5 @@
                                     CACHE_SLOT_STATE_VALID );
 #if DEBUG_ICACHE
-if ( m_debug_icache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -1716,5 +1780,5 @@
 
 #if DEBUG_ICACHE
-if ( m_debug_icache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -1749,5 +1813,5 @@
             }
 #if DEBUG_ICACHE
-if ( m_debug_icache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -1759,8 +1823,8 @@
         else  								                            // no match
         {
-            int	        state;
-            size_t 	    way;
-            size_t 	    set;
-            size_t 	    word;
+            int	        state = 0;
+            size_t 	    way = 0;
+            size_t 	    set = 0;
+            size_t 	    word = 0;
 
 #ifdef INSTRUMENTATION
@@ -1818,5 +1882,5 @@
 
 #if DEBUG_ICACHE
-if ( m_debug_icache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -1862,5 +1926,5 @@
 
 #if DEBUG_ICACHE
-if ( m_debug_icache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -1925,5 +1989,5 @@
 
 #if DEBUG_ICACHE
-if ( m_debug_icache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -2085,5 +2149,5 @@
         size_t     	tlb_way;
         size_t     	tlb_set;
-        paddr_t    	tlb_nline;
+        paddr_t    	tlb_nline = 0;
         size_t		cache_way;
         size_t		cache_set;
@@ -2115,5 +2179,8 @@
             else                                    // identity mapping
             {
-                paddr       = (paddr_t)m_dreq.addr;
+                paddr = (paddr_t)m_dreq.addr;
+                // we take into account the paddr extension
+                if (vci_param::N > 32) 
+                    paddr = paddr | ((paddr_t)(r_dcache_paddr_ext.read()) << 32);
             }
         } // end physical address computation
@@ -2189,14 +2256,12 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_IDLE> Cache update in P1 stage" << std::dec
-              << " / WAY = " << r_dcache_save_cache_way.read()
-              << " / SET = " << r_dcache_save_cache_set.read()
-              << " / WORD = " << r_dcache_save_cache_word.read() << std::hex
-              << " / DATA = " << r_dcache_save_wdata.read()
-              << " / BE = " << r_dcache_save_be.read() << std::endl;
-}
+if ( m_debug_activated )
+std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
+          << " Cache update in P1 stage" << std::dec
+          << " / WAY = " << r_dcache_save_cache_way.read()
+          << " / SET = " << r_dcache_save_cache_set.read()
+          << " / WORD = " << r_dcache_save_cache_word.read() << std::hex
+          << " / WDATA = " << r_dcache_save_wdata.read()
+          << " / BE = " << r_dcache_save_be.read() << std::endl;
 #endif
         } // end test TLB inval
@@ -2341,4 +2406,10 @@
                     case iss_t::XTN_MMU_WORD_HI:
                         m_drsp.rdata = r_mmu_word_hi.read();
+                        m_drsp.valid = true;
+                        m_drsp.error = false;
+                        break;
+
+                    case iss_t::XTN_DATA_PADDR_EXT:
+                        m_drsp.rdata = r_dcache_paddr_ext.read();
                         m_drsp.valid = true;
                         m_drsp.error = false;
@@ -2465,4 +2536,10 @@
                         m_drsp.valid     = true;
                         r_dcache_fsm     = DCACHE_IDLE;
+                    break;
+
+                    case iss_t::XTN_DATA_PADDR_EXT:     // no cache or tlb access
+                        r_dcache_paddr_ext = m_dreq.wdata;
+                        m_drsp.valid       = true;
+                        r_dcache_fsm       = DCACHE_IDLE;
                     break;
 
@@ -2530,9 +2607,7 @@
                             m_drsp.rdata = 0;
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
-{
-    std::cout << "  <PROC " << name()
-              << ".DCACHE_IDLE> HIT in dtlb, but privilege violation" << std::endl;
-}
+if ( m_debug_activated )
+std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
+          << " HIT in dtlb, but privilege violation" << std::endl;
 #endif
                         }
@@ -2548,9 +2623,7 @@
                             m_drsp.rdata = 0;
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
-{
-    std::cout << "  <PROC " << name()
-              << ".DCACHE_IDLE> HIT in dtlb, but writable violation" << std::endl;
-}
+if ( m_debug_activated )
+std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
+          << " HIT in dtlb, but writable violation" << std::endl;
 #endif
                         }
@@ -2569,5 +2642,5 @@
                 }    // end DTLB activated
 
-                if ( valid_req ) 	// processor request is valid after TLB check
+                if ( valid_req ) 	// processor request is valid (after MMU check)
                 {
                     r_dcache_save_cacheable  = cacheable;
@@ -2593,9 +2666,8 @@
                                 r_dcache_fsm          = DCACHE_MISS_SELECT;
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
-{
-    std::cout << "  <PROC " << name()
-              << ".DCACHE_IDLE> READ MISS in dcache" << std::endl;
-}
+if ( m_debug_activated )
+std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
+          << " READ MISS in dcache" 
+          << " / PADDR = " << std::hex << paddr << std::endl;
 #endif
                             }
@@ -2604,4 +2676,10 @@
                                 // stalled until cleanup is acknowledged
                                 r_dcache_fsm   = DCACHE_IDLE;
+#if DEBUG_DCACHE
+if ( m_debug_activated )
+std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
+          << " Pending cleanup, stalled until cleanup acknowledge"
+          << " / PADDR = " << std::hex << paddr << std::endl;
+#endif
                             }
                             else                                      // cache hit
@@ -2615,9 +2693,8 @@
                                 m_drsp.rdata   = cache_rdata;
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
-{
-    std::cout << "  <PROC " << name()
-              << ".DCACHE_IDLE> READ HIT in dcache" << std::endl;
-}
+if ( m_debug_activated )
+std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
+          << " READ HIT in dcache" 
+          << " / PADDR = " << std::hex << paddr << std::endl;
 #endif
                             }
@@ -2630,9 +2707,8 @@
                             r_dcache_fsm          = DCACHE_UNC_WAIT;
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
-{
-    std::cout << "  <PROC " << name()
-              << ".DCACHE_IDLE> READ UNCACHEABLE in dcache" << std::endl;
-}
+if ( m_debug_activated )
+std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
+          << " READ UNCACHEABLE in dcache" 
+          << " / PADDR = " << std::hex << paddr << std::endl;
 #endif
                         }
@@ -2804,6 +2880,6 @@
         if ( not bypass )     // Try to read PTE1/PTD1 in dcache
         {
-            pte_paddr = (paddr_t)r_mmu_ptpr.read() << (INDEX1_NBITS+2) |
-                        (paddr_t)((r_dcache_tlb_vaddr.read() >> PAGE_M_NBITS) << 2);
+            pte_paddr = (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2)) |
+                        ((((paddr_t)r_dcache_tlb_vaddr.read()) >> PAGE_M_NBITS) << 2);
             r_dcache_tlb_paddr = pte_paddr;
             r_dcache_fsm       = DCACHE_TLB_PTE1_GET;
@@ -2818,15 +2894,12 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     if ( r_dcache_tlb_ins.read() )
-    {
-        std::cout << "  <PROC " << name() << ".DCACHE_TLB_MISS> ITLB miss";
-    }
+        std::cout << "  <PROC " << name() << " DCACHE_TLB_MISS> ITLB miss";
     else
-    {
-        std::cout << "  <PROC " << name() << ".DCACHE_TLB_MISS> DTLB miss";
-    }
+        std::cout << "  <PROC " << name() << " DCACHE_TLB_MISS> DTLB miss";
     std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
+              << " / ptpr  = " << (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2))
               << " / BYPASS = " << bypass
               << " / PTE_ADR = " << pte_paddr << std::endl;
@@ -2883,7 +2956,8 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
-    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
+    std::cout << "  <PROC " << name() 
+              << " DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
               << std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
               << std::dec << " / way = " << way
@@ -2919,7 +2993,8 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
-    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache"
+    std::cout << "  <PROC " << name() 
+              << " DCACHE_TLB_PTE1_GET> HIT in dcache"
               << std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
               << std::dec << " / way = " << way
@@ -2940,7 +3015,8 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
-    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache"
+    std::cout << "  <PROC " << name() 
+              << " DCACHE_TLB_PTE1_GET> HIT in dcache"
               << std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
               << std::dec << " / way = " << way
@@ -2966,7 +3042,8 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
-    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_GET> MISS in dcache:"
+    std::cout << "  <PROC " << name() 
+              << " DCACHE_TLB_PTE1_GET> MISS in dcache:"
               << " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
 }
@@ -3006,10 +3083,12 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     if ( r_dcache_tlb_ins.read() )
-        std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
+        std::cout << "  <PROC " << name() 
+                  << " DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
     else
-        std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
+        std::cout << "  <PROC " << name() 
+                  << ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
         std::cout << " way = " << std::dec << way
                   << " / set = " << set << std::endl;
@@ -3076,8 +3155,9 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
-    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB";
-    std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
+    std::cout << "  <PROC " << name() 
+              << " DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB"
+              << " / set = " << std::dec << r_dcache_tlb_set.read()
               << " / way = " << r_dcache_tlb_way.read() << std::endl;
     r_itlb.printTrace();
@@ -3099,8 +3179,9 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
-    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB";
-    std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
+    std::cout << "  <PROC " << name() 
+              << " DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB"
+              << " / set = " << std::dec << r_dcache_tlb_set.read()
               << " / way = " << r_dcache_tlb_way.read() << std::endl;
     r_dtlb.printTrace();
@@ -3115,7 +3196,8 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
-    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> L/R bit update required"
+    std::cout << "  <PROC " << name() 
+              << " DCACHE_TLB_PTE1_UPDT> L/R bit update required"
               << std::endl;
 }
@@ -3174,8 +3256,8 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
-              << " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE is unmapped"
+              << " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE unmapped"
               << " PTE_FLAGS = " << std::hex << pte_flags
               << " PTE_PPN = " << std::hex << pte_ppn << std::endl;
@@ -3194,7 +3276,8 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
-    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE2_GET> HIT in dcache:"
+    std::cout << "  <PROC " << name() 
+              << " DCACHE_TLB_PTE2_GET> HIT in dcache:"
               << " PTE_FLAGS = " << std::hex << pte_flags
               << " PTE_PPN = " << std::hex << pte_ppn << std::endl;
@@ -3207,4 +3290,13 @@
             // stalled until cleanup is acknowledged
             r_dcache_fsm   = DCACHE_TLB_PTE2_GET;
+
+#if DEBUG_DCACHE
+if ( m_debug_activated )
+{
+    std::cout << "  <PROC " << name() 
+              << " DCACHE_TLB_PTE2_GET> ZOMBI in dcache: waiting cleanup ack"
+              << std::endl;
+}
+#endif
         }
         else            // we must load the missing cache line in dcache
@@ -3217,5 +3309,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -3255,5 +3347,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     if ( r_dcache_tlb_ins.read() )
@@ -3331,5 +3423,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -3355,5 +3447,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -3373,5 +3465,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -3386,5 +3478,5 @@
     {
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -3431,5 +3523,5 @@
 	{
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -3446,5 +3538,5 @@
     {
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -3541,8 +3633,16 @@
                                 // returns to IDLE and flush TLBs when last slot
     {
+        // coherence request (from CC_RECEIVE FSM)
+        if ( r_cc_receive_dcache_req.read() )
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_cc_save = r_dcache_fsm.read();
+            break;
+        }
+
         if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
         {
             int       state;
-            uint32_t  tag;
+            paddr_t   tag;
             size_t    way = r_dcache_flush_count.read()/m_dcache_sets;
             size_t    set = r_dcache_flush_count.read()%m_dcache_sets;
@@ -3560,5 +3660,5 @@
                 // request cleanup
                 r_dcache_cc_send_req   = true;
-                r_dcache_cc_send_nline = tag * m_dcache_sets;
+                r_dcache_cc_send_nline = tag * m_dcache_sets + set;
                 r_dcache_cc_send_way   = way;
                 r_dcache_cc_send_type  = CC_TYPE_CLEANUP;
@@ -3664,5 +3764,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -3707,5 +3807,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -3767,5 +3867,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -3804,9 +3904,9 @@
         if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
         {
-            bool     found;
-            bool     cleanup;
-            size_t   way;
-            size_t   set;
-            paddr_t  victim;
+            bool     found = false;
+            bool     cleanup = false;
+            size_t   way = 0;
+            size_t   set = 0;
+            paddr_t  victim = 0;
 
 #ifdef INSTRUMENTATION
@@ -3841,5 +3941,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -3848,5 +3948,5 @@
               << " / SET = "   << set
               << " / PADDR = " << std::hex << r_dcache_save_paddr.read();
-    if(cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
+    if(cleanup) std::cout << " / VICTIM = " << (victim*m_dcache_words*4) << std::endl;
     else        std::cout << std::endl;
 }
@@ -3864,5 +3964,4 @@
         size_t  way   = r_dcache_miss_way.read();
         size_t  set   = r_dcache_miss_set.read();
-        paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words<<2);
 
 #ifdef INSTRUMENTATION
@@ -3873,5 +3972,5 @@
                             CACHE_SLOT_STATE_ZOMBI );
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -3886,5 +3985,5 @@
         {
             r_dcache_in_tlb[way*m_dcache_sets+set] = false;
-            r_dcache_tlb_inval_line  = nline;
+            r_dcache_tlb_inval_line  = r_dcache_cc_send_nline;
             r_dcache_tlb_inval_set   = 0;
             r_dcache_fsm_scan_save   = DCACHE_MISS_WAIT;
@@ -3995,9 +4094,9 @@
                                 r_vci_rsp_fifo_dcache.read() );
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
               << " DCACHE_MISS_DATA_UPDT> Write one word:"
-              << " / DATA = "  << r_vci_rsp_fifo_dcache.read()
+              << " / DATA = "  << std::hex << r_vci_rsp_fifo_dcache.read()
               << " / WAY = "   << std::dec << r_dcache_miss_way.read()
               << " / SET = "   << r_dcache_miss_set.read()
@@ -4038,5 +4137,5 @@
             if ( r_dcache_miss_inval.read() ) // switch slot to ZOMBI state, and new cleanup
             {
-                if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
+                if ( not r_dcache_cc_send_req.read() ) // blocked until previous request sent
                 {
                     r_dcache_miss_inval     = false;
@@ -4055,12 +4154,10 @@
                                         CACHE_SLOT_STATE_ZOMBI );
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_MISS_DIR_UPDT> Switch slot to ZOMBI state"
-              << " PADDR = " << std::hex << r_dcache_save_paddr.read()
-              << " / WAY = "   << std::dec << r_dcache_miss_way.read()
-              << " / SET = "   << r_dcache_miss_set.read() << std::endl;
-}
+if ( m_debug_activated )
+std::cout << "  <PROC " << name()
+          << " DCACHE_MISS_DIR_UPDT> Switch slot to ZOMBI state"
+          << " PADDR = " << std::hex << r_dcache_save_paddr.read()
+          << " / WAY = "   << std::dec << r_dcache_miss_way.read()
+          << " / SET = "   << r_dcache_miss_set.read() << std::endl;
 #endif
                 }
@@ -4080,16 +4177,10 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_MISS_DIR_UPDT> Switch slot to VALID state"
-              << " PADDR = " << std::hex << r_dcache_save_paddr.read()
-              << " / WAY = "   << std::dec << r_dcache_miss_way.read()
-              << " / SET = "   << r_dcache_miss_set.read() << std::endl;
-
-    r_dcache.printTrace();
-
-
-}
+if ( m_debug_activated )
+std::cout << "  <PROC " << name()
+          << " DCACHE_MISS_DIR_UPDT> Switch slot to VALID state"
+          << " PADDR = " << std::hex << r_dcache_save_paddr.read()
+          << " / WAY = "   << std::dec << r_dcache_miss_way.read()
+          << " / SET = "   << r_dcache_miss_set.read() << std::endl;
 #endif
                 // reset directory extension
@@ -4263,5 +4354,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -4303,5 +4394,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -4325,5 +4416,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -4331,7 +4422,10 @@
               << " r_dcache_vci_paddr = " << r_dcache_vci_paddr.read()
               << " mask = " << mask 
-              << " (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = " << (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT)
-              << " (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = " << (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)
-              << " ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = " << ((r_dcache_vci_paddr.read() & mask) == (paddr & mask))
+              << " (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = " 
+              << (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT)
+              << " (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = " 
+              << (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)
+              << " ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = " 
+              << ((r_dcache_vci_paddr.read() & mask) == (paddr & mask))
               <<std::endl;
 }
@@ -4361,5 +4455,5 @@
             r_cc_receive_dcache_req = false;
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -4395,5 +4489,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -4406,8 +4500,8 @@
         else                                                    // no match
 	    {
-            int        state;
-            size_t 	   way;
-            size_t 	   set;
-            size_t	   word;
+            int        state = 0;
+            size_t 	   way = 0;
+            size_t 	   set = 0;
+            size_t	   word = 0;
 
 #ifdef INSTRUMENTATION
@@ -4459,5 +4553,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -4498,5 +4592,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -4514,5 +4608,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -4570,5 +4664,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -4590,5 +4684,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -4608,5 +4702,5 @@
 
                 // wait to send a request to cc_send_fsm
-                if(not r_icache_cc_send_req.read())
+                if(not r_dcache_cc_send_req.read())
                 // cc_send is available
                 {
@@ -4663,5 +4757,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -4680,5 +4774,5 @@
                 r_dcache_cc_need_write = false;
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -4734,5 +4828,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm and ok )
+if ( m_debug_activated and ok )
 {
     std::cout << "  <PROC " << name()
@@ -4750,12 +4844,10 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm and ok )
-{
-    std::cout << "  <PROC " << name()
-              << ".DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry:" << std::hex
-              << " line = " << line << std::dec
-              << " / set = " << set
-              << " / way = " << way << std::endl;
-}
+if ( m_debug_activated and ok )
+std::cout << "  <PROC " << name() << " DCACHE_INVAL_TLB_SCAN>"
+          << " Invalidate DTLB entry" << std::hex
+          << " / line = " << line << std::dec
+          << " / set = " << set
+          << " / way = " << way << std::endl;
 #endif
         }
@@ -4847,4 +4939,5 @@
     ////////////////////////////////////////////////////////////////////////////////////
 
+
     switch ( r_vci_cmd_fsm.read() )
     {
@@ -4852,5 +4945,5 @@
         case CMD_IDLE:
         {
-            // DDACHE read requests (r_dcache_vci_miss_req or r_dcache_vci_ll_req), and
+            // DCACHE read requests (r_dcache_vci_miss_req or r_dcache_vci_ll_req), and
             // ICACHE read requests (r_icache_miss_req) require both a write_buffer access
             // to check a possible pending write on the same cache line.
@@ -4877,5 +4970,4 @@
                      or r_vci_cmd_imiss_prio.read() );
 
-
             // 1 - Data Read Miss
             if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
@@ -4911,6 +5003,6 @@
             else if ( r_icache_unc_req.read() )
             {
-                r_vci_cmd_fsm    = CMD_INS_UNC;
-                r_icache_unc_req = false;
+                r_vci_cmd_fsm       = CMD_INS_UNC;
+                r_icache_unc_req    = false;
 //                m_cpt_iunc_transaction++;
             }
@@ -4941,4 +5033,14 @@
 //              m_cpt_cas_transaction++;
             }
+
+#if DEBUG_CMD
+if ( m_debug_activated )
+{
+std::cout << "  <PROC " << name() << " CMD_IDLE>"
+          << " / dmiss_req = " << dcache_miss_req
+          << " / imiss_req = " << icache_miss_req
+          << std::endl;
+}
+#endif
             break;
         }
@@ -4977,5 +5079,7 @@
         {
             // all read VCI commands contain one single flit
-            if ( p_vci.cmdack.read() )  r_vci_cmd_fsm = CMD_IDLE;
+            if ( p_vci.cmdack.read() ) {
+                r_vci_cmd_fsm = CMD_IDLE;
+            }
             break;
         }
@@ -5172,5 +5276,5 @@
             break;
         }
-        ////////////////////
+        /////////////////
         case RSP_DATA_LL:
         {
@@ -5181,4 +5285,5 @@
                     r_vci_rsp_data_error = true;
                     r_vci_rsp_fsm = RSP_IDLE;
+                    break;
                 }
                 if (r_vci_rsp_cpt.read() == 0) //first flit
@@ -5243,6 +5348,6 @@
             // we first check for the last client and listen for //
             // a request of the other, then update the client    //
+            // r_cc_send_last_client : 0 dcache / 1 icache
             ///////////////////////////////////////////////////////
-            // r_cc_send_last_client : 0 dcache / 1 icache
             bool update_last_client = r_cc_send_last_client.read();
             if ( r_cc_send_last_client.read() == 0 ) // last client was dcache
@@ -5261,15 +5366,19 @@
             if (r_dcache_cc_send_req.read() or r_icache_cc_send_req.read())
             {
-                // test if the new client is dcache and has a cleanup request
-                if ( (update_last_client == 0) and (r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP))
+                // the new client is dcache and has a cleanup request
+                if      ( (update_last_client == 0) and 
+                          (r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP))
                     r_cc_send_fsm = CC_SEND_CLEANUP_1;
-                // test if the new client is dcache and has a multi acknowledgement request
-                else if ( (update_last_client == 0) and (r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
+                // the new client is dcache and has a multi acknowledgement request
+                else if ( (update_last_client == 0) and 
+                          (r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
                     r_cc_send_fsm = CC_SEND_MULTI_ACK;
-                // test if the new client is icache and has a cleanup request
-                else if ( (update_last_client == 1) and (r_icache_cc_send_type.read() == CC_TYPE_CLEANUP))
+                // the new client is icache and has a cleanup request
+                else if ( (update_last_client == 1) and 
+                          (r_icache_cc_send_type.read() == CC_TYPE_CLEANUP))
                     r_cc_send_fsm = CC_SEND_CLEANUP_1;
-                // test if the new client is icache and has a multi acknowledgement request
-                else if ( (update_last_client == 1) and (r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
+                // the new client is icache and has a multi acknowledgement request
+                else if ( (update_last_client == 1) and
+                        (r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
                     r_cc_send_fsm = CC_SEND_MULTI_ACK;
             }
@@ -5321,5 +5430,5 @@
     //   C_RECEIVE  FSM
     // This FSM receive all coherence packets on a DSPIN40 port.
-    // There is 4 packet types:
+    // There is 7 packet types:
     // - CC_DATA_INVAL : DCACHE invalidate request
     // - CC_DATA_UPDT  : DCACHE update request (multi-words)
@@ -5341,5 +5450,6 @@
                 uint64_t receive_data = p_dspin_in.data.read();
                 // initialize coherence packet type
-                uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_TYPE);
+                uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data,
+                                            DspinDhccpParam::FROM_MC_TYPE);
                 // initialize data/ins flip_flop (0 data / 1 ins)
                 r_cc_receive_data_ins = (bool)(receive_type & 0x1);
@@ -5376,10 +5486,15 @@
 
             // for data CLACK, wait for dcache to take the request
-            if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
+            if ((r_cc_receive_data_ins.read() == 0) and 
+                   not (r_cc_receive_dcache_req.read()))
             {
                 // request dcache to handle the CLACK
                 r_cc_receive_dcache_req  = true;
-                r_cc_receive_dcache_set  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_SET) & ((1ULL<<(uint32_log2(m_dcache_sets)))-1);
-                r_cc_receive_dcache_way  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_WAY) & ((1ULL<<(uint32_log2(m_dcache_ways)))-1);
+                r_cc_receive_dcache_set  = DspinDhccpParam::dspin_get(receive_data,
+                                           DspinDhccpParam::CLEANUP_ACK_SET) & 
+                                           ((1ULL<<(uint32_log2(m_dcache_sets)))-1);
+                r_cc_receive_dcache_way  = DspinDhccpParam::dspin_get(receive_data,
+                                           DspinDhccpParam::CLEANUP_ACK_WAY) & 
+                                           ((1ULL<<(uint32_log2(m_dcache_ways)))-1);
                 r_cc_receive_dcache_type = CC_TYPE_CLACK;
                 // get back to idle state
@@ -5388,10 +5503,15 @@
             }
             // for ins CLACK, wait for icache to take the request
-            if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
+            if ((r_cc_receive_data_ins.read() == 1) and 
+                   not (r_cc_receive_icache_req.read()))
             {
                 // request icache to handle the CLACK
                 r_cc_receive_icache_req  = true;
-                r_cc_receive_icache_set  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_SET) & ((1ULL<<(uint32_log2(m_icache_sets)))-1);
-                r_cc_receive_icache_way  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_WAY) & ((1ULL<<(uint32_log2(m_icache_ways)))-1);
+                r_cc_receive_icache_set  = DspinDhccpParam::dspin_get(receive_data,
+                                           DspinDhccpParam::CLEANUP_ACK_SET) & 
+                                           ((1ULL<<(uint32_log2(m_icache_sets)))-1);
+                r_cc_receive_icache_way  = DspinDhccpParam::dspin_get(receive_data,
+                                           DspinDhccpParam::CLEANUP_ACK_WAY) & 
+                                           ((1ULL<<(uint32_log2(m_icache_ways)))-1);
                 r_cc_receive_icache_type = CC_TYPE_CLACK;
                 // get back to idle state
@@ -5418,13 +5538,17 @@
             // not to actually post a request to an available cache => need a
             // flip_flop to check that ?
-            if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()) and (p_dspin_in.write.read()))
+            if (not (r_cc_receive_icache_req.read()) and 
+                not (r_cc_receive_dcache_req.read()) and 
+                (p_dspin_in.write.read()))
             {
                 // request dcache to handle the BROADCAST
                 r_cc_receive_dcache_req  = true;
-                r_cc_receive_dcache_nline  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::BROADCAST_NLINE);
+                r_cc_receive_dcache_nline  = DspinDhccpParam::dspin_get(receive_data,
+                                             DspinDhccpParam::BROADCAST_NLINE);
                 r_cc_receive_dcache_type = CC_TYPE_BRDCAST;
                 // request icache to handle the BROADCAST
                 r_cc_receive_icache_req  = true;
-                r_cc_receive_icache_nline  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::BROADCAST_NLINE);
+                r_cc_receive_icache_nline  = DspinDhccpParam::dspin_get(receive_data,
+                                             DspinDhccpParam::BROADCAST_NLINE);
                 r_cc_receive_icache_type = CC_TYPE_BRDCAST;
                 // get back to idle state
@@ -5441,14 +5565,18 @@
             uint64_t receive_data = p_dspin_in.data.read();
             // for data INVAL, wait for dcache to take the request
-            if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
-            {
-                r_cc_receive_dcache_updt_tab_idx  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
+            if ((r_cc_receive_data_ins.read() == 0) and 
+                 not (r_cc_receive_dcache_req.read()))
+            {
+                r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,
+                                                   DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
                 r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE;
                 break;
             }
             // for ins INVAL, wait for icache to take the request
-            if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
-            {
-                r_cc_receive_icache_updt_tab_idx  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
+            if ((r_cc_receive_data_ins.read() == 1) and 
+                 not (r_cc_receive_icache_req.read()))
+            {
+                r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,
+                                                   DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
                 r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE;
                 break;
@@ -5463,5 +5591,7 @@
             uint64_t receive_data = p_dspin_in.data.read();
             // for data INVAL, wait for dcache to take the request
-            if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and (p_dspin_in.write.read()))
+            if ( (r_cc_receive_data_ins.read() == 0) and 
+                 not (r_cc_receive_dcache_req.read()) and 
+                 (p_dspin_in.write.read()) )
             {
                 // request dcache to handle the INVAL
@@ -5485,5 +5615,5 @@
             }
             // we should never get there
-            assert ( false && "CC_RECEIVE_INVAL_NLINE : incoherent handling of either r_cc_receive_data_ins or r_cc_receive_*cache_req\n");
+            assert ( false && "ERROR in CC_VCACHE : CC_RECEIVE_INVAL_NLINE\n");
         }
         ////////////////////////////
@@ -5518,5 +5648,8 @@
             // for data INVAL, wait for dcache to take the request and fifo to
             // be empty
-            if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and r_cc_receive_updt_fifo_be.empty() and (p_dspin_in.write.read()))
+            if ( (r_cc_receive_data_ins.read() == 0) and 
+                 not (r_cc_receive_dcache_req.read()) and 
+                 r_cc_receive_updt_fifo_be.empty() and 
+                 (p_dspin_in.write.read()) )
             {
                 r_cc_receive_dcache_nline  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
@@ -5529,5 +5662,8 @@
             // for ins INVAL, wait for icache to take the request and fifo to be
             // empty
-            if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and r_cc_receive_updt_fifo_be.empty() and (p_dspin_in.write.read()))
+            if ( (r_cc_receive_data_ins.read() == 1) and 
+                 not (r_cc_receive_icache_req.read()) and 
+                 r_cc_receive_updt_fifo_be.empty() and 
+                 (p_dspin_in.write.read()))
             {
                 r_cc_receive_icache_nline  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
@@ -5539,5 +5675,5 @@
             }
             // we should never get there
-            assert ( false && "CC_RECEIVE_UPDT_NLINE : incoherent handling of either r_cc_receive_data_ins or r_cc_receive_*cache_req or r_cc_receive_fifo\n");
+            assert ( false && "ERROR in CC_VCACHE : CC_RECEIVE_UPDT_NLINE \n");
             break;
         }
@@ -5550,17 +5686,14 @@
                 r_cc_receive_icache_req = true;
 
-            // sample data, be and eop
-            uint64_t receive_data = p_dspin_in.data.read();
             // wait for the fifo
             if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_in.write.read()))
             {
-                cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
+                uint64_t receive_data = p_dspin_in.data.read();
+                bool     receive_eop  = p_dspin_in.eop.read();
+                cc_receive_updt_fifo_be   = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
                 cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
-                // sample eop to test for state exit
-                bool flit_eop = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_EOP);
-                cc_receive_updt_fifo_eop = flit_eop;
+                cc_receive_updt_fifo_eop  = receive_eop;
                 cc_receive_updt_fifo_put  = true;
-                if(flit_eop)
-                    r_cc_receive_fsm = CC_RECEIVE_IDLE;
+                if ( receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE;
             }
             break;
@@ -5610,4 +5743,21 @@
     p_vci.cfixed = false;
 
+    if ( m_monitor_ok ) {
+        if ( p_vci.cmdack.read() == true and p_vci.cmdval == true) {
+            if (((p_vci.address.read()) >= m_monitor_base) and 
+                ((p_vci.address.read()) < m_monitor_base + m_monitor_length) ) {
+                std::cout << "CC_VCACHE Monitor " << name() << std::hex
+                          << " Access type = " << vci_cmd_type_str[p_vci.cmd.read()] 
+                          << " Pktid type = " << vci_pktid_type_str[p_vci.pktid.read()]
+                          << " : address = " << p_vci.address.read()
+                          << " / be = " << p_vci.be.read(); 
+                if ( p_vci.cmd.read() == vci_param::CMD_WRITE ) {
+                    std::cout << " / data = " << p_vci.wdata.read();
+                }
+                std::cout << std::dec << std::endl;
+            }
+        }
+    }
+
     switch ( r_vci_cmd_fsm.read() ) {
 
@@ -5738,5 +5888,5 @@
 
     
-    // Send coherence packets on DSPIN L2M 
+    // Send coherence packets on DSPIN P2M 
     // it depends on the CC_SEND FSM 
 
@@ -5754,7 +5904,7 @@
         {
             // initialize dspin send data
-            DspinDhccpParam::dspin_set(dspin_send_data,
-                                       0,
-                                       DspinDhccpParam::FROM_L1_EOP);
+//            DspinDhccpParam::dspin_set(dspin_send_data,
+//                                       0,
+//                                       DspinDhccpParam::FROM_L1_EOP);
             DspinDhccpParam::dspin_set(dspin_send_data,
                                        m_cc_global_id,
@@ -5775,5 +5925,5 @@
 
                 DspinDhccpParam::dspin_set(dspin_send_data,
-                                           r_dcache_cc_send_nline.read() & 0x300000000ULL,
+                                           (r_dcache_cc_send_nline.read() & 0x300000000ULL)>>32,
                                            DspinDhccpParam::CLEANUP_NLINE_MSB);
 
@@ -5797,5 +5947,5 @@
 
                 DspinDhccpParam::dspin_set(dspin_send_data,
-                                           r_icache_cc_send_nline.read() & 0x300000000ULL,
+                                           (r_icache_cc_send_nline.read() & 0x300000000ULL)>>32,
                                            DspinDhccpParam::CLEANUP_NLINE_MSB);
 
@@ -5811,4 +5961,5 @@
             p_dspin_out.data  = dspin_send_data;
             p_dspin_out.write = true;
+            p_dspin_out.eop   = false;
             break;
         }
@@ -5817,7 +5968,7 @@
         {
             // initialize dspin send data
-            DspinDhccpParam::dspin_set(dspin_send_data,
-                                       1,
-                                       DspinDhccpParam::FROM_L1_EOP);
+//            DspinDhccpParam::dspin_set(dspin_send_data,
+//                                       1,
+//                                       DspinDhccpParam::FROM_L1_EOP);
 
             if(r_cc_send_last_client.read() == 0) // dcache active request
@@ -5836,4 +5987,5 @@
             p_dspin_out.data  = dspin_send_data;
             p_dspin_out.write = true;
+            p_dspin_out.eop   = true;
             break;
         }
@@ -5842,7 +5994,7 @@
         {
             // initialize dspin send data
-            DspinDhccpParam::dspin_set(dspin_send_data,
-                                       1,
-                                       DspinDhccpParam::FROM_L1_EOP);
+//            DspinDhccpParam::dspin_set(dspin_send_data,
+//                                       1,
+//                                       DspinDhccpParam::FROM_L1_EOP);
             DspinDhccpParam::dspin_set(dspin_send_data,
                                        0,
@@ -5884,4 +6036,5 @@
             p_dspin_out.data  = dspin_send_data;
             p_dspin_out.write = true;
+            p_dspin_out.eop   = true;
 
             break;
@@ -5951,7 +6104,7 @@
                 r_cc_receive_updt_fifo_be.empty())
                 or
-                ((r_cc_receive_data_ins.read() == 1) and
+                (((r_cc_receive_data_ins.read() == 1) and
                 not r_cc_receive_icache_req.read()) and
-                r_cc_receive_updt_fifo_be.empty())
+                r_cc_receive_updt_fifo_be.empty()))
                 p_dspin_in.read = true;
             else
@@ -5987,4 +6140,17 @@
 } // end genMoore
 
+tmpl(void)::start_monitor(paddr_t base, paddr_t length)
+// This version of monitor print both Read and Write request
+{
+    m_monitor_ok        = true;
+    m_monitor_base      = base;
+    m_monitor_length    = length;
+}
+
+tmpl(void)::stop_monitor()
+{
+    m_monitor_ok        = false;
+}
+
 }}
 
