Ignore:
Timestamp:
Jul 19, 2013, 10:16:17 AM (11 years ago)
Author:
cfuguet
Message:

Merged

/trunk/modules/vci_mem_cache:449 with
/branches/v5/modules/vci_mem_cache:446.

This merge introduces into the branch the last modifications concerning
the VCI memory cache configuration interface

Location:
branches/v5/modules/vci_mem_cache
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • branches/v5/modules/vci_mem_cache

  • branches/v5/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp

    r445 r455  
    527527    r_cas_rdata                = new sc_signal<data_t>[2];
    528528
     529    // Allocation for debug
     530    m_debug_previous_data      = new sc_signal<data_t>[nwords];
     531    m_debug_data               = new sc_signal<data_t>[nwords];
    529532
    530533    SC_METHOD(transition);
     
    554557
    555558////////////////////////////////////////////////
    556 tmpl(void) ::check_monitor( const char  *buf,
    557                             addr_t      addr,
     559tmpl(void) ::check_monitor( addr_t      addr,
    558560                            data_t      data,
    559561                            bool        read )
     
    563565      (addr < m_monitor_base + m_monitor_length))
    564566  {
    565     if ( read ) std::cout << " Monitor MEMC Read  ";
    566     else        std::cout << " Monitor MEMC Write ";
    567     std::cout << buf
    568               << " / Address = " << std::hex << addr
     567    if ( read ) std::cout << " Monitor MEMC Read ";
     568    else        std::cout << " Monitor MEMC Write";
     569    std::cout << " / Address = " << std::hex << addr
    569570              << " / Data = " << data
    570571              << " at cycle " << std::dec << m_cpt_cycles << std::endl;
     
    573574
    574575/////////////////////////////////////////////////////
    575 tmpl(void) ::copies_monitor(addr_t addr)
     576tmpl(void) ::cache_monitor(addr_t addr)
    576577/////////////////////////////////////////////////////
    577578{
    578   DirectoryEntry entry = m_cache_directory.read_neutral(addr);
    579 
    580   if((entry.count != m_debug_previous_count) or
    581       (entry.valid != m_debug_previous_hit))
    582   {
    583     std::cout << "Monitor MEMC " << name()
    584               << " at cycle " << std::dec << m_cpt_cycles
    585               << " for address " << std::hex << addr
    586               << " / HIT = " << entry.valid
    587               << " / COUNT = " << std::dec << entry.count << std::endl;
    588   }
    589   m_debug_previous_count = entry.count;
    590   m_debug_previous_hit = entry.valid;
     579    size_t way = 0;
     580    size_t set = 0;
     581    DirectoryEntry entry = m_cache_directory.read_neutral(addr, &way, &set );
     582
     583    bool data_change = false;
     584
     585    if ( entry.valid )
     586    {
     587        m_cache_data.read_line( way, set, m_debug_data );
     588
     589        for ( size_t i = 0 ; i<m_words ; i++ )
     590        {
     591            if ( m_debug_previous_valid and
     592                 (m_debug_data[i].read() != m_debug_previous_data[i].read()) )
     593                 data_change = true;
     594            m_debug_previous_data[i] = m_debug_data[i].read();
     595        }
     596    }
     597   
     598    if ( (entry.valid != m_debug_previous_valid) or
     599         (entry.valid and (entry.count != m_debug_previous_count)) or
     600         (entry.valid and (entry.dirty != m_debug_previous_dirty)) or data_change )
     601    {
     602        std::cout << "Monitor MEMC " << name()
     603                  << " at cycle " << std::dec << m_cpt_cycles
     604                  << " for address " << std::hex << addr
     605                  << " / HIT = " << std::dec << entry.valid
     606                  << " / WAY = " << way
     607                  << " / COUNT = " << entry.count
     608                  << " / DIRTY = " << entry.dirty
     609                  << " / DATA_CHANGE = " << entry.count
     610                  << std::endl;
     611    }
     612    m_debug_previous_count = entry.count;
     613    m_debug_previous_valid = entry.valid;
     614    m_debug_previous_dirty = entry.dirty;
    591615}
    592616
     
    694718
    695719    m_debug                = false;
    696     m_debug_previous_hit   = false;
     720    m_debug_previous_valid = false;
     721    m_debug_previous_dirty = false;
    697722    m_debug_previous_count = 0;
    698723
     
    14401465  //
    14411466  // From the software point of view, a configuration request is a sequence
    1442   // of 6 atomic accesses:
     1467  // of 6 atomic accesses in an uncached segment:
    14431468  // - Read  MEMC_LOCK       : Get the lock
    14441469  // - Write MEMC_ADDR_LO    : Set the buffer address LSB
     
    15951620                                  nb_copies,
    15961621                                  index);
     1622
    15971623                  if ( wok )  // IVT success => inval DIR slot
    15981624                  {
     
    18371863      case READ_IDLE:  // waiting a read request
    18381864      {
    1839       if(m_cmd_read_addr_fifo.rok())
    1840       {
     1865        if(m_cmd_read_addr_fifo.rok())
     1866        {
    18411867
    18421868#if DEBUG_MEMC_READ
    1843 if(m_debug)
    1844 std::cout << "  <MEMC " << name() << " READ_IDLE> Read request"
    1845           << " : address = " << std::hex << m_cmd_read_addr_fifo.read()
    1846           << " / srcid = " << m_cmd_read_srcid_fifo.read()
    1847           << " / trdid = " << m_cmd_read_trdid_fifo.read()
    1848           << " / pktid = " << m_cmd_read_pktid_fifo.read()
    1849           << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl;
    1850 #endif
    1851         r_read_fsm = READ_DIR_REQ;
    1852       }
     1869          if(m_debug)
     1870            std::cout << "  <MEMC " << name() << " READ_IDLE> Read request"
     1871              << " : address = " << std::hex << m_cmd_read_addr_fifo.read()
     1872              << " / srcid = " << m_cmd_read_srcid_fifo.read()
     1873              << " / trdid = " << m_cmd_read_trdid_fifo.read()
     1874              << " / pktid = " << m_cmd_read_pktid_fifo.read()
     1875              << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl;
     1876#endif
     1877          r_read_fsm = READ_DIR_REQ;
     1878        }
    18531879      break;
    18541880    }
     
    18771903        DirectoryEntry entry =
    18781904          m_cache_directory.read(m_cmd_read_addr_fifo.read(), way);
    1879         if((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL)   // access the global table ONLY when we have an LL cmd
     1905        // access the global table ONLY when we have an LL cmd
     1906        if((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL)   
    18801907        {
    18811908          r_read_ll_key   = m_llsc_table.ll(m_cmd_read_addr_fifo.read());
     
    19391966
    19401967    //////////////////
    1941     case READ_DIR_HIT:
    1942     {
    1943       //  read data in cache & update the directory
    1944       //  we enter this state in 3 cases:
    1945       //  - the read request is uncachable
    1946       //  - the cache line is in counter mode
    1947       //  - the cache line is valid but not replcated
    1948 
     1968    case READ_DIR_HIT:    //  read data in cache & update the directory
     1969                          //  we enter this state in 3 cases:
     1970                          //  - the read request is uncachable
     1971                          //  - the cache line is in counter mode
     1972                          //  - the cache line is valid but not replicated
     1973
     1974    {
    19491975      if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ)
    19501976      {
     
    19651991        m_cache_data.read_line(way, set, r_read_data);
    19661992
     1993        if(m_monitor_ok) check_monitor( m_cmd_read_addr_fifo.read(), r_read_data[0], true);
     1994
    19671995        // update the cache directory
    19681996        DirectoryEntry entry;
     
    19732001        entry.lock    = r_read_lock.read();
    19742002        entry.ptr     = r_read_ptr.read();
     2003
    19752004        if(cached_read)   // Cached read => we must update the copies
    19762005        {
     
    19942023          }
    19952024        }
    1996         else  // Uncached read
     2025        else            // Uncached read
    19972026        {
    19982027          entry.owner.srcid     = r_read_copy.read();
     
    20052034
    20062035#if DEBUG_MEMC_READ
    2007 if(m_debug)
    2008 std::cout << "  <MEMC " << name() << " READ_DIR_HIT> Update directory entry:"
    2009           << " addr = " << std::hex << m_cmd_read_addr_fifo.read()
    2010           << " / set = " << std::dec << set
    2011           << " / way = " << way
    2012           << " / owner_id = " << std::hex << entry.owner.srcid
    2013           << " / owner_ins = " << std::dec << entry.owner.inst
    2014           << " / count = " << entry.count
    2015           << " / is_cnt = " << entry.is_cnt << std::endl;
    2016 #endif
    2017 
    2018           if(m_monitor_ok)
    2019           {
    2020             char buf[80];
    2021             snprintf(buf, 80, "READ_DIR_HIT srcid %d, ins %d",
    2022                      (int)m_cmd_read_srcid_fifo.read(),
    2023                      (int)((m_cmd_read_pktid_fifo.read()&0x2)!=0));
    2024             check_monitor(buf, m_cmd_read_addr_fifo.read(), r_read_data[0], true);
    2025           }
    2026 
     2036        if(m_debug)
     2037          std::cout << "  <MEMC " << name() << " READ_DIR_HIT> Update directory entry:"
     2038            << " addr = " << std::hex << m_cmd_read_addr_fifo.read()
     2039            << " / set = " << std::dec << set
     2040            << " / way = " << way
     2041            << " / owner_id = " << std::hex << entry.owner.srcid
     2042            << " / owner_ins = " << std::dec << entry.owner.inst
     2043            << " / count = " << entry.count
     2044            << " / is_cnt = " << entry.is_cnt << std::endl;
     2045#endif
    20272046
    20282047        m_cache_directory.write(set, way, entry);
     
    20312050      break;
    20322051    }
    2033 
    20342052    ///////////////////
    20352053    case READ_HEAP_REQ:    // Get the lock to the HEAP directory
     
    20622080
    20632081        m_cache_data.read_line(way, set, r_read_data);
     2082
     2083        if(m_monitor_ok) check_monitor( m_cmd_read_addr_fifo.read(), r_read_data[0], true);
    20642084
    20652085        // update the cache directory
     
    24292449
    24302450#if DEBUG_MEMC_WRITE
    2431         if(m_debug)
    2432         {
    2433           std::cout << "  <MEMC " << name() << " WRITE_IDLE> Write request "
    2434                     << " srcid = " << std::dec << m_cmd_write_srcid_fifo.read()
    2435                     << " / address = " << std::hex << m_cmd_write_addr_fifo.read()
    2436                     << " / data = " << m_cmd_write_data_fifo.read() << std::endl;
    2437         }
     2451if(m_debug)
     2452std::cout << "  <MEMC " << name() << " WRITE_IDLE> Write request "
     2453          << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read()
     2454          << " / address = " << std::hex << m_cmd_write_addr_fifo.read()
     2455          << " / data = " << m_cmd_write_data_fifo.read() << std::endl;
    24382456#endif
    24392457      }
     
    24482466
    24492467#if DEBUG_MEMC_WRITE
    2450         if(m_debug)
    2451         {
    2452           std::cout << "  <MEMC " << name()
    2453                     << " WRITE_NEXT> Write another word in local buffer"
    2454                     << std::endl;
    2455         }
     2468if(m_debug)
     2469std::cout << "  <MEMC " << name()
     2470          << " WRITE_NEXT> Write another word in local buffer"
     2471          << std::endl;
    24562472#endif
    24572473        m_cpt_write_cells++;
     
    25322548
    25332549#if DEBUG_MEMC_WRITE
    2534       if(m_debug)
    2535       {
    2536         std::cout
    2537             << "  <MEMC " << name() << " WRITE_DIR_REQ> Requesting DIR lock "
    2538             << std::endl;
    2539       }
     2550if(m_debug)
     2551std::cout << "  <MEMC " << name() << " WRITE_DIR_REQ> Requesting DIR lock "
     2552          << std::endl;
    25402553#endif
    25412554
     
    25442557
    25452558    ////////////////////
    2546     case WRITE_DIR_LOCK:
    2547       // access directory to check hit/miss
     2559    case WRITE_DIR_LOCK:     // access directory to check hit/miss
    25482560    {
    25492561      if(r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE)
     
    25822594
    25832595#if DEBUG_MEMC_WRITE
    2584         if(m_debug)
    2585         {
    2586           std::cout << "  <MEMC " << name() << " WRITE_DIR_LOCK> Check the directory: "
    2587                     << " address = " << std::hex << r_write_address.read()
    2588                     << " hit = " << std::dec << entry.valid
    2589                     << " count = " << entry.count
    2590                     << " is_cnt = " << entry.is_cnt << std::endl;
    2591           if((r_write_pktid.read() & 0x7) == TYPE_SC)
    2592             std::cout << "  <MEMC " << name() << " WRITE_DIR_LOCK> global_llsc_table SC access" << std::endl;
    2593           else
    2594             std::cout << "  <MEMC " << name() << " WRITE_DIR_LOCK> global_llsc_table SW access" << std::endl;
    2595         }
     2596if(m_debug)
     2597{
     2598std::cout << "  <MEMC " << name() << " WRITE_DIR_LOCK> Check the directory: "
     2599          << " address = " << std::hex << r_write_address.read()
     2600          << " / hit = " << std::dec << entry.valid
     2601          << " / count = " << entry.count
     2602          << " / is_cnt = " << entry.is_cnt ;
     2603if((r_write_pktid.read() & 0x7) == TYPE_SC)
     2604std::cout << " / SC access" << std::endl;
     2605else
     2606std::cout << " / SW access" << std::endl;
     2607}
    25962608#endif
    25972609      }
     
    26042616        exit(0);
    26052617      }
    2606 
    2607       break;
    2608     }
    2609 
     2618      break;
     2619    }
    26102620    ////////////////////
    26112621    case WRITE_DIR_READ:  // read the cache and complete the buffer when be!=0xF
     
    26322642
    26332643#if DEBUG_MEMC_WRITE
    2634       if(m_debug)
    2635       {
    2636         std::cout << "  <MEMC " << name() << " WRITE_DIR_READ> Read the cache to complete local buffer" << std::endl;
    2637       }
     2644if(m_debug)
     2645std::cout << "  <MEMC " << name() << " WRITE_DIR_READ>"
     2646          << " Read the cache to complete local buffer" << std::endl;
    26382647#endif
    26392648      break;
     
    26482657      entry.valid          = true;
    26492658      entry.dirty          = true;
    2650       entry.tag          = r_write_tag.read();
     2659      entry.tag            = r_write_tag.read();
    26512660      entry.is_cnt         = r_write_is_cnt.read();
    26522661      entry.lock           = r_write_lock.read();
     
    26752684      // (tests for sc requests)
    26762685      bool no_update = ( (r_write_count.read() == 0) or
    2677                          (owner and (r_write_count.read() ==1) and (r_write_pktid.read() != TYPE_SC)));
     2686                         (owner and (r_write_count.read() ==1) and
     2687                         (r_write_pktid.read() != TYPE_SC)));
    26782688
    26792689      // write data in the cache if no coherence transaction
     
    26872697          {
    26882698            addr_t address = (r_write_address.read() & ~(addr_t) 0x3F) | word<<2;
    2689             char buf[80];
    2690             snprintf(buf, 80, "WRITE_DIR_HIT srcid %d",
    2691                      (int)r_write_srcid.read());
    2692             check_monitor(buf, address, r_write_data[word].read(), false);
     2699            check_monitor( address, r_write_data[word].read(), false);
    26932700          }
    26942701        }
     
    27392746      break;
    27402747    }
    2741 
    27422748    ////////////////////
    27432749    case WRITE_UPT_LOCK:  // Try to register the update request in UPT
     
    27782784            {
    27792785              addr_t address = (r_write_address.read() & ~(addr_t) 0x3F) | word<<2;
    2780               char buf[80];
    2781               snprintf(buf, 80, "WRITE_UPT_LOCK srcid %d", (int)srcid);
    2782               check_monitor(buf, address, r_write_data[word].read(), false);
     2786              check_monitor( address, r_write_data[word].read(), false);
    27832787            }
    27842788          }
     
    38803884        {
    38813885          addr_t address = r_xram_rsp_trt_buf.nline<<6 | word<<2;
    3882           check_monitor("XRAM_RSP_DIR_UPDT", address, r_xram_rsp_trt_buf.wdata[word], false);
     3886          check_monitor( address, r_xram_rsp_trt_buf.wdata[word], false);
    38833887        }
    38843888      }
     
    52705274        {
    52715275          addr_t address = m_cmd_cas_addr_fifo.read();
    5272           char buf[80];
    5273           snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d",
    5274                    (int)m_cmd_cas_srcid_fifo.read());
    5275           check_monitor(buf, address, r_cas_wdata.read(), false);
     5276          check_monitor( address, r_cas_wdata.read(), false);
    52765277
    52775278          if(r_cas_cpt.read() == 4)
    5278             check_monitor(buf, address+4, m_cmd_cas_wdata_fifo.read(), false);
     5279            check_monitor( address+4, m_cmd_cas_wdata_fifo.read(), false);
    52795280        }
    52805281
     
    53355336          {
    53365337            addr_t address = m_cmd_cas_addr_fifo.read();
    5337             char buf[80];
    5338             snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d",
    5339                      (int)m_cmd_cas_srcid_fifo.read());
    5340             check_monitor(buf, address, r_cas_wdata.read(), false);
     5338            check_monitor( address, r_cas_wdata.read(), false);
    53415339
    53425340            if(r_cas_cpt.read() ==4)
    5343               check_monitor(buf, address+4, m_cmd_cas_wdata_fifo.read(), false);
     5341              check_monitor( address+4, m_cmd_cas_wdata_fifo.read(), false);
    53445342          }
    53455343        }
     
    55725570          {
    55735571            addr_t address = m_cmd_cas_addr_fifo.read();
    5574             char buf[80];
    5575             snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d",
    5576                      (int)m_cmd_cas_srcid_fifo.read());
    5577             check_monitor(buf, address, r_cas_wdata.read(), false);
     5572            check_monitor( address, r_cas_wdata.read(), false);
     5573
    55785574            if(r_cas_cpt.read() ==4)
    5579               check_monitor(buf, address+4, m_cmd_cas_wdata_fifo.read(), false);
     5575              check_monitor( address+4, m_cmd_cas_wdata_fifo.read(), false);
    55805576          }
    55815577          r_cas_upt_index = index;
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