Ignore:
Timestamp:
Jul 24, 2013, 8:47:40 AM (9 years ago)
Author:
cfuguet
Message:


Merging vci_mem_cache from branches/v5 to trunk [441-467]

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r441 | cfuguet | 2013-07-17 10:54:07 +0200 (Wed, 17 Jul 2013) | 14 lines

Modifications in branches/v5/vci_mem_cache:

  • Changing name of CC DSPIN ports: + p_dspin_in => p_dspin_p2m + p_dspin_out => p_dspin_m2p
  • Splitting the Update Table in two tables: + UPT (Update Table): Stores the MULTI-UPDATE transactions + IVT (Invalidate Table): Stores the MULTI/BROADCAST INVALIDATE

transactions

Each table has its own allocator FSM: r_alloc_upt and r_alloc_ivt

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r442 | cfuguet | 2013-07-17 12:13:51 +0200 (Wed, 17 Jul 2013) | 13 lines

Modifications in branches/v5/modules/vci_mem_cache:

  • Introducing third port for the CLACK network.
  • CLEANUP FSM is no more a CC_SEND FSM client.
  • CLEANUP FSM controls directly the p_dspin_clack port

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r445 | cfuguet | 2013-07-18 10:49:36 +0200 (Thu, 18 Jul 2013) | 7 lines

Bugfix in vci_mem_cache:

  • Adding missing "strings" for print_trace() function
  • Adding alloc_ivt fsm (Invalidate Table) in the

print_trace() function

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r455 | cfuguet | 2013-07-19 10:16:17 +0200 (Fri, 19 Jul 2013) | 8 lines

Merged

/trunk/modules/vci_mem_cache:449 with
/branches/v5/modules/vci_mem_cache:446.

This merge introduces into the branch the last modifications concerning
the VCI memory cache configuration interface


Merging vci_cc_vcache_wrapper from branches/v5 to trunk [444-467]

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r444 | cfuguet | 2013-07-17 14:46:46 +0200 (Wed, 17 Jul 2013) | 7 lines

Modifications in branches/v5/modules/vci_cc_vcache_wrapper:

  • Renaming FROM_MC DSPIN flits fields in M2P
  • Renaming FROM_L1 DSPIN flits fields in P2M
  • Renaming CLEANUP_ACK DSPIN flits fields in CLACK

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r446 | cfuguet | 2013-07-18 11:37:47 +0200 (Thu, 18 Jul 2013) | 13 lines

Modifications in vci_cc_vcache_wrapper:

  • Merging the states DCACHE/ICACHE_CC_BROADCAST and DCACHE/ICACHE_CC_INVAL. This is because, the BROADCAST INVALIDATE and the MULTICAST INVALIDATE are both acknowledged by a CLEANUP.
  • Adding third port for the clack coherence network.
  • Renaming the port dspin_in to dspin_m2p and the port dspin_out to dspin_p2m

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r454 | haoliu | 2013-07-19 10:15:13 +0200 (Fri, 19 Jul 2013) | 2 lines

modified CC_RECEIVE FSM and CC_CHECK FSM (icache and dcache) for new
version V5

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r461 | cfuguet | 2013-07-19 15:49:43 +0200 (Fri, 19 Jul 2013) | 9 lines

Bugfix in vci_cc_vcache_wrapper:

  • In the states DCACHE/ICACHE CC_UPDT the FSM returns to the state CC_CHECK only when the cc_send_req is occupied.

We must not return to the CC_CHECK state if not ROK of the
DATA FIFO because the counter word counter will be reset.

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r462 | cfuguet | 2013-07-19 16:26:26 +0200 (Fri, 19 Jul 2013) | 8 lines

Modification in vci_cc_vcache_wrapper:

  • Optimization in DCACHE/ICACHE CC_CHECK state. We can handle a CLACK and a CC request if the latter does a MISS match. This is because the CC request doing MISS match does not need to access the directory

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r463 | cfuguet | 2013-07-19 16:52:06 +0200 (Fri, 19 Jul 2013) | 12 lines

Modification in vci_cc_vcache_wrapper:

  • Optimization in DCACHE/ICACHE CC_CHECK state. If pending request to CC_SEND, we wait in the CC_CHECK state. Doing this, during the wait, we can handle incoming CLACK avoiding any deadlock situation.

The states CC_UPDT and CC_INVAL do not need to test anymore if
there is a pending request to CC_SEND.


Merging tsar_generic_xbar from branches/v5 to trunk [447-467]

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r447 | cfuguet | 2013-07-18 16:12:05 +0200 (Thu, 18 Jul 2013) | 8 lines

Adding tsar_generic_xbar platform in branches/v5/platforms:

  • This platform contains a third local crossbar interconnect for the CLACK network.
  • It works only in a monocluster topology

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r448 | cfuguet | 2013-07-18 17:51:18 +0200 (Thu, 18 Jul 2013) | 9 lines

Modification in branches/v5/platforms/tsar_generic_xbar:

  • Adding a DSPIN router to the platform to allow the inter-cluster communication for the CLACK commands.

With this modification, the tsar_generic_xbar platform can be used
for multi-cluster simulations

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r466 | cfuguet | 2013-07-23 17:01:49 +0200 (Tue, 23 Jul 2013) | 9 lines

Modifications in branches/v5 vci_mem_cache:

  • Replacing the third router CLACK by a third virtual channel in the new virtual_dspin_router supporting several virtual channels.

The third channel has been added in the COMMAND router.

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r467 | cfuguet | 2013-07-23 17:23:13 +0200 (Tue, 23 Jul 2013) | 5 lines

Modifications in branches/v5 tsar_generic_xbar:

  • Adding preprocessor conditional statements for ALMOS support


Merging dspin_dhccp_param from branches/v5 to trunk [377-467]

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r442 | cfuguet | 2013-07-17 12:13:51 +0200 (Wed, 17 Jul 2013) | 13 lines

Modifications in branches/v5/communication/dspin_dhccp_param:

  • Renaming FROM_MC fields in M2P
  • Renaming FROM_L1 fields in P2M
  • Renaming CLEANUP_ACK fields in CLACK
Location:
trunk/modules/vci_cc_vcache_wrapper
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • trunk/modules/vci_cc_vcache_wrapper

  • trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h

    r432 r468  
    8989        // handling coherence requests
    9090        ICACHE_CC_CHECK,
     91        ICACHE_CC_UPDT,
    9192        ICACHE_CC_INVAL,
    92         ICACHE_CC_UPDT,
    93         ICACHE_CC_BROADCAST,
    94         ICACHE_CC_SEND_WAIT,
    9593    };
    9694
     
    138136        // handling coherence requests
    139137        DCACHE_CC_CHECK,
     138        DCACHE_CC_UPDT,
    140139        DCACHE_CC_INVAL,
    141         DCACHE_CC_UPDT,
    142         DCACHE_CC_BROADCAST,
    143         DCACHE_CC_SEND_WAIT,
    144140        // handling TLB inval (after a coherence or XTN request)
    145141        DCACHE_INVAL_TLB_SCAN,
     
    173169    {
    174170        CC_RECEIVE_IDLE,
    175         CC_RECEIVE_CLACK,
    176171        CC_RECEIVE_BRDCAST_HEADER,
    177172        CC_RECEIVE_BRDCAST_NLINE,
    178         CC_RECEIVE_INVAL_HEADER,
    179         CC_RECEIVE_INVAL_NLINE,
    180         CC_RECEIVE_UPDT_HEADER,
    181         CC_RECEIVE_UPDT_NLINE,
    182         CC_RECEIVE_UPDT_DATA,
     173        CC_RECEIVE_INS_INVAL_HEADER,
     174        CC_RECEIVE_INS_INVAL_NLINE,
     175        CC_RECEIVE_INS_UPDT_HEADER,
     176        CC_RECEIVE_INS_UPDT_NLINE,
     177        CC_RECEIVE_INS_UPDT_DATA,
     178        CC_RECEIVE_DATA_INVAL_HEADER,
     179        CC_RECEIVE_DATA_INVAL_NLINE,
     180        CC_RECEIVE_DATA_UPDT_HEADER,
     181        CC_RECEIVE_DATA_UPDT_NLINE,
     182        CC_RECEIVE_DATA_UPDT_DATA,
    183183    };
    184184
     
    285285
    286286public:
    287     sc_in<bool>                                 p_clk;
    288     sc_in<bool>                                 p_resetn;
    289     sc_in<bool>                                 p_irq[iss_t::n_irq];
    290     soclib::caba::VciInitiator<vci_param>       p_vci;
    291     soclib::caba::DspinInput <dspin_in_width>   p_dspin_in;
    292     soclib::caba::DspinOutput<dspin_out_width>  p_dspin_out;
     287    sc_in<bool>                                p_clk;
     288    sc_in<bool>                                p_resetn;
     289    sc_in<bool>                                p_irq[iss_t::n_irq];
     290    soclib::caba::VciInitiator<vci_param>      p_vci;
     291    soclib::caba::DspinInput<dspin_in_width>   p_dspin_m2p;
     292    soclib::caba::DspinOutput<dspin_out_width> p_dspin_p2m;
     293    soclib::caba::DspinInput<dspin_in_width>   p_dspin_clack;
    293294
    294295private:
     
    371372    sc_signal<bool>         r_icache_cc_need_write;     // activate the cache for writing
    372373
     374    // coherence clack handling
     375    sc_signal<bool>         r_icache_clack_req;         // clack request
     376    sc_signal<size_t>       r_icache_clack_way;             // clack way
     377    sc_signal<size_t>       r_icache_clack_set;             // clack set
     378
    373379    // icache flush handling
    374380    sc_signal<size_t>       r_icache_flush_count;           // slot counter used for cache flush
     
    444450    sc_signal<bool>         r_dcache_cc_need_write;     // activate the cache for writing
    445451
     452    // coherence clack handling
     453    sc_signal<bool>         r_dcache_clack_req;         // clack request
     454    sc_signal<size_t>       r_dcache_clack_way;             // clack way
     455    sc_signal<size_t>       r_dcache_clack_set;             // clack set
     456
    446457    // dcache flush handling
    447458    sc_signal<size_t>       r_dcache_flush_count;           // slot counter used for cache flush
     
    537548    sc_signal<paddr_t>      r_cc_receive_dcache_nline;      // cache line physical address
    538549
     550    ///////////////////////////////////
     551    //  DSPIN CLACK INTERFACE REGISTER
     552    ///////////////////////////////////
     553    sc_signal<bool>         r_dspin_clack_req;
     554    sc_signal<uint64_t>     r_dspin_clack_flit;
     555   
    539556    //////////////////////////////////////////////////////////////////
    540557    // processor, write buffer, caches , TLBs
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