Changeset 468 for trunk/modules/vci_mem_cache/caba/source/include

Timestamp:

Jul 24, 2013, 8:47:40 AM (11 years ago)

Author:

cfuguet

Message:

Merging vci_mem_cache from branches/v5 to trunk [441-467]

=-----------------------------------------------------------------------
r441 | cfuguet | 2013-07-17 10:54:07 +0200 (Wed, 17 Jul 2013) | 14 lines

Modifications in branches/v5/vci_mem_cache:

• Changing name of CC DSPIN ports: + p_dspin_in => p_dspin_p2m + p_dspin_out => p_dspin_m2p

• Splitting the Update Table in two tables: + UPT (Update Table): Stores the MULTI-UPDATE transactions + IVT (Invalidate Table): Stores the MULTI/BROADCAST INVALIDATE

transactions

Each table has its own allocator FSM: r_alloc_upt and r_alloc_ivt

=-----------------------------------------------------------------------
r442 | cfuguet | 2013-07-17 12:13:51 +0200 (Wed, 17 Jul 2013) | 13 lines

Modifications in branches/v5/modules/vci_mem_cache:

• Introducing third port for the CLACK network.
• CLEANUP FSM is no more a CC_SEND FSM client.
• CLEANUP FSM controls directly the p_dspin_clack port

=-----------------------------------------------------------------------
r445 | cfuguet | 2013-07-18 10:49:36 +0200 (Thu, 18 Jul 2013) | 7 lines

Bugfix in vci_mem_cache:

• Adding missing "strings" for print_trace() function
• Adding alloc_ivt fsm (Invalidate Table) in the

print_trace() function

=-----------------------------------------------------------------------
r455 | cfuguet | 2013-07-19 10:16:17 +0200 (Fri, 19 Jul 2013) | 8 lines

Merged

/trunk/modules/vci_mem_cache:449 with
/branches/v5/modules/vci_mem_cache:446.

This merge introduces into the branch the last modifications concerning
the VCI memory cache configuration interface

Merging vci_cc_vcache_wrapper from branches/v5 to trunk [444-467]

=-----------------------------------------------------------------------
r444 | cfuguet | 2013-07-17 14:46:46 +0200 (Wed, 17 Jul 2013) | 7 lines

Modifications in branches/v5/modules/vci_cc_vcache_wrapper:

• Renaming FROM_MC DSPIN flits fields in M2P
• Renaming FROM_L1 DSPIN flits fields in P2M
• Renaming CLEANUP_ACK DSPIN flits fields in CLACK

=-----------------------------------------------------------------------
r446 | cfuguet | 2013-07-18 11:37:47 +0200 (Thu, 18 Jul 2013) | 13 lines

Modifications in vci_cc_vcache_wrapper:

• Merging the states DCACHE/ICACHE_CC_BROADCAST and DCACHE/ICACHE_CC_INVAL. This is because, the BROADCAST INVALIDATE and the MULTICAST INVALIDATE are both acknowledged by a CLEANUP.

• Adding third port for the clack coherence network.

• Renaming the port dspin_in to dspin_m2p and the port dspin_out to dspin_p2m

=-----------------------------------------------------------------------
r454 | haoliu | 2013-07-19 10:15:13 +0200 (Fri, 19 Jul 2013) | 2 lines

modified CC_RECEIVE FSM and CC_CHECK FSM (icache and dcache) for new
version V5

=-----------------------------------------------------------------------
r461 | cfuguet | 2013-07-19 15:49:43 +0200 (Fri, 19 Jul 2013) | 9 lines

Bugfix in vci_cc_vcache_wrapper:

• In the states DCACHE/ICACHE CC_UPDT the FSM returns to the state CC_CHECK only when the cc_send_req is occupied.

We must not return to the CC_CHECK state if not ROK of the
DATA FIFO because the counter word counter will be reset.

=-----------------------------------------------------------------------
r462 | cfuguet | 2013-07-19 16:26:26 +0200 (Fri, 19 Jul 2013) | 8 lines

Modification in vci_cc_vcache_wrapper:

• Optimization in DCACHE/ICACHE CC_CHECK state. We can handle a CLACK and a CC request if the latter does a MISS match. This is because the CC request doing MISS match does not need to access the directory

=-----------------------------------------------------------------------
r463 | cfuguet | 2013-07-19 16:52:06 +0200 (Fri, 19 Jul 2013) | 12 lines

Modification in vci_cc_vcache_wrapper:

• Optimization in DCACHE/ICACHE CC_CHECK state. If pending request to CC_SEND, we wait in the CC_CHECK state. Doing this, during the wait, we can handle incoming CLACK avoiding any deadlock situation.

The states CC_UPDT and CC_INVAL do not need to test anymore if
there is a pending request to CC_SEND.

Merging tsar_generic_xbar from branches/v5 to trunk [447-467]

=-----------------------------------------------------------------------
r447 | cfuguet | 2013-07-18 16:12:05 +0200 (Thu, 18 Jul 2013) | 8 lines

Adding tsar_generic_xbar platform in branches/v5/platforms:

• This platform contains a third local crossbar interconnect for the CLACK network.

• It works only in a monocluster topology

=-----------------------------------------------------------------------
r448 | cfuguet | 2013-07-18 17:51:18 +0200 (Thu, 18 Jul 2013) | 9 lines

Modification in branches/v5/platforms/tsar_generic_xbar:

• Adding a DSPIN router to the platform to allow the inter-cluster communication for the CLACK commands.

With this modification, the tsar_generic_xbar platform can be used
for multi-cluster simulations

=-----------------------------------------------------------------------
r466 | cfuguet | 2013-07-23 17:01:49 +0200 (Tue, 23 Jul 2013) | 9 lines

Modifications in branches/v5 vci_mem_cache:

• Replacing the third router CLACK by a third virtual channel in the new virtual_dspin_router supporting several virtual channels.

The third channel has been added in the COMMAND router.

=-----------------------------------------------------------------------
r467 | cfuguet | 2013-07-23 17:23:13 +0200 (Tue, 23 Jul 2013) | 5 lines

Modifications in branches/v5 tsar_generic_xbar:

• Adding preprocessor conditional statements for ALMOS support

Merging dspin_dhccp_param from branches/v5 to trunk [377-467]

=-----------------------------------------------------------------------
r442 | cfuguet | 2013-07-17 12:13:51 +0200 (Wed, 17 Jul 2013) | 13 lines

Modifications in branches/v5/communication/dspin_dhccp_param:

• Renaming FROM_MC fields in M2P
• Renaming FROM_L1 fields in P2M
• Renaming CLEANUP_ACK fields in CLACK

Location:

trunk/modules/vci_mem_cache

Files:

• . (modified) (1 prop)
• caba/source/include/vci_mem_cache.h (modified) (14 diffs)

trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h

@@ -54 +54 @@
 #define TRT_ENTRIES      4      // Number of entries in TRT
 #define UPT_ENTRIES      4      // Number of entries in UPT
+#define IVT_ENTRIES      4      // Number of entries in IVT
 #define HEAP_ENTRIES     1024   // Number of entries in HEAP
 
@@ -122 +123 @@
         CC_SEND_WRITE_IDLE,
         CC_SEND_CAS_IDLE,
-        CC_SEND_CLEANUP_IDLE,
         CC_SEND_CONFIG_INVAL_HEADER,
         CC_SEND_CONFIG_INVAL_NLINE,
         CC_SEND_CONFIG_BRDCAST_HEADER,
         CC_SEND_CONFIG_BRDCAST_NLINE,
-        CC_SEND_CLEANUP_ACK,
         CC_SEND_XRAM_RSP_BRDCAST_HEADER,
         CC_SEND_XRAM_RSP_BRDCAST_NLINE,
@@ -163 +162 @@
         CONFIG_DIR_REQ,
         CONFIG_DIR_ACCESS,
-        CONFIG_DIR_UPT_LOCK,
+        CONFIG_DIR_IVT_LOCK,
         CONFIG_BC_SEND,
         CONFIG_BC_WAIT,
@@ -211 +210 @@
         WRITE_MISS_XRAM_REQ,
         WRITE_BC_TRT_LOCK,
-        WRITE_BC_UPT_LOCK,
+        WRITE_BC_IVT_LOCK,
         WRITE_BC_DIR_INVAL,
         WRITE_BC_CC_SEND,
@@ -274 +273 @@
         CAS_UPT_NEXT,
         CAS_BC_TRT_LOCK,
-        CAS_BC_UPT_LOCK,
+        CAS_BC_IVT_LOCK,
         CAS_BC_DIR_INVAL,
         CAS_BC_CC_SEND,
@@ -299 +298 @@
         CLEANUP_HEAP_CLEAN,
         CLEANUP_HEAP_FREE,
-        CLEANUP_UPT_LOCK,
-        CLEANUP_UPT_DECREMENT,
-        CLEANUP_UPT_CLEAR,
+        CLEANUP_IVT_LOCK,
+        CLEANUP_IVT_DECREMENT,
+        CLEANUP_IVT_CLEAR,
         CLEANUP_WRITE_RSP,
         CLEANUP_CONFIG_ACK,
@@ -332 +331 @@
       enum alloc_upt_fsm_state_e
       {
-        ALLOC_UPT_CONFIG,
         ALLOC_UPT_WRITE,
-        ALLOC_UPT_XRAM_RSP,
-        ALLOC_UPT_MULTI_ACK,
-        ALLOC_UPT_CLEANUP,
-        ALLOC_UPT_CAS
+        ALLOC_UPT_CAS,
+        ALLOC_UPT_MULTI_ACK
+      };
+
+      /* States of the ALLOC_IVT fsm */
+      enum alloc_ivt_fsm_state_e
+      {
+        ALLOC_IVT_WRITE,
+        ALLOC_IVT_XRAM_RSP,
+        ALLOC_IVT_CLEANUP,
+        ALLOC_IVT_CAS,
+        ALLOC_IVT_CONFIG
       };
 
@@ -451 +457 @@
       soclib::caba::VciTarget<vci_param_int>      p_vci_tgt;
       soclib::caba::VciInitiator<vci_param_ext>   p_vci_ixr;
-      soclib::caba::DspinInput<dspin_in_width>    p_dspin_in;
-      soclib::caba::DspinOutput<dspin_out_width>  p_dspin_out;
+      soclib::caba::DspinInput<dspin_in_width>    p_dspin_p2m;
+      soclib::caba::DspinOutput<dspin_out_width>  p_dspin_m2p;
+      soclib::caba::DspinOutput<dspin_out_width>  p_dspin_clack;
 
       VciMemCache(
@@ -468 +475 @@
           const size_t                       trt_lines=TRT_ENTRIES, 
           const size_t                       upt_lines=UPT_ENTRIES,     
+          const size_t                       ivt_lines=IVT_ENTRIES,     
           const size_t                       debug_start_cycle=0,
           const bool                         debug_ok=false );
@@ -502 +510 @@
       TransactionTab                     m_trt;              // xram transaction table
       uint32_t                           m_upt_lines;
-      UpdateTab                          m_upt;              // pending update & invalidate
+      UpdateTab                          m_upt;              // pending update
+      UpdateTab                          m_ivt;              // pending invalidate
       CacheDirectory                     m_cache_directory;  // data cache directory
       CacheData                          m_cache_data;       // data array[set][way][word]
@@ -591 +600 @@
       sc_signal<size_t>   r_config_heap_next;      // current pointer to scan HEAP
 
-      sc_signal<size_t>   r_config_upt_index;  // UPT index
+      sc_signal<size_t>   r_config_ivt_index;      // IVT index
 
       // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache)
@@ -780 +789 @@
       sc_signal<size_t>   r_cleanup_to_tgt_rsp_pktid; // transaction pktid
 
-      // Buffer between CLEANUP fsm and CC_SEND fsm (acknowledge a cleanup command from L1)
-      sc_signal<bool>     r_cleanup_to_cc_send_req;       // valid request
-      sc_signal<size_t>   r_cleanup_to_cc_send_srcid;     // L1 srcid
-      sc_signal<size_t>   r_cleanup_to_cc_send_set_index; // L1 set index
-      sc_signal<size_t>   r_cleanup_to_cc_send_way_index; // L1 way index
-      sc_signal<bool>     r_cleanup_to_cc_send_inst;      // Instruction Cleanup Ack
-
       ///////////////////////////////////////////////////////
       // Registers controlled by CAS fsm
@@ -872 +874 @@
       sc_signal<size_t>   r_xram_rsp_victim_ptr;        // victim line pointer to the heap
       sc_signal<data_t> * r_xram_rsp_victim_data;       // victim line data
-      sc_signal<size_t>   r_xram_rsp_upt_index;         // UPT entry index
+      sc_signal<size_t>   r_xram_rsp_ivt_index;         // IVT entry index
       sc_signal<size_t>   r_xram_rsp_next_ptr;          // Next pointer to the heap
 
@@ -953 +955 @@
 
       ////////////////////////////////////////////////////
+      // Registers controlled by ALLOC_IVT fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int>      r_alloc_ivt_fsm;
+
+      ////////////////////////////////////////////////////
       // Registers controlled by ALLOC_HEAP fsm
       ////////////////////////////////////////////////////