Index: branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
===================================================================
--- trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 468)
+++ branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 477)
@@ -115,4 +115,5 @@
         DCACHE_XTN_IT_INVAL,
         DCACHE_XTN_DC_FLUSH,
+        DCACHE_XTN_DC_FLUSH_DATA,
         DCACHE_XTN_DC_FLUSH_GO,
         DCACHE_XTN_DC_INVAL_VA,
@@ -120,4 +121,5 @@
         DCACHE_XTN_DC_INVAL_END,
         DCACHE_XTN_DC_INVAL_GO,
+        DCACHE_XTN_DC_INVAL_DATA,
         DCACHE_XTN_DT_INVAL,
         //handling dirty bit update
@@ -127,4 +129,5 @@
         DCACHE_MISS_SELECT,
         DCACHE_MISS_CLEAN,
+        DCACHE_MISS_DATA,
         DCACHE_MISS_WAIT,
         DCACHE_MISS_DATA_UPDT,
@@ -138,4 +141,5 @@
         DCACHE_CC_UPDT,
         DCACHE_CC_INVAL,
+        DCACHE_CC_INVAL_DATA,
         // handling TLB inval (after a coherence or XTN request)
         DCACHE_INVAL_TLB_SCAN,
@@ -188,4 +192,5 @@
         CC_SEND_CLEANUP_1,
         CC_SEND_CLEANUP_2,
+        CC_SEND_CLEANUP_DATA_UPDT,
         CC_SEND_MULTI_ACK,
     };
@@ -283,4 +288,14 @@
         TYPE_INS_MISS     = 0x3,
     };
+
+    //////////////////MODIFIED////////////////
+    enum content_line_cache_status_e
+    {
+        LINE_CACHE_DATA_NOT_DIRTY,
+        LINE_CACHE_DATA_DIRTY,
+        LINE_CACHE_IN_TLB,
+        LINE_CACHE_CONTAINS_PTD,
+    };
+    //////////////////////////////////////////
 
 public:
@@ -390,5 +405,5 @@
     // communication between ICACHE FSM and CC_SEND FSM
     sc_signal<bool>         r_icache_cc_send_req;           // ICACHE cc_send request
-    sc_signal<cc_send_t>    r_icache_cc_send_type;          // ICACHE cc_send request type
+    sc_signal<int>          r_icache_cc_send_type;          // ICACHE cc_send request type
     sc_signal<paddr_t>      r_icache_cc_send_nline;         // ICACHE cc_send nline
     sc_signal<size_t>       r_icache_cc_send_way;           // ICACHE cc_send way
@@ -429,4 +444,10 @@
     sc_signal<uint32_t>     r_dcache_vci_sc_data;       // SC data (command)
 
+    //RWT: local cas
+    sc_signal<bool>         r_cas_islocal;
+    sc_signal<size_t>       r_cas_local_way;
+    sc_signal<size_t>       r_cas_local_set;
+    sc_signal<size_t>       r_cas_local_word;
+
     // register used for XTN inval
     sc_signal<size_t>       r_dcache_xtn_way;		    // selected way (from dcache)
@@ -447,6 +468,9 @@
     sc_signal<size_t>       r_dcache_cc_way;		    // selected way for cc update/inval
     sc_signal<size_t>       r_dcache_cc_set;		    // selected set for cc update/inval
+    sc_signal<int>          r_dcache_cc_state;          // state of selected cache slot
     sc_signal<size_t>       r_dcache_cc_word;		    // word counter for cc update
     sc_signal<bool>         r_dcache_cc_need_write;     // activate the cache for writing
+    sc_signal<paddr_t>      r_dcache_cc_inval_addr;     // address for a cleanup transaction
+    sc_signal<uint32_t>     r_dcache_cc_inval_data_cpt;  
 
     // coherence clack handling
@@ -483,13 +507,35 @@
     // communication between DCACHE FSM and CC_SEND FSM
     sc_signal<bool>         r_dcache_cc_send_req;           // DCACHE cc_send request
-    sc_signal<cc_send_t>    r_dcache_cc_send_type;          // DCACHE cc_send request type
+    sc_signal<int>          r_dcache_cc_send_type;          // DCACHE cc_send request type
     sc_signal<paddr_t>      r_dcache_cc_send_nline;         // DCACHE cc_send nline
     sc_signal<size_t>       r_dcache_cc_send_way;           // DCACHE cc_send way
     sc_signal<size_t>       r_dcache_cc_send_updt_tab_idx;  // DCACHE cc_send update table index
-
+    
+    // special registers for ODCCP/RWT
+    sc_signal<bool>         r_dcache_cc_cleanup_updt_data;          // Register for cleanup with data (wb updt)
+    sc_signal<bool>         r_dcache_cc_cleanup_line_ncc;          // Register for cleanup with data (wb updt)
+    sc_signal<bool>         r_dcache_miss_victim_no_coherence;      // Register for victim in no coherence mode
+    sc_signal<bool>         r_dcache_line_no_coherence;             // Register for line current in no coherence mode
+    sc_signal<bool>         r_dcache_dirty_save;             
+    sc_signal<uint32_t>     r_cc_send_cpt_word;
+    sc_signal<uint32_t>     r_dcache_miss_data_cpt;
+    sc_signal<paddr_t>      r_dcache_miss_data_addr;
+    sc_signal<uint32_t>     r_dcache_xtn_flush_data_cpt;
+    sc_signal<paddr_t>      r_dcache_xtn_flush_addr_data;
+    sc_signal<int>          r_dcache_xtn_state;
+    sc_signal<paddr_t>      r_dcache_xtn_data_addr;
+    sc_signal<uint32_t>     r_dcache_xtn_data_cpt;
     // dcache directory extension
-    bool                    *r_dcache_in_tlb;               // copy exist in dtlb or itlb
-    bool                    *r_dcache_contains_ptd;         // cache line contains a PTD
-
+    ///////////////////////////MODIFIED///////////////////////////////////////////////////
+    //bool                    *r_dcache_in_tlb;           // copy exist in dtlb or itlb
+    //bool                    *r_dcache_contains_ptd;     // cache line contains a PTD
+    int                     *r_dcache_content_state;    // content state of one cache line
+    int                     *r_dcache_dirty_word;    // content state of one cache line
+    //////////////////////////////////////////////////////////////////////////////////////
+
+    //RWT
+    sc_signal<bool>         r_dcache_read_state;
+   
+     ///////////////////////////////////
     // Physical address extension for data access
     sc_signal<uint32_t>     r_dcache_paddr_ext;             // CP2 register (if vci_address > 32)
@@ -513,4 +559,10 @@
     GenericFifo<uint32_t>   r_vci_rsp_fifo_icache;	        // response FIFO to ICACHE FSM
     GenericFifo<uint32_t>   r_vci_rsp_fifo_dcache;	        // response FIFO to DCACHE FSM
+    
+
+    //RWT
+    GenericFifo<bool>       r_vci_rsp_fifo_rpktid;
+
+    GenericFifo<uint32_t>   r_cc_send_data_fifo;   
 
     ///////////////////////////////////
@@ -534,5 +586,5 @@
     // communication between CC_RECEIVE FSM and ICACHE FSM
     sc_signal<bool>         r_cc_receive_icache_req;        // cc_receive to icache request
-    sc_signal<cc_receive_t> r_cc_receive_icache_type;       // cc_receive type of request
+    sc_signal<int>          r_cc_receive_icache_type;       // cc_receive type of request
     sc_signal<size_t>       r_cc_receive_icache_way;        // cc_receive to icache way
     sc_signal<size_t>       r_cc_receive_icache_set;        // cc_receive to icache set
@@ -542,5 +594,5 @@
     // communication between CC_RECEIVE FSM and DCACHE FSM
     sc_signal<bool>         r_cc_receive_dcache_req;        // cc_receive to dcache request
-    sc_signal<cc_receive_t> r_cc_receive_dcache_type;       // cc_receive type of request
+    sc_signal<int>          r_cc_receive_dcache_type;       // cc_receive type of request
     sc_signal<size_t>       r_cc_receive_dcache_way;        // cc_receive to dcache way
     sc_signal<size_t>       r_cc_receive_dcache_set;        // cc_receive to dcache set
@@ -593,4 +645,7 @@
     uint32_t m_cpt_data_read;               // total number of read data
     uint32_t m_cpt_data_write;              // total number of write data
+    uint32_t m_cpt_data_write_back;
+    uint32_t m_cpt_data_cleanup;
+    uint32_t m_cpt_data_sc;
     uint32_t m_cpt_data_miss;               // number of read miss
     uint32_t m_cpt_ins_miss;                // number of instruction miss
@@ -608,4 +663,6 @@
     uint32_t m_cpt_dmiss_transaction;       // number of VCI data miss transactions
     uint32_t m_cpt_unc_transaction;         // number of VCI uncached read transactions
+    uint32_t m_cpt_dunc_transaction;         // number of VCI uncached read transactions
+    uint32_t m_cpt_ll_transaction;         // number of VCI uncached read transactions
     uint32_t m_cpt_write_transaction;       // number of VCI write transactions
     uint32_t m_cpt_icache_unc_transaction;
@@ -673,4 +730,6 @@
     uint32_t m_cpt_cc_cleanup_ins;              // number of coherence cleanup packets
     uint32_t m_cpt_cc_cleanup_data;             // number of coherence cleanup packets
+    uint32_t m_cpt_cleanup_data_not_dirty;
+    uint32_t m_cpt_cleanup_data_dirty_word;
 
     uint32_t m_cpt_icleanup_transaction;        // number of instruction cleanup transactions
