Index: branches/RWT/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h
===================================================================
--- trunk/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h	(revision 468)
+++ branches/RWT/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h	(revision 477)
@@ -96,4 +96,5 @@
 
     bool    valid;                  // entry valid
+    bool    cache_coherent;         // WB or WT policy
     bool    is_cnt;                 // directory entry is in counter mode
     bool    dirty;                  // entry dirty
@@ -107,4 +108,5 @@
     {
       valid         = false;
+      cache_coherent= false;
       is_cnt        = false;
       dirty         = false;
@@ -123,4 +125,5 @@
     {
       valid         = source.valid;
+      cache_coherent= source.cache_coherent;
       is_cnt        = source.is_cnt;
       dirty         = source.dirty;
@@ -138,4 +141,5 @@
     {
       valid     = false;
+      cache_coherent = false;
       is_cnt    = false;
       dirty     = false;
@@ -150,4 +154,5 @@
     {
       valid	    = source.valid;
+      cache_coherent = source.cache_coherent;
       is_cnt    = source.is_cnt;
       dirty	    = source.dirty;
@@ -165,4 +170,5 @@
     {
       std::cout << "Valid = " << valid 
+                << " ; COHERENCE = " << cache_coherent
                 << " ; IS COUNT = " << is_cnt 
                 << " ; Dirty = " << dirty 
Index: branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
===================================================================
--- trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h	(revision 468)
+++ branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h	(revision 477)
@@ -131,4 +131,8 @@
         CC_SEND_XRAM_RSP_INVAL_HEADER,
         CC_SEND_XRAM_RSP_INVAL_NLINE,
+        CC_SEND_READ_NCC_INVAL_HEADER,
+        CC_SEND_READ_NCC_INVAL_NLINE,
+        CC_SEND_WRITE_NCC_INVAL_HEADER,
+        CC_SEND_WRITE_NCC_INVAL_NLINE,
         CC_SEND_WRITE_BRDCAST_HEADER,
         CC_SEND_WRITE_BRDCAST_NLINE,
@@ -178,4 +182,6 @@
         READ_DIR_REQ,
         READ_DIR_LOCK,
+        READ_IVT_LOCK,
+        READ_WAIT,
         READ_DIR_HIT,
         READ_HEAP_REQ,
@@ -197,4 +203,5 @@
         WRITE_DIR_REQ,
         WRITE_DIR_LOCK,
+        WRITE_IVT_LOCK_HIT_WB,
         WRITE_DIR_READ,
         WRITE_DIR_HIT,
@@ -205,4 +212,5 @@
         WRITE_UPT_DEC,
         WRITE_RSP,
+        WRITE_MISS_IVT_LOCK,
         WRITE_MISS_TRT_LOCK,
         WRITE_MISS_TRT_DATA,
@@ -253,8 +261,10 @@
         IXR_CMD_CAS_IDLE,
         IXR_CMD_XRAM_IDLE,
+        IXR_CMD_CLEANUP_IDLE,
         IXR_CMD_READ,
         IXR_CMD_WRITE,
         IXR_CMD_CAS,
-        IXR_CMD_XRAM
+        IXR_CMD_XRAM,
+        IXR_CMD_CLEANUP_DATA
       };
 
@@ -290,7 +300,11 @@
         CLEANUP_IDLE,
         CLEANUP_GET_NLINE,
+        CLEANUP_GET_DATA,
         CLEANUP_DIR_REQ,
         CLEANUP_DIR_LOCK,
         CLEANUP_DIR_WRITE,
+        CLEANUP_IVT_LOCK_DATA,
+        CLEANUP_IVT_CLEAR_DATA,
+        CLEANUP_READ_RSP,
         CLEANUP_HEAP_REQ,
         CLEANUP_HEAP_LOCK,
@@ -302,4 +316,6 @@
         CLEANUP_IVT_CLEAR,
         CLEANUP_WRITE_RSP,
+        CLEANUP_IXR_REQ,
+        CLEANUP_WAIT,
         CLEANUP_CONFIG_ACK,
         CLEANUP_SEND_CLACK
@@ -325,5 +341,6 @@
         ALLOC_TRT_CAS,
         ALLOC_TRT_XRAM_RSP,
-        ALLOC_TRT_IXR_RSP
+        ALLOC_TRT_IXR_RSP,
+        ALLOC_TRT_CLEANUP
       };
 
@@ -340,4 +357,5 @@
       {
         ALLOC_IVT_WRITE,
+        ALLOC_IVT_READ,
         ALLOC_IVT_XRAM_RSP,
         ALLOC_IVT_CLEANUP,
@@ -434,4 +452,98 @@
       uint32_t     m_cpt_sc;            // Number of SC transactions
       uint32_t     m_cpt_cas;           // Number of CAS transactions
+      
+      uint32_t     m_cpt_read_fsm_dir_lock;        // wait DIR LOCK
+      uint32_t     m_cpt_read_fsm_n_dir_lock;      // NB DIR LOCK
+      uint32_t     m_cpt_write_fsm_dir_lock;       // wait DIR LOCK
+      uint32_t     m_cpt_write_fsm_n_dir_lock;     // NB DIR LOCK
+      uint32_t     m_cpt_xram_rsp_fsm_dir_lock;    // wait DIR LOCK
+      uint32_t     m_cpt_xram_rsp_fsm_n_dir_lock;  // NB DIR LOCK
+      uint32_t     m_cpt_cas_fsm_dir_lock;         // wait DIR LOCK
+      uint32_t     m_cpt_cas_fsm_n_dir_lock;       // NB DIR LOCK
+      uint32_t     m_cpt_cleanup_fsm_dir_lock;     // wait DIR LOCK
+      uint32_t     m_cpt_cleanup_fsm_n_dir_lock;   // NB DIR LOCK
+      
+      uint32_t     m_cpt_dir_unused;            // NB cycles DIR LOCK unused
+      uint32_t     m_cpt_read_fsm_dir_used;     // NB cycles DIR LOCK used
+      uint32_t     m_cpt_write_fsm_dir_used;    // NB cycles DIR LOCK used
+      uint32_t     m_cpt_cas_fsm_dir_used;      // NB cycles DIR LOCK used
+      uint32_t     m_cpt_xram_rsp_fsm_dir_used; // NB cycles DIR LOCK used
+      uint32_t     m_cpt_cleanup_fsm_dir_used;  // NB cycles DIR LOCK used
+
+      uint32_t     m_cpt_read_fsm_trt_lock;      // wait TRT LOCK
+      uint32_t     m_cpt_write_fsm_trt_lock;     // wait TRT LOCK
+      uint32_t     m_cpt_cas_fsm_trt_lock;       // wait TRT LOCK
+      uint32_t     m_cpt_xram_rsp_fsm_trt_lock;  // wait TRT LOCK
+      uint32_t     m_cpt_ixr_fsm_trt_lock;       // wait TRT LOCK
+      
+      uint32_t     m_cpt_read_fsm_n_trt_lock;      // NB TRT LOCK
+      uint32_t     m_cpt_write_fsm_n_trt_lock;     // NB TRT LOCK
+      uint32_t     m_cpt_cas_fsm_n_trt_lock;       // NB TRT LOCK
+      uint32_t     m_cpt_xram_rsp_fsm_n_trt_lock;  // NB TRT LOCK
+      uint32_t     m_cpt_ixr_fsm_n_trt_lock;       // NB TRT LOCK
+
+      uint32_t     m_cpt_read_fsm_trt_used;      // NB cycles TRT LOCK used
+      uint32_t     m_cpt_write_fsm_trt_used;     // NB cycles TRT LOCK used
+      uint32_t     m_cpt_cas_fsm_trt_used;       // NB cycles TRT LOCK used
+      uint32_t     m_cpt_xram_rsp_fsm_trt_used;  // NB cycles TRT LOCK used
+      uint32_t     m_cpt_ixr_fsm_trt_used;       // NB cycles TRT LOCK used
+      
+      uint32_t     m_cpt_trt_unused;            // NB cycles TRT LOCK unused
+
+      uint32_t     m_cpt_write_fsm_upt_lock;     // wait UPT LOCK
+      uint32_t     m_cpt_xram_rsp_fsm_upt_lock;  // wait UPT LOCK
+      uint32_t     m_cpt_multi_ack_fsm_upt_lock; // wait UPT LOCK
+      uint32_t     m_cpt_cleanup_fsm_ivt_lock;   // wait UPT LOCK
+      uint32_t     m_cpt_cas_fsm_upt_lock;       // wait UPT LOCK
+      
+      uint32_t     m_cpt_write_fsm_n_upt_lock;     // NB UPT LOCK
+      uint32_t     m_cpt_xram_rsp_fsm_n_upt_lock;  // NB UPT LOCK
+      uint32_t     m_cpt_multi_ack_fsm_n_upt_lock; // NB UPT LOCK
+      uint32_t     m_cpt_cleanup_fsm_n_upt_lock;   // NB UPT LOCK
+      uint32_t     m_cpt_cas_fsm_n_upt_lock;       // NB UPT LOCK
+      
+      uint32_t     m_cpt_write_fsm_upt_used;     // NB cycles UPT LOCK used
+      uint32_t     m_cpt_xram_rsp_fsm_upt_used;  // NB cycles UPT LOCK used
+      uint32_t     m_cpt_multi_ack_fsm_upt_used; // NB cycles UPT LOCK used
+      uint32_t     m_cpt_cleanup_fsm_ivt_used;   // NB cycles UPT LOCK used
+      uint32_t     m_cpt_cas_fsm_upt_used;       // NB cycles UPT LOCK used
+      
+      uint32_t     m_cpt_ivt_unused;            // NB cycles UPT LOCK unused
+      uint32_t     m_cpt_upt_unused;            // NB cycles UPT LOCK unused
+
+      uint32_t     m_cpt_read_fsm_heap_lock;     // wait HEAP LOCK
+      uint32_t     m_cpt_write_fsm_heap_lock;    // wait HEAP LOCK
+      uint32_t     m_cpt_cas_fsm_heap_lock;      // wait HEAP LOCK
+      uint32_t     m_cpt_cleanup_fsm_heap_lock;  // wait HEAP LOCK
+      uint32_t     m_cpt_xram_rsp_fsm_heap_lock; // wait HEAP LOCK
+      
+      uint32_t     m_cpt_read_fsm_n_heap_lock;     // NB HEAP LOCK
+      uint32_t     m_cpt_write_fsm_n_heap_lock;    // NB HEAP LOCK
+      uint32_t     m_cpt_cas_fsm_n_heap_lock;      // NB HEAP LOCK
+      uint32_t     m_cpt_cleanup_fsm_n_heap_lock;  // NB HEAP LOCK
+      uint32_t     m_cpt_xram_rsp_fsm_n_heap_lock; // NB HEAP LOCK
+      
+      uint32_t     m_cpt_read_fsm_heap_used;     // NB cycles HEAP LOCK used
+      uint32_t     m_cpt_write_fsm_heap_used;    // NB cycles HEAP LOCK used
+      uint32_t     m_cpt_cas_fsm_heap_used;      // NB cycles HEAP LOCK used
+      uint32_t     m_cpt_cleanup_fsm_heap_used;  // NB cycles HEAP LOCK used
+      uint32_t     m_cpt_xram_rsp_fsm_heap_used; // NB cycles HEAP LOCK used
+      
+      uint32_t     m_cpt_heap_unused;            // NB cycles HEAP LOCK unused
+
+      //RWT
+      uint32_t     m_cpt_cleanup_data;   
+      uint32_t     m_cpt_ncc_to_cc_read;         // NB change from NCC to CC caused by a READ
+      uint32_t     m_cpt_ncc_to_cc_write;        // NB change from NCC to CC caused by a WRITE
+      uint32_t     m_cpt_ncc_to_cc;              // NB change from NCC to CC
+
+      uint32_t     m_cpt_read_data_unc;
+      uint32_t     m_cpt_read_data_miss_CC;
+      uint32_t     m_cpt_read_ins_unc;
+      uint32_t     m_cpt_read_ins_miss;
+      uint32_t     m_cpt_read_ll_CC;
+      uint32_t     m_cpt_read_data_miss_NCC;
+      uint32_t     m_cpt_read_ll_NCC;
+      uint32_t     m_cpt_read_WTF;
 
       uint32_t     m_cpt_cleanup_cost;  // Number of (flits * distance) for CLEANUPs
@@ -481,4 +593,5 @@
       ~VciMemCache();
 
+      void clear_stats();
       void print_stats();
       void print_trace();
@@ -657,4 +770,25 @@
       sc_signal<addr_t>   r_read_to_tgt_rsp_ll_key; // LL key from the llsc_global_table
 
+      //RWT: Buffer between READ fsm and CC_SEND fsm (send inval)
+      sc_signal<bool>     r_read_to_cc_send_req;
+      sc_signal<size_t>   r_read_to_cc_send_dest;
+      sc_signal<addr_t>   r_read_to_cc_send_nline;
+      sc_signal<bool>     r_read_to_cc_send_inst;
+
+      //RWT: Buffer between READ fsm and CLEANUP fsm (wait for the data coming from L1 cache) 
+      sc_signal<bool>     r_read_to_cleanup_req;    // valid request
+      sc_signal<addr_t>   r_read_to_cleanup_nline;  // cache line index
+      sc_signal<size_t>   r_read_to_cleanup_srcid;
+      sc_signal<size_t>   r_read_to_cleanup_length;
+      sc_signal<size_t>   r_read_to_cleanup_first_word;
+      sc_signal<bool>     r_read_to_cleanup_cached_read;    
+      sc_signal<bool>     r_read_to_cleanup_is_ll;
+      sc_signal<addr_t>   r_read_to_cleanup_addr;
+      sc_signal<addr_t>   r_read_to_cleanup_ll_key;
+
+      //RWT:
+      sc_signal<bool>     r_read_coherent;          // State of the cache slot after transaction
+      sc_signal<bool>     r_read_ll_done;
+
       ///////////////////////////////////////////////////////////////
       // Registers controlled by the WRITE fsm
@@ -721,4 +855,16 @@
       sc_signal<size_t>   r_write_to_multi_ack_upt_index; // index in update table
 
+      // RWT: Buffer between WRITE fsm and CLEANUP fsm (change slot state)
+      sc_signal<bool>     r_write_to_cleanup_req;         // valid request
+      sc_signal<addr_t>   r_write_to_cleanup_nline;       // cache line index
+
+      // RWT
+      sc_signal<bool>     r_write_coherent;               // cache slot state after transaction
+
+      //Buffer between WRITE fsm and CC_SEND fsm (INVAL for RWT)
+      sc_signal<bool>     r_write_to_cc_send_req;
+      sc_signal<size_t>   r_write_to_cc_send_dest;
+
+
       /////////////////////////////////////////////////////////
       // Registers controlled by MULTI_ACK fsm
@@ -788,4 +934,15 @@
       sc_signal<size_t>   r_cleanup_to_tgt_rsp_trdid; // transaction trdid
       sc_signal<size_t>   r_cleanup_to_tgt_rsp_pktid; // transaction pktid
+      sc_signal<addr_t>     r_cleanup_to_tgt_rsp_ll_key;
+
+      //RWT
+      sc_signal<size_t>   r_cleanup_read_srcid;
+      sc_signal<size_t>   r_cleanup_read_trdid;
+      sc_signal<size_t>   r_cleanup_read_pktid;
+      sc_signal<bool>     r_cleanup_read_need_rsp;
+      sc_signal<bool>     r_cleanup_to_tgt_rsp_type;
+      sc_signal<data_t> * r_cleanup_to_tgt_rsp_data;
+      sc_signal<size_t>   r_cleanup_to_tgt_rsp_length;
+      sc_signal<size_t>   r_cleanup_to_tgt_rsp_first_word;
 
       ///////////////////////////////////////////////////////
@@ -813,4 +970,6 @@
       sc_signal<data_t> * r_cas_data;       // cache line data
 
+      sc_signal<bool>     r_cas_coherent;
+
       // Buffer between CAS fsm and IXR_CMD fsm (XRAM write)
       sc_signal<bool>     r_cas_to_ixr_cmd_req;   // valid request
@@ -906,4 +1065,7 @@
       sc_signal<size_t>   r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table
 
+      //RWT
+      sc_signal<bool>     r_xram_rsp_victim_coherent;      // victim's cache slot state
+      sc_signal<bool>     r_xram_rsp_coherent;             // coherence of the read
       ////////////////////////////////////////////////////
       // Registers controlled by the IXR_CMD fsm
@@ -966,4 +1128,28 @@
       sc_signal<int>      r_alloc_heap_fsm;
       sc_signal<unsigned> r_alloc_heap_reset_cpt;
+
+
+      ////////////////////////////////////////////////////
+      // REGISTERS FOR ODCCP
+      ////////////////////////////////////////////////////
+
+      sc_signal<uint32_t>  r_cleanup_data_index;
+      sc_signal<uint32_t>  r_cleanup_trdid;
+      sc_signal<uint32_t>  r_cleanup_pktid;
+      sc_signal<bool>      r_cleanup_coherent;
+      sc_signal<data_t>    *r_cleanup_data;
+      sc_signal<data_t>    *r_cleanup_old_data;
+      sc_signal<bool>      r_cleanup_contains_data;
+      
+      sc_signal<bool>      r_cleanup_ncc;
+      sc_signal<bool>      r_cleanup_to_ixr_cmd_ncc_l1_dirty;
+      sc_signal<bool>      r_xram_rsp_to_ixr_cmd_inval_ncc_pending;
+      
+      sc_signal<bool>      r_cleanup_to_ixr_cmd_req;
+      sc_signal<data_t>    *r_cleanup_to_ixr_cmd_data;
+      sc_signal<uint32_t>  r_cleanup_to_ixr_cmd_srcid;
+      sc_signal<uint32_t>  r_cleanup_to_ixr_cmd_trdid;
+      sc_signal<uint32_t>  r_cleanup_to_ixr_cmd_pktid;
+      sc_signal<addr_t>    r_cleanup_to_ixr_cmd_nline;
     }; // end class VciMemCache
 
Index: branches/RWT/modules/vci_mem_cache/caba/source/include/xram_transaction.h
===================================================================
--- trunk/modules/vci_mem_cache/caba/source/include/xram_transaction.h	(revision 468)
+++ branches/RWT/modules/vci_mem_cache/caba/source/include/xram_transaction.h	(revision 477)
@@ -294,4 +294,22 @@
     }
 
+    ///////////////////////////////////////////////////////////////////////
+    // The hit_write() function looks if an XRAM write transaction exists 
+    // for a given line.
+    // Arguments :
+    // - index : (return argument) the index of the hit entry, if there is
+    // - nline : the index (zy) of the requested line
+    // The function returns true if a write request has already been sent
+    ///////////////////////////////////////////////////////////////////////
+    bool hit_write(const addr_t nline, size_t* index)
+    {
+        for(size_t i=0; i<size_tab; i++){
+            if(tab[i].valid && (nline==tab[i].nline) && !(tab[i].xram_read)) {
+                *index = i;
+                return true;	
+            }
+        }
+        return false;
+    }
     /////////////////////////////////////////////////////////////////////
     // The write_data_mask() function writes a vector of data (a line).
