Index: trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp
===================================================================
--- trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp	(revision 37)
+++ trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp	(revision 48)
@@ -367,28 +367,39 @@
     float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
     std::cout << name() << std::endl
-    	      << "- CPI                    = " << (float)m_cpt_total_cycles/run_cycles << std::endl 
-    	      << "- READ RATE              = " << (float)m_cpt_read/run_cycles << std::endl 
-    	      << "- WRITE RATE             = " << (float)m_cpt_write/run_cycles << std::endl
-    	      << "- UNCACHED READ RATE     = " << (float)m_cpt_unc_read/m_cpt_read << std::endl 
-    	      << "- CACHED WRITE RATE      = " << (float)m_cpt_write_cached/m_cpt_write << std::endl 
-    	      << "- IMISS_RATE             = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl    
-    	      << "- DMISS RATE             = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl 
-    	      << "- INS MISS COST          = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
-    	      << "- IMISS TRANSACTION      = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
-    	      << "- DMISS COST             = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
-    	      << "- DMISS TRANSACTION      = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
-    	      << "- UNC COST               = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
-    	      << "- UNC TRANSACTION        = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
-    	      << "- WRITE COST             = " << (float)m_cost_write_frz/m_cpt_write << std::endl
-    	      << "- WRITE TRANSACTION      = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
-    	      << "- WRITE LENGTH           = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
-    	      << "- INS TLB MISS RATE      = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
-    	      << "- DATA TLB MISS RATE     = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
-    	      << "- ITLB MISS TRANSACTION  = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
-    	      << "- ITLB WRITE TRANSACTION = " << (float)m_cost_itlb_write_transaction/m_cpt_itlb_write_transaction << std::endl
-    	      << "- ITLB MISS COST         = " << (float)m_cost_ins_tlb_miss_frz/(m_cpt_ins_tlb_miss+m_cpt_ins_tlb_write_et) << std::endl
-    	      << "- DTLB MISS TRANSACTION  = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl
-    	      << "- DTLB WRITE TRANSACTION = " << (float)m_cost_dtlb_write_transaction/m_cpt_dtlb_write_transaction << std::endl
-    	      << "- DTLB MISS COST         = " << (float)m_cost_data_tlb_miss_frz/(m_cpt_data_tlb_miss+m_cpt_data_tlb_write_et+m_cpt_data_tlb_write_dirty) << std::endl;
+        << "- CPI                    = " << (float)m_cpt_total_cycles/run_cycles << std::endl 
+        << "- READ RATE              = " << (float)m_cpt_read/run_cycles << std::endl 
+        << "- WRITE RATE             = " << (float)m_cpt_write/run_cycles << std::endl
+        << "- IMISS_RATE             = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
+        << "- DMISS RATE             = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl  
+        << "- INS MISS COST          = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl     
+        << "- DATA MISS COST         = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl 
+        << "- WRITE COST             = " << (float)m_cost_write_frz/m_cpt_write << std::endl        
+        << "- UNC COST               = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
+        << "- UNCACHED READ RATE     = " << (float)m_cpt_unc_read/m_cpt_read << std::endl 
+        << "- CACHED WRITE RATE      = " << (float)m_cpt_write_cached/m_cpt_write << std::endl 
+        << "- INS TLB MISS RATE      = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
+        << "- DATA TLB MISS RATE     = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
+        << "- ITLB MISS COST         = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
+        << "- DTLB MISS COST         = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl   
+        << "- ITLB UPDATE ACC COST   = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
+        << "- DTLB UPDATE ACC COST   = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
+        << "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
+        << "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
+        << "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
+        << "- DCACHE FROZEN BY TLB OP= " << (float)(m_cost_ins_tlb_occup_cache_frz+m_cost_data_tlb_occup_cache_frz)/m_cpt_dcache_frz_cycles << std::endl
+        << "- DCACHE FOR TLB %       = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
+        << "- NB CC BROADCAST        = " << m_cpt_cc_broadcast << std::endl
+        << "- NB CC UPDATE DATA      = " << m_cpt_cc_update_data << std::endl
+        << "- NB CC INVAL DATA       = " << m_cpt_cc_inval_data << std::endl
+        << "- NB CC INVAL INS        = " << m_cpt_cc_inval_ins << std::endl
+        << "- NB CC CLEANUP DATA     = " << m_cpt_cc_cleanup_data << std::endl
+        << "- NB CC CLEANUP INS      = " << m_cpt_cc_cleanup_ins << std::endl
+        << "- IMISS TRANSACTION      = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
+        << "- DMISS TRANSACTION      = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
+        << "- UNC TRANSACTION        = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
+        << "- WRITE TRANSACTION      = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
+        << "- WRITE LENGTH           = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
+        << "- ITLB MISS TRANSACTION  = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
+        << "- DTLB MISS TRANSACTION  = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
 }
 
@@ -464,4 +475,5 @@
         r_dcache_dirty_save       = false;
         r_dcache_hit_p_save       = false;
+        r_dcache_cached_save      = false;
 
         r_icache_buf_unc_valid    = false;
@@ -527,6 +539,7 @@
         m_cpt_icache_dir_write  = 0;
 
-	m_cpt_frz_cycles   = 0;
-        m_cpt_total_cycles = 0;
+	m_cpt_frz_cycles        = 0;
+        m_cpt_dcache_frz_cycles = 0;
+	m_cpt_total_cycles      = 0;
 
         m_cpt_read         = 0;
@@ -543,36 +556,55 @@
         m_cost_ins_miss_frz  = 0;
 
-        m_cpt_imiss_transaction = 0;
-        m_cpt_dmiss_transaction = 0;
-        m_cpt_unc_transaction   = 0;
-        m_cpt_write_transaction = 0;
-
-        m_cost_imiss_transaction   = 0;
-        m_cost_dmiss_transaction   = 0;
-        m_cost_unc_transaction     = 0;
-        m_cost_write_transaction   = 0;
-        m_length_write_transaction = 0;
-
-        m_cpt_ins_tlb_read         = 0;             
-        m_cpt_ins_tlb_miss         = 0;             
-        m_cpt_ins_tlb_write_et     = 0;         
-
-        m_cpt_data_tlb_read        = 0;           
-        m_cpt_data_tlb_miss        = 0;           
-        m_cpt_data_tlb_write_et    = 0;       
-        m_cpt_data_tlb_write_dirty = 0;    
-
-        m_cost_ins_tlb_miss_frz    = 0;      
-        m_cost_data_tlb_miss_frz   = 0;      
-
-        m_cpt_itlbmiss_transaction   = 0;    
-        m_cpt_itlb_write_transaction = 0;  
-        m_cpt_dtlbmiss_transaction   = 0;  
-        m_cpt_dtlb_write_transaction = 0;  
+        m_cpt_imiss_transaction      = 0;
+        m_cpt_dmiss_transaction      = 0;
+        m_cpt_unc_transaction        = 0;
+        m_cpt_write_transaction      = 0;
+        m_cpt_icache_unc_transaction = 0;	
+
+        m_cost_imiss_transaction      = 0;
+        m_cost_dmiss_transaction      = 0;
+        m_cost_unc_transaction        = 0;
+        m_cost_write_transaction      = 0;
+	m_cost_icache_unc_transaction = 0;
+        m_length_write_transaction    = 0;
+
+        m_cpt_ins_tlb_read       = 0;             
+        m_cpt_ins_tlb_miss       = 0;             
+        m_cpt_ins_tlb_update_acc = 0;         
+
+        m_cpt_data_tlb_read         = 0;           
+        m_cpt_data_tlb_miss         = 0;           
+        m_cpt_data_tlb_update_acc   = 0;       
+        m_cpt_data_tlb_update_dirty = 0;    
+        m_cpt_ins_tlb_hit_dcache    = 0;
+        m_cpt_data_tlb_hit_dcache   = 0;
+        m_cpt_ins_tlb_occup_cache   = 0;
+        m_cpt_data_tlb_occup_cache  = 0;
+
+        m_cost_ins_tlb_miss_frz          = 0;      
+        m_cost_data_tlb_miss_frz         = 0;      
+        m_cost_ins_tlb_update_acc_frz    = 0;
+        m_cost_data_tlb_update_acc_frz   = 0;
+        m_cost_data_tlb_update_dirty_frz = 0;
+        m_cost_ins_tlb_occup_cache_frz   = 0;
+        m_cost_data_tlb_occup_cache_frz  = 0;
+
+        m_cpt_itlbmiss_transaction      = 0;    
+        m_cpt_itlb_ll_transaction       = 0;  
+        m_cpt_itlb_sc_transaction       = 0;  
+        m_cpt_dtlbmiss_transaction      = 0;  
+        m_cpt_dtlb_ll_transaction       = 0;  
+        m_cpt_dtlb_sc_transaction       = 0;  
+        m_cpt_dtlb_ll_dirty_transaction = 0;  
+        m_cpt_dtlb_sc_dirty_transaction = 0;  
  
-        m_cost_itlbmiss_transaction   = 0;   
-        m_cost_itlb_write_transaction = 0;  
-        m_cost_dtlbmiss_transaction   = 0;   
-        m_cost_dtlb_write_transaction = 0;   
+        m_cost_itlbmiss_transaction      = 0;   
+        m_cost_itlb_ll_transaction       = 0;  
+        m_cost_itlb_sc_transaction       = 0;  
+        m_cost_dtlbmiss_transaction      = 0;   
+        m_cost_dtlb_ll_transaction       = 0;   
+        m_cost_dtlb_sc_transaction       = 0;   
+        m_cost_dtlb_ll_dirty_transaction = 0;   
+        m_cost_dtlb_sc_dirty_transaction = 0;    
         return;
     }
@@ -691,5 +723,5 @@
                     r_tgt_update = false; 
                     r_vci_tgt_fsm = TGT_REQ_DCACHE;
-                    m_cpt_cc_inval++ ;
+                    m_cpt_cc_inval_data++ ;
                 }
                 else if (cell == 4)                // update 
@@ -703,5 +735,5 @@
                     r_tgt_update = true; 
                     r_vci_tgt_fsm = TGT_UPDT_WORD;
-                    m_cpt_cc_update++ ;
+                    m_cpt_cc_update_data++ ;
                 }     
 		else if (cell == 8)
@@ -715,5 +747,5 @@
                     r_tgt_update = false; 
                     r_vci_tgt_fsm = TGT_REQ_ICACHE;
-                    m_cpt_cc_inval++ ;
+                    m_cpt_cc_inval_ins++ ;
 
 		}
@@ -948,5 +980,4 @@
         if ( r_tgt_icache_req )
         {
-            if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
             r_icache_fsm = ICACHE_CC_INVAL;
             r_icache_fsm_save = r_icache_fsm;
@@ -957,5 +988,4 @@
         if ( r_dcache_itlb_inval_req )
         {
-            if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
 	    r_itlb_inval_req = true;
             r_icache_fsm = ICACHE_TLB_CC_INVAL;
@@ -1119,11 +1149,10 @@
     case ICACHE_BIS: 
     {
-        m_cost_ins_miss_frz++;
         // external cache invalidate request
         if ( r_tgt_icache_req )
         {
+	    if ( ireq.valid ) m_cost_ins_miss_frz++;
             r_icache_fsm = ICACHE_CC_INVAL;
             r_icache_fsm_save = r_icache_fsm;
-            m_cost_ins_waste_wait_frz++;
             break;
         }
@@ -1132,8 +1161,8 @@
         if ( r_dcache_itlb_inval_req )
         {
+	    if ( ireq.valid ) m_cost_ins_miss_frz++;
 	    r_itlb_inval_req = true;
             r_icache_fsm = ICACHE_TLB_CC_INVAL;
             r_icache_fsm_save = r_icache_fsm;
-            m_cost_ins_waste_wait_frz++;
             break;
         }
@@ -1142,7 +1171,7 @@
         if ( r_icache_inval_tlb_rsp )
         {
+	    if ( ireq.valid ) m_cost_ins_miss_frz++;
             r_icache_inval_tlb_rsp = false;
             r_icache_fsm = ICACHE_IDLE;
-            m_cost_ins_tlb_miss_frz++;
             break;
         }
@@ -1167,4 +1196,5 @@
                 r_icache_fsm = ICACHE_MISS_WAIT;
                 m_cpt_ins_miss++;
+                m_cost_ins_miss_frz++;
             } 
             else
@@ -1191,5 +1221,5 @@
     case ICACHE_TLB1_READ:
     {
-        m_cost_ins_tlb_miss_frz++;
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
 
         // external cache invalidate request
@@ -1198,5 +1228,4 @@
             r_icache_fsm = ICACHE_CC_INVAL;
             r_icache_fsm_save = r_icache_fsm;
-            m_cost_ins_waste_wait_frz++;
             break;
         }
@@ -1208,5 +1237,4 @@
             r_icache_fsm = ICACHE_TLB_CC_INVAL;
             r_icache_fsm_save = r_icache_fsm;
-            m_cost_ins_waste_wait_frz++;
             break;
         }
@@ -1262,5 +1290,6 @@
                                 r_itlb_acc_dcache_req = true;
                                 r_icache_fsm          = ICACHE_TLB1_WRITE;
-                                m_cpt_ins_tlb_write_et++;
+                                m_cpt_ins_tlb_update_acc++;
+                                m_cost_ins_tlb_update_acc_frz++;
             		    }
                         }
@@ -1277,5 +1306,6 @@
                                 r_itlb_acc_dcache_req = true;
                                 r_icache_fsm          = ICACHE_TLB1_WRITE;
-                                m_cpt_ins_tlb_write_et++;
+                                m_cpt_ins_tlb_update_acc++;
+                                m_cost_ins_tlb_update_acc_frz++;
             		    }
             	        }
@@ -1311,5 +1341,6 @@
     case ICACHE_TLB1_WRITE:  
     {
-        m_cost_ins_tlb_miss_frz++;
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
+        m_cost_ins_tlb_update_acc_frz++;
 
         // external cache invalidate request
@@ -1318,5 +1349,4 @@
             r_icache_fsm = ICACHE_CC_INVAL;
             r_icache_fsm_save = r_icache_fsm;
-            m_cost_ins_waste_wait_frz++;
             break;
         }
@@ -1327,5 +1357,4 @@
             r_icache_fsm = ICACHE_TLB_CC_INVAL;
             r_icache_fsm_save = r_icache_fsm;
-            m_cost_ins_waste_wait_frz++;
             break;
         }
@@ -1368,5 +1397,5 @@
     case ICACHE_TLB1_UPDT:
     {
-        m_cost_ins_tlb_miss_frz++;
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
 
         // external cache invalidate request
@@ -1375,5 +1404,4 @@
             r_icache_fsm = ICACHE_CC_INVAL;
             r_icache_fsm_save = r_icache_fsm;
-            m_cost_ins_waste_wait_frz++;
             break;
         }
@@ -1385,5 +1413,4 @@
             r_icache_fsm = ICACHE_TLB_CC_INVAL;
             r_icache_fsm_save = r_icache_fsm;
-            m_cost_ins_waste_wait_frz++;
             break;
         }
@@ -1395,4 +1422,5 @@
             r_dcache_itlb_cleanup_req = icache_tlb.update(r_icache_pte_update,r_icache_vaddr_req.read(),(r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index);
             r_dcache_itlb_cleanup_line = victim_index;
+	    m_cpt_cc_cleanup_ins++;
             r_icache_fsm = ICACHE_IDLE;
         }
@@ -1409,5 +1437,5 @@
     case ICACHE_TLB2_READ:
     {
-        m_cost_ins_tlb_miss_frz++;
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
 
         // external cache invalidate request
@@ -1416,5 +1444,4 @@
             r_icache_fsm = ICACHE_CC_INVAL;
             r_icache_fsm_save = r_icache_fsm;
-            m_cost_ins_waste_wait_frz++;
             break;
         }
@@ -1426,5 +1453,4 @@
             r_icache_fsm = ICACHE_TLB_CC_INVAL;
             r_icache_fsm_save = r_icache_fsm;
-            m_cost_ins_waste_wait_frz++;
             break;
         }
@@ -1466,5 +1492,6 @@
                         	r_itlb_acc_dcache_req = true;
                         	r_icache_fsm          = ICACHE_TLB2_WRITE;
-                         	m_cpt_ins_tlb_write_et++;
+                                m_cpt_ins_tlb_update_acc++;
+                                m_cost_ins_tlb_update_acc_frz++;
             		    }
                         }
@@ -1481,5 +1508,6 @@
                         	r_itlb_acc_dcache_req = true;
                         	r_icache_fsm          = ICACHE_TLB2_WRITE;
-                        	m_cpt_ins_tlb_write_et++;
+                                m_cpt_ins_tlb_update_acc++;
+                                m_cost_ins_tlb_update_acc_frz++;
             		    }
             	        }
@@ -1515,5 +1543,6 @@
     case ICACHE_TLB2_WRITE:
     {  
-        m_cost_ins_tlb_miss_frz++;
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
+        m_cost_ins_tlb_update_acc_frz++;
 
         // external cache invalidate request
@@ -1522,5 +1551,4 @@
             r_icache_fsm = ICACHE_CC_INVAL;
             r_icache_fsm_save = r_icache_fsm;
-            m_cost_ins_waste_wait_frz++;
             break;
         }
@@ -1531,5 +1559,4 @@
             r_icache_fsm = ICACHE_TLB_CC_INVAL;
             r_icache_fsm_save = r_icache_fsm;
-            m_cost_ins_waste_wait_frz++;
             break;
         }
@@ -1572,5 +1599,5 @@
     case ICACHE_TLB2_UPDT: 
     {
-        m_cost_ins_tlb_miss_frz++;
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
 
         // external cache invalidate request
@@ -1579,5 +1606,4 @@
             r_icache_fsm = ICACHE_CC_INVAL;
             r_icache_fsm_save = r_icache_fsm;
-            m_cost_ins_waste_wait_frz++;
             break;
         }
@@ -1589,5 +1615,4 @@
             r_icache_fsm = ICACHE_TLB_CC_INVAL;
             r_icache_fsm_save = r_icache_fsm;
-            m_cost_ins_waste_wait_frz++;
             break;
         }
@@ -1599,4 +1624,5 @@
             r_dcache_itlb_cleanup_req = icache_tlb.update(r_icache_pte_update,r_dcache_rsp_itlb_ppn,r_icache_vaddr_req.read(),(r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index);
             r_dcache_itlb_cleanup_line = victim_index;
+	    m_cpt_cc_cleanup_ins++;
             r_icache_fsm = ICACHE_IDLE;
         }
@@ -1616,5 +1642,4 @@
         bool clean = false;
 
-        if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
         m_cost_ins_tlb_sw_frz++;
 
@@ -1654,6 +1679,4 @@
     case ICACHE_TLB_FLUSH:
     {   
-        if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
-
         // data cache flush leads to ins tlb flush, flush all tlb entry 
         icache_tlb.flush(true);    // global entries are invalidated
@@ -1672,5 +1695,4 @@
             r_icache_fsm = ICACHE_CC_INVAL;
             r_icache_fsm_save = r_icache_fsm;
-            m_cost_ins_waste_wait_frz++;
             break;
         }
@@ -1679,7 +1701,4 @@
         size_t set = r_icache_set;
         bool clean = false;
-
-        m_cost_ins_cache_flush_frz++;
-        if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
 
         // cache flush and send cleanup to external
@@ -1696,4 +1715,5 @@
                         r_icache_cleanup_req = true;
                         r_icache_cleanup_line = victim_index;
+			m_cpt_cc_cleanup_ins++;
                         r_icache_way = way + ((set+1)/m_icache_sets);
                         r_icache_set = (set+1) % m_icache_sets;
@@ -1715,5 +1735,4 @@
     case ICACHE_TLB_INVAL:  
     {
-        if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
         paddr_t victim_index = 0;
 
@@ -1722,4 +1741,5 @@
             r_dcache_itlb_cleanup_req = icache_tlb.inval(r_dcache_wdata_save, &victim_index);
             r_dcache_itlb_cleanup_line = victim_index;
+	    m_cpt_cc_cleanup_ins++;
             r_dcache_xtn_req = false;
             r_itlb_translation_valid = false;
@@ -1732,5 +1752,4 @@
     case ICACHE_CACHE_INVAL:
     {	
-        if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
         // external cache invalidate request
         if ( r_tgt_icache_req )
@@ -1738,5 +1757,4 @@
             r_icache_fsm = ICACHE_CC_INVAL;
             r_icache_fsm_save = r_icache_fsm;
-            m_cost_ins_waste_wait_frz++;
             break;
         }
@@ -1760,5 +1778,6 @@
                 // invalidate and cleanup if necessary
                 r_icache_cleanup_req = r_icache.inval(ipaddr);
-                r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2);   
+                r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2);  
+	        m_cpt_cc_cleanup_ins++;	
             }
             r_dcache_xtn_req = false; 
@@ -1775,5 +1794,4 @@
             r_icache_fsm = ICACHE_CC_INVAL;
             r_icache_fsm_save = r_icache_fsm;
-            m_cost_ins_waste_wait_frz++;
             break;
         }
@@ -1785,5 +1803,6 @@
             // invalidate and cleanup if necessary
             r_icache_cleanup_req = r_icache.inval(ipaddr);
-            r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2);   
+            r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2);  
+	    m_cpt_cc_cleanup_ins++; 
             r_dcache_xtn_req = false; 
             r_icache_fsm = ICACHE_IDLE;
@@ -1801,5 +1820,4 @@
             r_icache_fsm = ICACHE_CC_INVAL;
             r_icache_fsm_save = r_icache_fsm;
-            m_cost_ins_waste_wait_frz++;
             break;
         }
@@ -1811,5 +1829,4 @@
             r_icache_fsm = ICACHE_TLB_CC_INVAL;
             r_icache_fsm_save = r_icache_fsm;
-            m_cost_ins_waste_wait_frz++;
             break;
         }
@@ -1832,9 +1849,9 @@
 		if ( r_icache_cleanup_req ) break;
                 r_icache_cleanup_req = true;
-                r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);  
+                r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); 
+	        m_cpt_cc_cleanup_ins++;	
                 r_icache_fsm = ICACHE_IDLE;
                 r_icache_inval_tlb_rsp = false;
                 if ( r_icache_inval_rsp ) r_icache_inval_rsp = false;
-                m_cost_ins_tlb_miss_frz++;
                 break;
             }
@@ -1845,4 +1862,5 @@
                 r_icache_cleanup_req = true;
                 r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);  
+		m_cpt_cc_cleanup_ins++;
                 r_icache_fsm = ICACHE_IDLE;
                 r_icache_inval_rsp = false;
@@ -1856,6 +1874,4 @@
     case ICACHE_UNC_WAIT:
     {
-        m_cost_ins_miss_frz++;
-
         // external cache invalidate request
         if ( r_tgt_icache_req ) 
@@ -1863,5 +1879,4 @@
             r_icache_fsm = ICACHE_CC_INVAL;
             r_icache_fsm_save = r_icache_fsm;
-            m_cost_ins_waste_wait_frz++;
             break;
         }
@@ -1873,5 +1888,4 @@
             r_icache_fsm = ICACHE_TLB_CC_INVAL;
             r_icache_fsm_save = r_icache_fsm;
-            m_cost_ins_waste_wait_frz++;
             break;
         }
@@ -1913,5 +1927,4 @@
             r_icache_fsm = ICACHE_CC_INVAL;
             r_icache_fsm_save = r_icache_fsm;
-            m_cost_ins_waste_wait_frz++;
             break;
         }
@@ -1923,5 +1936,4 @@
             r_icache_fsm = ICACHE_TLB_CC_INVAL;
             r_icache_fsm_save = r_icache_fsm;
-            m_cost_ins_waste_wait_frz++;
             break;
         }
@@ -1931,9 +1943,9 @@
             if ( r_icache_cleanup_req ) break;
             r_icache_cleanup_req = true;
-            r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);  
+            r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); 
+	    m_cpt_cc_cleanup_ins++; 
             r_icache_inval_tlb_rsp = false;
             if ( r_icache_inval_rsp ) r_icache_inval_rsp = false;
             r_icache_fsm = ICACHE_IDLE;
-            m_cost_ins_tlb_miss_frz++;
             break;
         }
@@ -1944,5 +1956,6 @@
             {
                 r_icache_cleanup_req = true;
-                r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);  
+                r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); 
+	        m_cpt_cc_cleanup_ins++;	
                 r_icache_fsm = ICACHE_IDLE;
                 r_icache_inval_rsp = false;
@@ -1956,6 +1969,5 @@
 
                 r_icache_cleanup_req = r_icache.update(r_icache_paddr_save.read(), buf, &victim_index);
-                r_icache_cleanup_line = victim_index;            
-
+                r_icache_cleanup_line = victim_index;                        m_cpt_cc_cleanup_ins++;
                 r_icache_fsm = ICACHE_IDLE;
 	    }
@@ -1977,6 +1989,16 @@
     case ICACHE_CC_INVAL:  
     {                       
-        if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
         m_cpt_icache_dir_read += m_icache_ways;
+        /* activity counter */
+        if ( (( r_icache_fsm_save == ICACHE_BIS ) ||( r_icache_fsm_save == ICACHE_MISS_WAIT ) || ( r_icache_fsm_save == ICACHE_MISS_UPDT ) ) && ( ireq.valid ) )        
+        {
+            m_cost_ins_miss_frz++;
+        }
+        if( (( r_icache_fsm_save == ICACHE_TLB1_READ )   || ( r_icache_fsm_save == ICACHE_TLB2_READ )    ||
+             ( r_icache_fsm_save == ICACHE_TLB1_WRITR )  || ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) ||
+             ( r_icache_fsm_save == ICACHE_TLB1_UPDT )   || ( r_icache_fsm_save == ICACHE_TLB2_UPDT ))   && (ireq.valid) )
+        {
+            m_cost_ins_tlb_miss_frz++;
+        }
 
         // invalidate cache
@@ -1999,5 +2021,15 @@
     case ICACHE_TLB_CC_INVAL:
     {
-        if ( ireq.valid ) m_cost_ins_waste_wait_frz++;        
+        /* activity counter */
+        if ( (( r_icache_fsm_save == ICACHE_BIS ) ||( r_icache_fsm_save == ICACHE_MISS_WAIT ) || ( r_icache_fsm_save == ICACHE_MISS_UPDT ) ) && ( ireq.valid ) )        
+        {
+            m_cost_ins_miss_frz++;
+        }
+        if( (( r_icache_fsm_save == ICACHE_TLB1_READ )   || ( r_icache_fsm_save == ICACHE_TLB2_READ )    ||
+             ( r_icache_fsm_save == ICACHE_TLB1_WRITR )  || ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) ||
+             ( r_icache_fsm_save == ICACHE_TLB1_UPDT )   || ( r_icache_fsm_save == ICACHE_TLB2_UPDT ))   && (ireq.valid) )
+        {
+            m_cost_ins_tlb_miss_frz++;
+        }
 
 	if ( r_itlb_inval_req ) break;
@@ -2148,5 +2180,4 @@
             r_dcache_fsm = DCACHE_CC_CHECK;
             r_dcache_fsm_save = r_dcache_fsm;
-            if ( dreq.valid ) m_cost_data_waste_wait_frz++; 
             break;
         }
@@ -2194,5 +2225,4 @@
             r_dcache_fsm = DCACHE_CC_CHECK;
             r_dcache_fsm_save = DCACHE_IDLE;
-            if ( dreq.valid ) m_cost_data_waste_wait_frz++;
             break;
         }        
@@ -2202,6 +2232,4 @@
         {
             r_dcache_fsm = DCACHE_ITLB_CLEANUP;
-            m_cpt_ins_tlb_cleanup++;
-            if ( dreq.valid ) m_cost_data_waste_wait_frz++;
             break;
         }    
@@ -2209,4 +2237,5 @@
     	if ( r_itlb_read_dcache_req )
     	{
+            if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++;		
             data_t rsp_itlb_miss;
 	    data_t rsp_itlb_ppn;
@@ -2225,4 +2254,5 @@
     	    if ( itlb_hit_dcache )  // ins TLB request hits in data cache 
     	    {
+                if (!((rsp_itlb_miss & PTE_T_MASK ) >> PTE_T_SHIFT)) m_cpt_ins_tlb_hit_dcache++;		    
                 r_dcache_rsp_itlb_miss = rsp_itlb_miss; 
                 r_dcache_rsp_itlb_ppn = rsp_itlb_ppn; 
@@ -2241,5 +2271,4 @@
                 r_dcache_fsm = DCACHE_ITLB_READ;
             }
-            if ( dreq.valid ) m_cost_data_waste_wait_frz++; 
     	}
     	else if ( r_itlb_acc_dcache_req ) // ins tlb write access bit
@@ -2248,6 +2277,6 @@
             assert(write_hit && "Write on miss ignores data");
             r_dcache_itlb_ll_acc_req = true;
-	    r_dcache_fsm = DCACHE_ITLB_LL_WAIT;	    		
-            if ( dreq.valid ) m_cost_data_waste_wait_frz++; 
+	    r_dcache_fsm = DCACHE_ITLB_LL_WAIT;	    	
+            m_cpt_dcache_data_write++;	    
     	}
         else if (dreq.valid) 
@@ -2630,5 +2659,5 @@
                 r_dcache_hit_p_save = dcache_hit_p;
                 r_dcache_fsm = DCACHE_BIS;
-                m_cost_data_miss_frz++;
+                m_cost_data_tlb_miss_frz++;
             }
             else  // cached or uncached access with a correct speculative physical address
@@ -2730,5 +2759,5 @@
                         m_cpt_write++;
                         if ( dcache_cached ) m_cpt_write_cached++;
-
+			m_cost_write_frz++;
                         if ( dcache_hit_c && dcache_cached )    // cache update required
                         {
@@ -2737,4 +2766,6 @@
                         else if ( !dcache_pte_info.d && (r_mmu_mode.read() & DATA_TLB_MASK) )   // dirty bit update required
                         {
+			    m_cpt_data_tlb_update_dirty++;
+                            m_cost_data_tlb_update_dirty_frz++;
                             if ( dcache_tlb.getpagesize(dcache_tlb_way, dcache_tlb_set) )	// 2M page size, one level page table 
                             {
@@ -2743,5 +2774,4 @@
                                 r_dcache_tlb_ll_dirty_req = true;
                                 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
-                                m_cpt_data_tlb_write_dirty++;
                             }
                             else	// 4k page size, two levels page table 
@@ -2753,5 +2783,4 @@
                                     r_dcache_tlb_ll_dirty_req = true;
                                     r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
-                                    m_cpt_data_tlb_write_dirty++;
                                 }
                                 else    // get PTBA to calculate the physical address of PTE
@@ -2763,5 +2792,4 @@
                                 }
                             }
-                            m_cost_data_tlb_miss_frz++;
                         }
                         else                                    // no cache update, not dirty bit update
@@ -2812,5 +2840,5 @@
             r_dcache_fsm = DCACHE_CC_CHECK;
             r_dcache_fsm_save = r_dcache_fsm;
-            m_cost_data_waste_wait_frz++;
+            if ( dreq.valid ) m_cost_data_miss_frz++;
             break;
         }
@@ -2821,5 +2849,5 @@
             r_dcache_inval_tlb_rsp = false;
             r_dcache_fsm = DCACHE_IDLE;
-            m_cost_data_tlb_miss_frz++;
+            if ( dreq.valid ) m_cost_data_miss_frz++;
             break;
         }
@@ -2866,4 +2894,6 @@
 	        else if (!r_dcache_dirty_save && (r_mmu_mode.read() & DATA_TLB_MASK))   // dirty bit update required
 	        {
+                    m_cpt_data_tlb_update_dirty++;
+                    m_cost_data_tlb_update_dirty_frz++;  			
 	            if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save)) 
 	            {
@@ -2872,5 +2902,4 @@
 	                r_dcache_tlb_ll_dirty_req = true;
 	                r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
-	                m_cpt_data_tlb_write_dirty++;
 	            }
 	            else
@@ -2882,5 +2911,4 @@
 	                    r_dcache_tlb_ll_dirty_req = true;
 	                    r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
-	                    m_cpt_data_tlb_write_dirty++;
 	                }
 	                else
@@ -2892,5 +2920,4 @@
 	                }
 	            }
-	            m_cost_data_tlb_miss_frz++;
 	        }
 	        else                                    // no cache update, not dirty bit update
@@ -2914,4 +2941,6 @@
     case DCACHE_LL_DIRTY_WAIT:
     {
+	m_cost_data_tlb_update_dirty_frz++;
+
         // external cache invalidate request
         if ( r_tgt_dcache_req )   
@@ -2919,5 +2948,4 @@
             r_dcache_fsm = DCACHE_CC_CHECK;
             r_dcache_fsm_save = r_dcache_fsm;
-            m_cost_data_waste_wait_frz++;
             break;
         }
@@ -2963,5 +2991,4 @@
         	    r_dcache_inval_tlb_rsp = false;
         	    r_dcache_fsm = DCACHE_IDLE;
-        	    m_cost_data_tlb_miss_frz++;
         	}
 		else if ( r_dcache_inval_rsp )
@@ -2983,4 +3010,5 @@
     case DCACHE_SC_DIRTY_WAIT:
     {
+        m_cost_data_tlb_update_dirty_frz++;	    
         // external cache invalidate request
         if ( r_tgt_dcache_req )   
@@ -2988,5 +3016,4 @@
             r_dcache_fsm = DCACHE_CC_CHECK;
             r_dcache_fsm_save = r_dcache_fsm;
-            m_cost_data_waste_wait_frz++;
             break;
         }
@@ -3018,5 +3045,4 @@
                     r_dcache_fsm = DCACHE_IDLE;
 		    if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
-                    m_cost_data_tlb_miss_frz++;
                 }
 		else if ( r_dcache_inval_rsp )
@@ -3030,5 +3056,6 @@
 		    r_dcache_tlb_ll_dirty_req = true;
 		    r_dcache_tlb_sc_fail = false;
-	            r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 
+	            r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+		    m_cpt_data_tlb_update_dirty++; 
 	        }
 		else
@@ -3050,5 +3077,4 @@
             r_dcache_fsm = DCACHE_CC_CHECK;
             r_dcache_fsm_save = r_dcache_fsm;
-            m_cost_data_waste_wait_frz++;
             break;
         }        
@@ -3059,5 +3085,4 @@
             r_dcache_inval_tlb_rsp = false;
             r_dcache_fsm = DCACHE_IDLE;
-            m_cost_data_tlb_miss_frz++;
             break;
         }
@@ -3099,5 +3124,6 @@
                     r_dcache_tlb_ll_dirty_req = true;
                     r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
-                    m_cpt_data_tlb_write_dirty++;
+		    m_cpt_dcache_data_write++; 
+                    m_cost_data_tlb_update_dirty_frz++;
                 }
                 else
@@ -3108,4 +3134,5 @@
 	    else	// PTE
 	    {
+		m_cpt_data_tlb_hit_dcache++;
                 r_dcache_ptba_ok = false;
 	        if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
@@ -3123,5 +3150,7 @@
                 	assert(write_hit && "Write on miss ignores data");  
                         r_dcache_fsm = DCACHE_TLB1_LL_WAIT;
-                        m_cpt_ins_tlb_write_et++;
+			m_cpt_dcache_data_write++; 
+                        m_cpt_data_tlb_update_acc++;
+                        m_cost_data_tlb_update_acc_frz++;
 		    }
     	        }
@@ -3140,5 +3169,7 @@
                 	assert(write_hit && "Write on miss ignores data");  
                         r_dcache_fsm = DCACHE_TLB1_LL_WAIT;
-                        m_cpt_ins_tlb_write_et++;
+			m_cpt_dcache_data_write++; 
+                        m_cpt_data_tlb_update_acc++;
+                        m_cost_data_tlb_update_acc_frz++;
 		    }
 		}
@@ -3156,4 +3187,6 @@
     case DCACHE_TLB1_LL_WAIT:
     {
+        if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
+        m_cost_data_tlb_update_acc_frz++;	    
         // external cache invalidate request
         if ( r_tgt_dcache_req )   
@@ -3161,5 +3194,4 @@
             r_dcache_fsm = DCACHE_CC_CHECK;
             r_dcache_fsm_save = r_dcache_fsm;
-            m_cost_data_waste_wait_frz++;
             break;
         }
@@ -3205,5 +3237,4 @@
        		    r_dcache_inval_tlb_rsp = false;
        		    r_dcache_fsm = DCACHE_IDLE;
-       		    m_cost_data_tlb_miss_frz++;
        		}
 		else if ( r_dcache_inval_rsp )
@@ -3225,4 +3256,6 @@
     case DCACHE_TLB1_SC_WAIT:
     {
+        if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
+        m_cost_data_tlb_update_acc_frz++;	    
         // external cache invalidate request
         if ( r_tgt_dcache_req )   
@@ -3230,5 +3263,4 @@
             r_dcache_fsm = DCACHE_CC_CHECK;
             r_dcache_fsm_save = r_dcache_fsm;
-            m_cost_data_waste_wait_frz++;
             break;
         }
@@ -3260,5 +3292,4 @@
         	    r_dcache_fsm = DCACHE_IDLE;
 		    if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
-        	    m_cost_data_tlb_miss_frz++;
         	}
 		else if ( r_dcache_inval_rsp )
@@ -3272,5 +3303,6 @@
 		    r_dcache_tlb_sc_fail = false;
 		    r_dcache_tlb_ll_acc_req = true;
-	    	    r_dcache_fsm = DCACHE_TLB1_LL_WAIT; 
+	    	    r_dcache_fsm = DCACHE_TLB1_LL_WAIT;
+                    m_cpt_data_tlb_update_acc++;
 	    	}
 	    	else 
@@ -3285,5 +3317,5 @@
     case DCACHE_TLB1_READ:
     {
-        m_cost_data_tlb_miss_frz++;
+        if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
 
         // external cache invalidate request
@@ -3292,5 +3324,4 @@
             r_dcache_fsm = DCACHE_CC_CHECK;
             r_dcache_fsm_save = r_dcache_fsm;
-            m_cost_data_waste_wait_frz++;
             break;
         }        
@@ -3328,4 +3359,5 @@
                 r_dcache_cleanup_req = true;
                 r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);  
+		m_cpt_cc_cleanup_data++;
                 r_dcache_fsm = DCACHE_IDLE;
                 r_dcache_inval_rsp = false;
@@ -3348,5 +3380,4 @@
             r_dcache_fsm = DCACHE_CC_CHECK;
             r_dcache_fsm_save = r_dcache_fsm;
-            m_cost_data_waste_wait_frz++;
             break;
         }        
@@ -3357,5 +3388,4 @@
             r_dcache_inval_tlb_rsp = false;
             r_dcache_fsm = DCACHE_IDLE;
-            m_cost_data_tlb_miss_frz++;
             break;
         }
@@ -3374,5 +3404,6 @@
             {
                 r_dcache_cleanup_req = true;
-                r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);  
+                r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2); 
+	        m_cpt_cc_cleanup_data++;	
                 r_dcache_fsm = DCACHE_IDLE;
                 r_dcache_inval_rsp = false;
@@ -3396,4 +3427,5 @@
                 r_dcache_cleanup_req = true; 
                 r_dcache_cleanup_line = victim_index;
+		m_cpt_cc_cleanup_data++;
 		r_dcache_fsm = DCACHE_TLB_CC_INVAL;
                 r_dcache_fsm_save = r_dcache_fsm;
@@ -3403,4 +3435,5 @@
 	    r_dcache.update(r_dcache_tlb_paddr, way, set, r_dcache_miss_buf);
             r_dcache.read(r_dcache_tlb_paddr, &rsp_dtlb_miss);	
+	    m_cpt_data_tlb_occup_cache++;
 
 	    if ( !(rsp_dtlb_miss >> PTE_V_SHIFT) )	// unmapped
@@ -3433,5 +3466,7 @@
                     r_dcache_tlb_ll_dirty_req = true;
                     r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
-                    m_cpt_data_tlb_write_dirty++;
+		    m_cpt_dcache_data_write++; 
+                    m_cpt_data_tlb_update_dirty++;
+                    m_cost_data_tlb_update_dirty_frz++;
                 }
                 else
@@ -3457,5 +3492,7 @@
                 	assert(write_hit && "Write on miss ignores data");  
                         r_dcache_fsm        = DCACHE_TLB1_LL_WAIT;
-                        m_cpt_ins_tlb_write_et++;
+			m_cpt_dcache_data_write++; 
+			m_cpt_data_tlb_update_acc++;
+                        m_cost_data_tlb_update_acc_frz++;
 		    }
     	        }
@@ -3474,5 +3511,7 @@
                 	assert(write_hit && "Write on miss ignores data");  
                         r_dcache_fsm        = DCACHE_TLB1_LL_WAIT;
-                        m_cpt_ins_tlb_write_et++;
+			m_cpt_dcache_data_write++; 
+			m_cpt_data_tlb_update_acc++;
+                        m_cost_data_tlb_update_acc_frz++;
 		    }
 		}
@@ -3491,5 +3530,4 @@
             r_dcache_fsm = DCACHE_CC_CHECK;
             r_dcache_fsm_save = r_dcache_fsm;
-            m_cost_data_waste_wait_frz++;
             break;
         }        
@@ -3523,5 +3561,4 @@
             r_dcache_fsm = DCACHE_CC_CHECK;
             r_dcache_fsm_save = r_dcache_fsm;
-            m_cost_data_waste_wait_frz++;
             break;
         }        
@@ -3532,5 +3569,4 @@
             r_dcache_inval_tlb_rsp = false;
             r_dcache_fsm = DCACHE_IDLE;
-            m_cost_data_tlb_miss_frz++;
             break;
         }
@@ -3571,4 +3607,5 @@
 	    else 
 	    {
+		m_cpt_data_tlb_hit_dcache++;
 	        if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
 		{
@@ -3587,5 +3624,7 @@
                 	assert(write_hit && "Write on miss ignores data");  
                         r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
-                        m_cpt_ins_tlb_write_et++;
+			m_cpt_dcache_data_write++; 
+                        m_cpt_data_tlb_update_acc++;
+                        m_cost_data_tlb_update_acc_frz++;
 		    }
     	        }
@@ -3606,5 +3645,7 @@
                 	assert(write_hit && "Write on miss ignores data");  
                         r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
-                        m_cpt_ins_tlb_write_et++;
+			m_cpt_dcache_data_write++; 
+                        m_cpt_data_tlb_update_acc++;
+                        m_cost_data_tlb_update_acc_frz++;
 		    }
 		}
@@ -3622,4 +3663,7 @@
     case DCACHE_TLB2_LL_WAIT:
     {
+        if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
+        m_cost_data_tlb_update_acc_frz++;
+
         // external cache invalidate request
         if ( r_tgt_dcache_req )   
@@ -3627,5 +3671,4 @@
             r_dcache_fsm = DCACHE_CC_CHECK;
             r_dcache_fsm_save = r_dcache_fsm;
-            m_cost_data_waste_wait_frz++;
             break;
         }
@@ -3671,5 +3714,4 @@
         	    r_dcache_inval_tlb_rsp = false;
         	    r_dcache_fsm = DCACHE_IDLE;
-        	    m_cost_data_tlb_miss_frz++;
         	}
 		else if ( r_dcache_inval_rsp )
@@ -3691,4 +3733,6 @@
     case DCACHE_TLB2_SC_WAIT:
     {
+        if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
+        m_cost_data_tlb_update_acc_frz++;	    
         // external cache invalidate request
         if ( r_tgt_dcache_req )   
@@ -3696,5 +3740,4 @@
             r_dcache_fsm = DCACHE_CC_CHECK;
             r_dcache_fsm_save = r_dcache_fsm;
-            m_cost_data_waste_wait_frz++;
             break;
         }
@@ -3726,5 +3769,4 @@
 		    if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
                     r_dcache_fsm = DCACHE_IDLE;
-                    m_cost_data_tlb_miss_frz++;
                 }
 		else if ( r_dcache_inval_rsp )
@@ -3738,5 +3780,6 @@
 	            r_dcache_tlb_ll_acc_req = true;
 		    r_dcache_tlb_sc_fail = false;
-	            r_dcache_fsm = DCACHE_TLB2_LL_WAIT; 
+	            r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
+		    m_cpt_data_tlb_update_acc++;
 	        }
 	        else 
@@ -3758,5 +3801,4 @@
             r_dcache_fsm = DCACHE_CC_CHECK;
             r_dcache_fsm_save = r_dcache_fsm;
-            m_cost_data_waste_wait_frz++;
             break;
         }        
@@ -3794,4 +3836,5 @@
                 r_dcache_cleanup_req = true;
                 r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);  
+		m_cpt_cc_cleanup_data++;
                 r_dcache_fsm = DCACHE_IDLE;
                 r_dcache_inval_rsp = false;
@@ -3814,5 +3857,4 @@
             r_dcache_fsm = DCACHE_CC_CHECK;
             r_dcache_fsm_save = r_dcache_fsm;
-            m_cost_data_waste_wait_frz++;
             break;
         }        
@@ -3823,5 +3865,4 @@
             r_dcache_inval_tlb_rsp = false;
             r_dcache_fsm = DCACHE_IDLE;
-            m_cost_data_tlb_miss_frz++;
             break;
         }
@@ -3842,4 +3883,5 @@
                 r_dcache_cleanup_req = true;
                 r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);  
+		m_cpt_cc_cleanup_data++;
                 r_dcache_fsm = DCACHE_IDLE;
                 r_dcache_inval_rsp = false;
@@ -3863,4 +3905,5 @@
                 r_dcache_cleanup_req = true; 
                 r_dcache_cleanup_line = victim_index;
+		m_cpt_cc_cleanup_data++;
 		r_dcache_fsm = DCACHE_TLB_CC_INVAL;
                 r_dcache_fsm_save = r_dcache_fsm;
@@ -3870,4 +3913,5 @@
 	    r_dcache.update(r_dcache_tlb_paddr, way, set, r_dcache_miss_buf);
 	    r_dcache.read(r_dcache_tlb_paddr, &rsp_dtlb_miss);
+	    m_cpt_data_tlb_occup_cache++;
 
 	    bool tlb_hit_ppn = r_dcache.read(r_dcache_tlb_paddr.read()+4, &tlb_data_ppn);
@@ -3911,5 +3955,7 @@
                 	assert(write_hit && "Write on miss ignores data");  
                         r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
-                        m_cpt_ins_tlb_write_et++;
+			m_cpt_dcache_data_write++; 
+                        m_cpt_data_tlb_update_acc++;
+                        m_cost_data_tlb_update_acc_frz++;
 		    }
     	        }
@@ -3930,5 +3976,7 @@
                 	assert(write_hit && "Write on miss ignores data");  
                         r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
-                        m_cpt_ins_tlb_write_et++;
+			m_cpt_dcache_data_write++; 
+                        m_cpt_data_tlb_update_acc++;
+                        m_cost_data_tlb_update_acc_frz++;
 		    }
 		}
@@ -3947,5 +3995,4 @@
             r_dcache_fsm = DCACHE_CC_CHECK;
             r_dcache_fsm_save = r_dcache_fsm;
-            m_cost_data_waste_wait_frz++;
             break;
         }        
@@ -4026,5 +4073,4 @@
             r_dcache_fsm = DCACHE_CC_CHECK;
             r_dcache_fsm_save = r_dcache_fsm;
-            m_cost_data_waste_wait_frz++;
             break;
         }  
@@ -4048,4 +4094,5 @@
                         r_dcache_cleanup_req = true;
                         r_dcache_cleanup_line = victim_index;
+			m_cpt_cc_cleanup_data++;
                         r_dcache_way = way + ((set+1)/m_dcache_sets);
                         r_dcache_set = (set+1) % m_dcache_sets;
@@ -4099,5 +4146,4 @@
             r_dcache_fsm = DCACHE_CC_CHECK;
             r_dcache_fsm_save = r_dcache_fsm;
-            m_cost_data_waste_wait_frz++;
             break;
         }  
@@ -4126,4 +4172,5 @@
 		r_dcache_cleanup_req = r_dcache.inval(dpaddr, &way, &set);
 		r_dcache_cleanup_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
+		m_cpt_cc_cleanup_data++;
 		
 		if ( r_dcache_in_itlb[way*m_dcache_sets+set] || r_dcache_in_dtlb[way*m_dcache_sets+set] ) 
@@ -4156,5 +4203,4 @@
             r_dcache_fsm = DCACHE_CC_CHECK;
             r_dcache_fsm_save = r_dcache_fsm;
-            m_cost_data_waste_wait_frz++;
             break;
         }  
@@ -4168,4 +4214,5 @@
 	    r_dcache_cleanup_req = r_dcache.inval(dpaddr, &way, &set);
 	    r_dcache_cleanup_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
+	    m_cpt_cc_cleanup_data++;
 	    
 	    if ( r_dcache_in_itlb[way*m_dcache_sets+set] || r_dcache_in_dtlb[way*m_dcache_sets+set] ) 
@@ -4210,5 +4257,4 @@
             r_dcache_fsm = DCACHE_CC_CHECK;
             r_dcache_fsm_save = r_dcache_fsm;
-            m_cost_data_waste_wait_frz++;
             break;
         }
@@ -4232,4 +4278,5 @@
                 r_dcache_cleanup_req = true;
                 r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);  
+		m_cpt_cc_cleanup_data++;
                 r_dcache_fsm = DCACHE_IDLE;
                 r_dcache_inval_tlb_rsp = false;
@@ -4243,4 +4290,5 @@
                 r_dcache_cleanup_req = true;
                 r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);  
+		m_cpt_cc_cleanup_data++;
                 r_dcache_fsm = DCACHE_IDLE;
                 r_dcache_inval_rsp = false;
@@ -4262,5 +4310,4 @@
             r_dcache_fsm = DCACHE_CC_CHECK;
             r_dcache_fsm_save = r_dcache_fsm;
-            m_cost_data_waste_wait_frz++;
             break;
         }
@@ -4271,8 +4318,8 @@
             r_dcache_cleanup_req = true;
             r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);  
+	    m_cpt_cc_cleanup_data++;
             r_dcache_inval_tlb_rsp = false;
             r_dcache_inval_rsp = false;
             r_dcache_fsm = DCACHE_IDLE;
-            m_cost_data_tlb_miss_frz++;
             break;
         }
@@ -4284,7 +4331,4 @@
             size_t set = 0;
 
-	    m_cpt_dcache_data_write++;
-            m_cpt_dcache_dir_write++;
-
             // Using tlb entry is in the invalidated cache line  
             if ( r_dcache_inval_rsp )
@@ -4292,4 +4336,5 @@
                 r_dcache_cleanup_req = true;
                 r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);  
+		m_cpt_cc_cleanup_data++;
                 r_dcache_fsm = DCACHE_IDLE;
                 r_dcache_inval_rsp = false;
@@ -4313,4 +4358,5 @@
                 r_dcache_cleanup_req = true; 
                 r_dcache_cleanup_line = victim_index;
+		m_cpt_cc_cleanup_data++;
 		if ( r_dcache_in_itlb[m_dcache_sets*way+set] || r_dcache_in_dtlb[m_dcache_sets*way+set] )
 		{
@@ -4320,5 +4366,6 @@
 		}
 	    }
-
+	    m_cpt_dcache_dir_write++;
+	    m_cpt_dcache_data_write++;
 	    r_dcache.update(r_dcache_paddr_save.read(), way, set, r_dcache_miss_buf);
             r_dcache_fsm = DCACHE_IDLE;
@@ -4336,5 +4383,4 @@
             r_dcache_fsm = DCACHE_CC_CHECK;
             r_dcache_fsm_save = r_dcache_fsm;
-            m_cost_data_waste_wait_frz++;
             break;
         }
@@ -4364,4 +4410,5 @@
 		r_dcache_cleanup_req = r_dcache.inval(r_dcache_paddr_save, &way, &set);
 		r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2);
+		m_cpt_cc_cleanup_data++;
 		
 		if ( r_dcache_in_itlb[way*m_dcache_sets+set] || r_dcache_in_dtlb[way*m_dcache_sets+set] ) 
@@ -4392,4 +4439,5 @@
     {
         m_cost_write_frz++;
+	m_cpt_dcache_data_write++; 
         size_t way = 0;
         size_t set = 0;
@@ -4419,11 +4467,12 @@
         if ( !r_dcache_dirty_save && (r_mmu_mode.read() & DATA_TLB_MASK) )   
         {
+            m_cpt_data_tlb_update_dirty++;
+            m_cost_data_tlb_update_dirty_frz++;	
             if ( dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save) )	// 2M page size, one level page table 
-            {
+            {		    
                 r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
                 r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
                 r_dcache_tlb_ll_dirty_req = true;
-                r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
-                m_cpt_data_tlb_write_dirty++;
+                r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;          
             }
             else
@@ -4435,5 +4484,4 @@
                     r_dcache_tlb_ll_dirty_req = true;
                     r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
-                    m_cpt_data_tlb_write_dirty++;
                 }
                 else
@@ -4457,5 +4505,5 @@
     case DCACHE_WRITE_DIRTY:
     {
-        m_cost_data_tlb_miss_frz++;
+	m_cost_data_tlb_update_dirty_frz++;
 
         // external cache invalidate request
@@ -4464,5 +4512,4 @@
             r_dcache_fsm = DCACHE_CC_CHECK;
             r_dcache_fsm_save = r_dcache_fsm;
-            m_cost_data_waste_wait_frz++;
             break;
         }
@@ -4482,4 +4529,5 @@
 	}
 
+	m_cpt_dcache_data_write++; 
         r_dcache.write(r_dcache_tlb_paddr, r_dcache_pte_update);
         dcache_tlb.setdirty(r_dcache_tlb_way_save, r_dcache_tlb_set_save);
@@ -4502,5 +4550,5 @@
     case DCACHE_ITLB_READ:
     {
-        m_cost_data_waste_wait_frz++;
+       if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++;
 
         // external cache invalidate request
@@ -4509,5 +4557,4 @@
             r_dcache_fsm = DCACHE_CC_CHECK;
             r_dcache_fsm_save = r_dcache_fsm;
-            m_cost_data_waste_wait_frz++;
             break;
         }
@@ -4531,4 +4578,5 @@
                 r_dcache_cleanup_req = true;
                 r_dcache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);  
+		m_cpt_cc_cleanup_data++;
                 r_dcache_fsm = DCACHE_IDLE;
                 r_dcache_inval_rsp = false;
@@ -4543,5 +4591,5 @@
     case DCACHE_ITLB_UPDT:
     {
-        m_cost_data_waste_wait_frz++;
+        if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++;  
 
         // external cache invalidate request
@@ -4550,5 +4598,4 @@
             r_dcache_fsm = DCACHE_CC_CHECK;
             r_dcache_fsm_save = r_dcache_fsm;
-            m_cost_data_waste_wait_frz++;
             break;
         }
@@ -4567,4 +4614,5 @@
                 r_dcache_cleanup_req = true;
                 r_dcache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);  
+		m_cpt_cc_cleanup_data++;
                 r_dcache_fsm = DCACHE_IDLE;
                 r_dcache_inval_rsp = false;
@@ -4588,4 +4636,5 @@
                 r_dcache_cleanup_req = true; 
                 r_dcache_cleanup_line = victim_index;
+		m_cpt_cc_cleanup_data++;
 		if ( r_dcache_in_itlb[m_dcache_sets*way+set] || r_dcache_in_dtlb[m_dcache_sets*way+set] )
 		{
@@ -4600,5 +4649,6 @@
             r_dcache.setinbit(r_icache_paddr_save, r_dcache_in_itlb, true);
             bool itlb_hit_dcache = r_dcache.read(r_icache_paddr_save, &rsp_itlb_miss);	
- 
+            m_cpt_ins_tlb_occup_cache++; 
+
 	    if ( r_itlb_k_read_dcache && itlb_hit_dcache )
 	    {	
@@ -4619,4 +4669,5 @@
     case DCACHE_ITLB_LL_WAIT:
     {
+        if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++;	    
         // external cache invalidate request
         if ( r_tgt_dcache_req )   
@@ -4624,5 +4675,4 @@
             r_dcache_fsm = DCACHE_CC_CHECK;
             r_dcache_fsm_save = r_dcache_fsm;
-            m_cost_data_waste_wait_frz++;
             break;
         }
@@ -4651,5 +4701,4 @@
        		    r_dcache_inval_rsp = false;
        		    r_dcache_fsm = DCACHE_IDLE;
-       		    m_cost_data_tlb_miss_frz++;
        		}
 		else
@@ -4666,4 +4715,5 @@
     case DCACHE_ITLB_SC_WAIT:
     {
+        if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++; 	    
         // external cache invalidate request
         if ( r_tgt_dcache_req )   
@@ -4671,5 +4721,4 @@
             r_dcache_fsm = DCACHE_CC_CHECK;
             r_dcache_fsm_save = r_dcache_fsm;
-            m_cost_data_waste_wait_frz++;
             break;
         }
@@ -4692,5 +4741,4 @@
 	            r_dcache_fsm = DCACHE_IDLE;
 		    if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
-	            m_cost_data_tlb_miss_frz++;
 	        }
 	        else if ( r_dcache_tlb_sc_fail )
@@ -4712,8 +4760,21 @@
     case DCACHE_CC_CHECK:   // read directory in case of invalidate or update request
     {
-        if ( dreq.valid ) m_cost_data_waste_wait_frz++;
-
         m_cpt_dcache_dir_read += m_dcache_ways;
         m_cpt_dcache_data_read += m_dcache_ways;
+
+        /* activity counter */
+        if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) )        
+        {
+            m_cost_data_miss_frz++;
+        }
+        if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) || ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ )        || ( r_dcache_fsm_save == DCACHE_TLB2_READ )        ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT )     ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT )     || 
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT )   || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT )   ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_UPDT )        || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) )
+        {
+            m_cost_data_tlb_miss_frz++;
+        }
 
 	// DCACHE_TLB1_LL_WAIT  DCACHE_TLB1_SC_WAIT  DCACHE_LL_DIRTY_WAIT  DCACHE_WRITE_DIRTY DCACHE_ITLB_LL_WAIT  DCACHE_ITLB_SC_WAIT
@@ -4792,5 +4853,18 @@
     case DCACHE_CC_UPDT:    // update directory and data cache        
     {
-        if ( dreq.valid ) m_cost_data_waste_wait_frz++;
+        /* activity counter */
+        if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) )        
+        {
+            m_cost_data_miss_frz++;
+        }
+        if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) || ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ )        || ( r_dcache_fsm_save == DCACHE_TLB2_READ )        ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT )     ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT )     || 
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT )   || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT )   ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_UPDT )        || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) )
+        {
+            m_cost_data_tlb_miss_frz++;
+        }
 
         m_cpt_dcache_dir_write++;
@@ -4810,5 +4884,18 @@
     case DCACHE_CC_INVAL:   // invalidate a cache line
     {
-        if ( dreq.valid ) m_cost_data_waste_wait_frz++;
+        /* activity counter */
+        if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) )        
+        {
+            m_cost_data_miss_frz++;
+        }
+        if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) || ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ )        || ( r_dcache_fsm_save == DCACHE_TLB2_READ )        ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT )     ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT )     || 
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT )   || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT )   ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_UPDT )        || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) )
+        {
+            m_cost_data_tlb_miss_frz++;
+        }
 
         r_tgt_dcache_rsp = r_dcache.inval(r_tgt_addr.read());
@@ -4820,5 +4907,18 @@
     case DCACHE_CC_NOP:     // no external hit
     {
-        if ( dreq.valid ) m_cost_data_waste_wait_frz++;
+        /* activity counter */
+        if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) )        
+        {
+            m_cost_data_miss_frz++;
+        }
+        if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) || ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ )        || ( r_dcache_fsm_save == DCACHE_TLB2_READ )        ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT )     ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT )     || 
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT )   || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT )   ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_UPDT )        || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) )
+        {
+            m_cost_data_tlb_miss_frz++;
+        }
 
         r_tgt_dcache_req = false;
@@ -4838,5 +4938,18 @@
     case DCACHE_TLB_CC_INVAL:
     {
-        if ( dreq.valid ) m_cost_data_waste_wait_frz++;
+        /* activity counter */
+        if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) )        
+        {
+            m_cost_data_miss_frz++;
+        }
+        if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) || ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ )        || ( r_dcache_fsm_save == DCACHE_TLB2_READ )        ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT )     ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT )     || 
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT )   || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT )   ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_UPDT )        || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) )
+        {
+            m_cost_data_tlb_miss_frz++;
+        }
 
 	if ( r_dcache_itlb_inval_req || r_dcache_dtlb_inval_req ) break;
@@ -4878,5 +4991,5 @@
     case DCACHE_ITLB_CLEANUP:
     {
-        if ( dreq.valid ) m_cost_data_waste_wait_frz++;
+        if ( dreq.valid ) m_cost_data_miss_frz++;
 
         r_dcache.setinbit(((paddr_t)r_dcache_itlb_cleanup_line.read()*m_dcache_words*2), r_dcache_in_itlb, false);
@@ -4973,5 +5086,16 @@
         m_cpt_frz_cycles++;
     }
-
+    if ( dreq.valid && !drsp.valid ) 
+    {
+        m_cpt_dcache_frz_cycles++;
+    }
+    for (size_t way = 0; way < m_dcache_ways; way++ )
+    {    
+        for (size_t set = 0; set < m_dcache_sets; set++ )
+        {
+	    if (r_dcache_in_itlb[way*m_dcache_sets+set] || r_dcache_in_dtlb[way*m_dcache_sets+set])
+		m_cpt_tlb_occup_dcache++;
+	}
+    }
     ////////////////////////////////////////////////////////////////////////////
     //     VCI_CMD FSM 
@@ -5006,8 +5130,10 @@
         {
             r_vci_cmd_fsm = CMD_INS_CLEANUP;
+	    m_cpt_icleanup_transaction++;
         }
         else if (r_dcache_cleanup_req)
         {
             r_vci_cmd_fsm = CMD_DATA_CLEANUP;
+	    m_cpt_dcleanup_transaction++;
         }
         else if (r_dcache_itlb_read_req)           
@@ -5019,10 +5145,10 @@
 	{
 	    r_vci_cmd_fsm = CMD_ITLB_ACC_LL;
-            m_cpt_itlb_write_transaction++; 
+            m_cpt_itlb_ll_transaction++; 
 	}
 	else if (r_dcache_itlb_sc_acc_req)
 	{
 	    r_vci_cmd_fsm = CMD_ITLB_ACC_SC;
-            m_cpt_itlb_write_transaction++; 
+            m_cpt_itlb_sc_transaction++; 
 	}
         else if (r_icache_miss_req) 
@@ -5034,5 +5160,5 @@
         {    
             r_vci_cmd_fsm = CMD_INS_UNC;
-            m_cpt_imiss_transaction++; 
+            m_cpt_icache_unc_transaction++; 
         }  
         else if (r_dcache_tlb_read_req) 
@@ -5044,20 +5170,20 @@
         {  
             r_vci_cmd_fsm = CMD_DTLB_ACC_LL;
-            m_cpt_dtlb_write_transaction++; 
+            m_cpt_dtlb_ll_transaction++; 
         } 
         else if (r_dcache_tlb_sc_acc_req) 
         {  
             r_vci_cmd_fsm = CMD_DTLB_ACC_SC;
-            m_cpt_dtlb_write_transaction++; 
+            m_cpt_dtlb_sc_transaction++; 
         } 
         else if (r_dcache_tlb_ll_dirty_req) 
         {  
             r_vci_cmd_fsm = CMD_DTLB_DIRTY_LL;
-            m_cpt_dtlb_write_transaction++; 
+            m_cpt_dtlb_ll_dirty_transaction++; 
         } 
         else if (r_dcache_tlb_sc_dirty_req) 
         {  
             r_vci_cmd_fsm = CMD_DTLB_DIRTY_SC;
-            m_cpt_dtlb_write_transaction++; 
+            m_cpt_dtlb_sc_dirty_transaction++; 
         } 
         else if (r_dcache_write_req)
@@ -5213,4 +5339,5 @@
 
     case RSP_ITLB_ACC_LL:
+	m_cost_itlb_ll_transaction++;
         if ( ! p_vci_ini_rw.rspval.read() )
             break;
@@ -5232,4 +5359,5 @@
 
     case RSP_ITLB_ACC_SC:
+	m_cost_itlb_sc_transaction++;
         if ( ! p_vci_ini_rw.rspval.read() )
             break;
@@ -5276,5 +5404,5 @@
 
     case RSP_INS_UNC:
-        m_cost_imiss_transaction++;
+        m_cost_icache_unc_transaction++;
         if ( ! p_vci_ini_rw.rspval.read() )
             break;
@@ -5318,4 +5446,5 @@
 
     case RSP_DTLB_ACC_LL:
+	m_cost_dtlb_ll_transaction++; 
         if ( ! p_vci_ini_rw.rspval.read() )
             break;
@@ -5337,4 +5466,5 @@
 
     case RSP_DTLB_ACC_SC:
+	m_cost_dtlb_sc_transaction++;
         if ( ! p_vci_ini_rw.rspval.read() )
             break;
@@ -5357,4 +5487,5 @@
 
     case RSP_DTLB_DIRTY_LL:
+	m_cost_dtlb_ll_dirty_transaction++; 
         if ( ! p_vci_ini_rw.rspval.read() )
             break;
@@ -5376,4 +5507,5 @@
 
     case RSP_DTLB_DIRTY_SC:
+	m_cost_dtlb_sc_dirty_transaction++; 
         if ( ! p_vci_ini_rw.rspval.read() )
             break;
@@ -5457,4 +5589,13 @@
     case RSP_INS_CLEANUP:
     case RSP_DATA_CLEANUP:
+        if ( r_vci_rsp_fsm == RSP_INS_CLEANUP ) 
+        {
+            m_cost_icleanup_transaction++;
+        }
+        else
+        {                                    
+            m_cost_dcleanup_transaction++;
+        }
+
         if ( ! p_vci_ini_c.rspval.read() )
             break;
