Changeset 484


Ignore:
Timestamp:
Aug 6, 2013, 1:36:51 PM (9 years ago)
Author:
devigne
Message:

Fixing deadlock :
L1 cache can be interrupted for coherency processing (UPDT, INVAL, BROADCAST)
only if CC_SEND_FSM is available.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp

    r473 r484  
    10301030
    10311031        // coherence interrupt
    1032         if ( r_cc_receive_icache_req.read() )
     1032        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
    10331033        {
    10341034            r_icache_fsm = ICACHE_CC_CHECK;
     
    12661266
    12671267        // coherence interrupt
    1268         if ( r_cc_receive_icache_req.read() )
     1268        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
    12691269        {
    12701270            r_icache_fsm = ICACHE_CC_CHECK;
     
    13181318
    13191319        // coherence request (from CC_RECEIVE FSM)
    1320         if ( r_cc_receive_icache_req.read() )
     1320        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
    13211321        {
    13221322            r_icache_fsm = ICACHE_CC_CHECK;
     
    15251525
    15261526        // coherence interrupt
    1527         if ( r_cc_receive_icache_req.read() )
     1527        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
    15281528        {
    15291529            r_icache_fsm = ICACHE_CC_CHECK;
     
    16221622
    16231623        // coherence interrupt
    1624         if ( r_cc_receive_icache_req.read() )
     1624        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
    16251625        {
    16261626            r_icache_fsm = ICACHE_CC_CHECK;
     
    17011701
    17021702        // coherence interrupt
    1703         if ( r_cc_receive_icache_req.read() )
     1703        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
    17041704        {
    17051705            r_icache_fsm = ICACHE_CC_CHECK;
     
    17801780
    17811781        // coherence interrupt
    1782         if ( r_cc_receive_icache_req.read() )
     1782        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
    17831783        {
    17841784            r_icache_fsm = ICACHE_CC_CHECK;
     
    18191819        paddr_t  mask  = ~((m_icache_words<<2)-1);
    18201820
     1821        // CLACK handler
     1822        // We switch the directory slot to EMPTY state
     1823        // and reset r_icache_miss_clack if the cleanup ack
     1824        // is matching a pending miss.
     1825        if ( r_icache_clack_req.read() )
     1826        {
     1827
     1828            if ( m_ireq.valid ) m_cost_ins_miss_frz++;
     1829
     1830#ifdef INSTRUMENTATION
     1831m_cpt_icache_dir_write++;
     1832#endif
     1833            r_icache.write_dir( 0,
     1834                                r_icache_clack_way.read(),
     1835                                r_icache_clack_set.read(),
     1836                                CACHE_SLOT_STATE_EMPTY);
     1837
     1838            if ( (r_icache_miss_set.read() == r_icache_clack_set.read()) and
     1839                 (r_icache_miss_way.read() == r_icache_clack_way.read()) )
     1840            {
     1841                r_icache_miss_clack = false;
     1842            }
     1843
     1844            r_icache_clack_req = false;
     1845
     1846            // return to cc_save state
     1847            r_icache_fsm = r_icache_fsm_save.read();
     1848
     1849#if DEBUG_ICACHE
     1850if ( m_debug_activated )
     1851{
     1852    std::cout << "  <PROC " << name()
     1853        << " ICACHE_CC_CHECK>  CC_TYPE_CLACK slot returns to empty state"
     1854        << " set = " << r_icache_clack_set.read()
     1855        << " / way = " << r_icache_clack_way.read() << std::endl;
     1856}
     1857#endif
     1858
     1859            break;
     1860        }
    18211861
    18221862        // Match between MISS address and CC address
     
    18581898        }
    18591899
    1860         // CLACK handler
    1861         // We switch the directory slot to EMPTY state
    1862         // and reset r_icache_miss_clack if the cleanup ack
    1863         // is matching a pending miss.
    1864         if ( r_icache_clack_req.read() )
    1865         {
    1866 
    1867             if ( m_ireq.valid ) m_cost_ins_miss_frz++;
    1868 
    1869 #ifdef INSTRUMENTATION
    1870 m_cpt_icache_dir_write++;
    1871 #endif
    1872             r_icache.write_dir( 0,
    1873                                 r_icache_clack_way.read(),
    1874                                 r_icache_clack_set.read(),
    1875                                 CACHE_SLOT_STATE_EMPTY);
    1876 
    1877             if ( (r_icache_miss_set.read() == r_icache_clack_set.read()) and
    1878                  (r_icache_miss_way.read() == r_icache_clack_way.read()) )
    1879             {
    1880                 r_icache_miss_clack = false;
    1881             }
    1882 
    1883             r_icache_clack_req = false;
    1884 
    1885             // return to cc_save state if no pending CC request
    1886             if ( not r_cc_receive_icache_req.read() )
    1887                 r_icache_fsm = r_icache_fsm_save.read();
    1888 
    1889 #if DEBUG_ICACHE
    1890 if ( m_debug_activated )
    1891 {
    1892     std::cout << "  <PROC " << name()
    1893         << " ICACHE_CC_CHECK>  CC_TYPE_CLACK slot returns to empty state"
    1894         << " set = " << r_icache_clack_set.read()
    1895         << " / way = " << r_icache_clack_way.read() << std::endl;
    1896 }
    1897 #endif
    1898 
    1899             break;
    1900         }
    1901 
    1902         // wait if pending request to CC_SEND. This way if there are pending
    1903         // CLACK they can be treated in this state and then a deadlock
    1904         // situation is avoided
    1905         if ( r_icache_cc_send_req.read() ) break;
     1900        assert ( not r_icache_cc_send_req.read() and "CC_SEND must be available in ICACHE_CC_CHECK");
    19061901
    19071902        // CC request handler
     
    23442339        }
    23452340        // coherence request (from CC_RECEIVE FSM)
    2346         else if ( r_cc_receive_dcache_req.read() )
     2341        else if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
    23472342        {
    23482343            r_dcache_fsm = DCACHE_CC_CHECK;
     
    29562951
    29572952        // coherence request (from CC_RECEIVE FSM)
    2958         if ( r_cc_receive_dcache_req.read() )
     2953        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
    29592954        {
    29602955            r_dcache_fsm = DCACHE_CC_CHECK;
     
    32613256
    32623257        // coherence request (from CC_RECEIVE FSM)
    3263         if ( r_cc_receive_dcache_req.read() )
     3258        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
    32643259        {
    32653260            r_dcache_fsm = DCACHE_CC_CHECK;
     
    35663561
    35673562        // coherence request (from CC_RECEIVE FSM)
    3568         if ( r_cc_receive_dcache_req.read() )
     3563        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
    35693564        {
    35703565            r_dcache_fsm = DCACHE_CC_CHECK;
     
    36453640
    36463641        // coherence request (from CC_RECEIVE FSM)
    3647         if ( r_cc_receive_dcache_req.read() )
     3642        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
    36483643        {
    36493644            r_dcache_fsm = DCACHE_CC_CHECK;
     
    36753670
    36763671        // coherence request (from CC_RECEIVE FSM)
    3677         if ( r_cc_receive_dcache_req.read() )
     3672        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
    36783673        {
    36793674            r_dcache_fsm = DCACHE_CC_CHECK;
     
    37183713
    37193714        // coherence request (from CC_RECEIVE FSM)
    3720         if ( r_cc_receive_dcache_req.read() )
     3715        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
    37213716        {
    37223717            r_dcache_fsm = DCACHE_CC_CHECK;
     
    39873982
    39883983        // coherence request (from CC_RECEIVE FSM)
    3989         if ( r_cc_receive_dcache_req.read() )
     3984        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
    39903985        {
    39913986            r_dcache_fsm = DCACHE_CC_CHECK;
     
    41114106
    41124107        // coherence request (from CC_RECEIVE FSM)
    4113         if ( r_cc_receive_dcache_req.read() )
     4108        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
    41144109        {
    41154110            r_dcache_fsm = DCACHE_CC_CHECK;
     
    42344229
    42354230        // coherence request (from CC_RECEIVE FSM)
    4236         if ( r_cc_receive_dcache_req.read() )
     4231        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
    42374232        {
    42384233            r_dcache_fsm = DCACHE_CC_CHECK;
     
    43164311
    43174312        // coherence request (from CC_RECEIVE FSM)
    4318         if ( r_cc_receive_dcache_req.read() )
     4313        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
    43194314        {
    43204315            r_dcache_fsm = DCACHE_CC_CHECK;
     
    43614356
    43624357        // coherence request (from CC_RECEIVE FSM)
    4363         if ( r_cc_receive_dcache_req.read() )
     4358        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
    43644359        {
    43654360            r_dcache_fsm = DCACHE_CC_CHECK;
     
    44154410
    44164411        // coherence request (from CC_RECEIVE FSM)
    4417         if ( r_cc_receive_dcache_req.read() )
     4412        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
    44184413        {
    44194414            r_dcache_fsm = DCACHE_CC_CHECK;
     
    45154510
    45164511        // coherence request (from CC_RECEIVE FSM)
    4517         if ( r_cc_receive_dcache_req.read() )
     4512        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
    45184513        {
    45194514            r_dcache_fsm = DCACHE_CC_CHECK;
     
    45714566}
    45724567#endif
     4568        // CLACK handler
     4569        // We switch the directory slot to EMPTY state and reset
     4570        // r_dcache_miss_clack if the cleanup ack is matching a pending miss.
     4571        if ( r_dcache_clack_req.read() )
     4572        {
     4573            if ( m_dreq.valid ) m_cost_data_miss_frz++;
     4574
     4575#ifdef INSTRUMENTATION
     4576m_cpt_dcache_dir_write++;
     4577#endif
     4578            r_dcache.write_dir( 0,
     4579                                r_dcache_clack_way.read(),
     4580                                r_dcache_clack_set.read(),
     4581                                CACHE_SLOT_STATE_EMPTY);
     4582
     4583            if ( (r_dcache_miss_set.read() == r_dcache_clack_set.read()) and
     4584                 (r_dcache_miss_way.read() == r_dcache_clack_way.read()) )
     4585            {
     4586                  r_dcache_miss_clack = false;
     4587            }
     4588
     4589            r_dcache_clack_req = false;
     4590
     4591            // return to cc_save state
     4592            r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
     4593
     4594#if DEBUG_DCACHE
     4595if ( m_debug_activated )
     4596{
     4597    std::cout << "  <PROC " << name()
     4598              << " DCACHE_CC_CHECK> CC_TYPE_CLACK Switch slot to EMPTY state"
     4599              << " set = " << r_dcache_clack_set.read()
     4600              << " / way = " << r_dcache_clack_way.read() << std::endl;
     4601}
     4602#endif
     4603            break;
     4604        }
    45734605
    45744606       
     
    46124644        }
    46134645
    4614         // CLACK handler
    4615         // We switch the directory slot to EMPTY state and reset
    4616         // r_dcache_miss_clack if the cleanup ack is matching a pending miss.
    4617         if ( r_dcache_clack_req.read() )
    4618         {
    4619             if ( m_dreq.valid ) m_cost_data_miss_frz++;
    4620 
    4621 #ifdef INSTRUMENTATION
    4622 m_cpt_dcache_dir_write++;
    4623 #endif
    4624             r_dcache.write_dir( 0,
    4625                                 r_dcache_clack_way.read(),
    4626                                 r_dcache_clack_set.read(),
    4627                                 CACHE_SLOT_STATE_EMPTY);
    4628 
    4629             if ( (r_dcache_miss_set.read() == r_dcache_clack_set.read()) and
    4630                  (r_dcache_miss_way.read() == r_dcache_clack_way.read()) )
    4631             {
    4632                   r_dcache_miss_clack = false;
    4633             }
    4634 
    4635             r_dcache_clack_req = false;
    4636 
    4637             // return to cc_save state if no pending CC request
    4638             if ( not r_cc_receive_dcache_req.read() )
    4639             {
    4640                 r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
    4641             }
    4642 
    4643 #if DEBUG_DCACHE
    4644 if ( m_debug_activated )
    4645 {
    4646     std::cout << "  <PROC " << name()
    4647               << " DCACHE_CC_CHECK> CC_TYPE_CLACK Switch slot to EMPTY state"
    4648               << " set = " << r_dcache_clack_set.read()
    4649               << " / way = " << r_dcache_clack_way.read() << std::endl;
    4650 }
    4651 #endif
    4652             break;
    4653         }
    4654 
    4655         // wait if pending request to CC_SEND. This way if there are pending
    4656         // CLACK they can be treated in this state and then a deadlock
    4657         // situation is avoided
    4658         if ( r_dcache_cc_send_req.read() ) break;
     4646
     4647        assert ( not r_dcache_cc_send_req.read() and "CC_SEND must be available in DCACHE_CC_CHECK" );
    46594648
    46604649        // CC request handler
     
    55735562            // flip_flop to check that ?
    55745563            if (not (r_cc_receive_icache_req.read()) and
    5575                 not (r_cc_receive_dcache_req.read()) and 
     5564                not (r_cc_receive_dcache_req.read()) and
    55765565                (p_dspin_m2p.write.read()))
    55775566            {
     
    56135602            uint64_t receive_data = p_dspin_m2p.data.read();
    56145603            // for data INVAL, wait for dcache to take the request
    5615             if (p_dspin_m2p.write.read() and not r_cc_receive_dcache_req.read())
     5604            if (p_dspin_m2p.write.read()           and
     5605                not r_cc_receive_dcache_req.read() )
    56165606            {
    56175607                // request dcache to handle the INVAL
     
    56315621            uint64_t receive_data = p_dspin_m2p.data.read();
    56325622            // for ins INVAL, wait for icache to take the request
    5633             if (p_dspin_m2p.write.read() and not r_cc_receive_icache_req.read())
     5623            if (p_dspin_m2p.write.read()           and
     5624                not r_cc_receive_icache_req.read() )
    56345625            {
    56355626                // request icache to handle the INVAL
     
    56815672            // for data INVAL, wait for dcache to take the request and fifo to
    56825673            // be empty
    5683             if ( r_cc_receive_updt_fifo_be.empty() and 
     5674            if ( r_cc_receive_updt_fifo_be.empty() and
    56845675                 p_dspin_m2p.write.read() )
    56855676            {
     
    57015692            // for ins INVAL, wait for icache to take the request and fifo to be
    57025693            // empty
    5703             if ( r_cc_receive_updt_fifo_be.empty() and 
     5694            if ( r_cc_receive_updt_fifo_be.empty() and
    57045695                 p_dspin_m2p.write.read() )
    57055696            {
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