- Timestamp:
- Aug 9, 2013, 11:00:05 AM (11 years ago)
- File:
-
- 1 edited
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trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r483 r489 25 25 * SOCLIB_LGPL_HEADER_END 26 26 * 27 * Maintainers: alain eric.guthmuller@polytechnique.edu 27 * Maintainers: alain.greiner@lip6.fr 28 * eric.guthmuller@polytechnique.edu 28 29 * cesar.fuguet-tortolero@lip6.fr 29 30 * alexandre.joannou@lip6.fr … … 150 151 MULTI_ACK_UPT_LOCK, 151 152 MULTI_ACK_UPT_CLEAR, 152 MULTI_ACK_WRITE_RSP, 153 MULTI_ACK_CONFIG_ACK 153 MULTI_ACK_WRITE_RSP 154 154 }; 155 155 … … 159 159 CONFIG_IDLE, 160 160 CONFIG_LOOP, 161 CONFIG_WAIT, 161 162 CONFIG_RSP, 162 163 CONFIG_DIR_REQ, 163 164 CONFIG_DIR_ACCESS, 164 CONFIG_ DIR_IVT_LOCK,165 CONFIG_IVT_LOCK, 165 166 CONFIG_BC_SEND, 166 CONFIG_BC_WAIT, 167 CONFIG_INV_SEND, 167 CONFIG_INVAL_SEND, 168 168 CONFIG_HEAP_REQ, 169 169 CONFIG_HEAP_SCAN, 170 170 CONFIG_HEAP_LAST, 171 CONFIG_INV_WAIT 171 CONFIG_TRT_LOCK, 172 CONFIG_TRT_SET, 173 CONFIG_PUT_REQ 172 174 }; 173 175 … … 197 199 WRITE_DIR_REQ, 198 200 WRITE_DIR_LOCK, 199 WRITE_DIR_READ,200 201 WRITE_DIR_HIT, 201 202 WRITE_UPT_LOCK, … … 209 210 WRITE_MISS_TRT_SET, 210 211 WRITE_MISS_XRAM_REQ, 212 WRITE_BC_DIR_READ, 211 213 WRITE_BC_TRT_LOCK, 212 214 WRITE_BC_IVT_LOCK, … … 221 223 { 222 224 IXR_RSP_IDLE, 223 IXR_RSP_ACK,224 225 IXR_RSP_TRT_ERASE, 225 226 IXR_RSP_TRT_READ … … 235 236 XRAM_RSP_DIR_UPDT, 236 237 XRAM_RSP_DIR_RSP, 237 XRAM_RSP_I NVAL_LOCK,238 XRAM_RSP_IVT_LOCK, 238 239 XRAM_RSP_INVAL_WAIT, 239 240 XRAM_RSP_INVAL, … … 253 254 IXR_CMD_CAS_IDLE, 254 255 IXR_CMD_XRAM_IDLE, 255 IXR_CMD_READ, 256 IXR_CMD_WRITE, 257 IXR_CMD_CAS, 258 IXR_CMD_XRAM 256 IXR_CMD_CONFIG_IDLE, 257 IXR_CMD_READ_TRT, 258 IXR_CMD_WRITE_TRT, 259 IXR_CMD_CAS_TRT, 260 IXR_CMD_XRAM_TRT, 261 IXR_CMD_CONFIG_TRT, 262 IXR_CMD_READ_SEND, 263 IXR_CMD_WRITE_SEND, 264 IXR_CMD_CAS_SEND, 265 IXR_CMD_XRAM_SEND, 266 IXR_CMD_CONFIG_SEND 259 267 }; 260 268 … … 302 310 CLEANUP_IVT_CLEAR, 303 311 CLEANUP_WRITE_RSP, 304 CLEANUP_CONFIG_ACK,305 312 CLEANUP_SEND_CLACK 306 313 }; … … 325 332 ALLOC_TRT_CAS, 326 333 ALLOC_TRT_XRAM_RSP, 327 ALLOC_TRT_IXR_RSP 334 ALLOC_TRT_IXR_RSP, 335 ALLOC_TRT_CONFIG, 336 ALLOC_TRT_IXR_CMD 328 337 }; 329 338 … … 386 395 }; 387 396 388 /* Configuration commands */ 389 enum cmd_config_type_e 390 { 391 CMD_CONFIG_INVAL = 0, 392 CMD_CONFIG_SYNC = 1 393 }; 394 395 // debug variables (for each FSM) 397 // debug variables 396 398 bool m_debug; 397 399 bool m_debug_previous_valid; 398 400 size_t m_debug_previous_count; 399 401 bool m_debug_previous_dirty; 400 sc_signal<data_t>* m_debug_previous_data; 401 sc_signal<data_t>* m_debug_data; 402 403 bool m_monitor_ok; 404 addr_t m_monitor_base; 405 addr_t m_monitor_length; 402 data_t * m_debug_previous_data; 403 data_t * m_debug_data; 406 404 407 405 // instrumentation counters … … 531 529 uint32_t m_broadcast_boundaries; 532 530 533 //////////////////////////////////////////////////534 // Registers controlled by the TGT_CMD fsm535 //////////////////////////////////////////////////536 537 sc_signal<int> r_tgt_cmd_fsm;538 539 531 // Fifo between TGT_CMD fsm and READ fsm 540 532 GenericFifo<addr_t> m_cmd_read_addr_fifo; … … 580 572 sc_signal<size_t> r_tgt_cmd_config_cmd; 581 573 574 ////////////////////////////////////////////////// 575 // Registers controlled by the TGT_CMD fsm 576 ////////////////////////////////////////////////// 577 578 sc_signal<int> r_tgt_cmd_fsm; 579 sc_signal<size_t> r_tgt_cmd_srcid; // srcid for response to config 580 sc_signal<size_t> r_tgt_cmd_trdid; // trdid for response to config 581 sc_signal<size_t> r_tgt_cmd_pktid; // pktid for response to config 582 582 583 /////////////////////////////////////////////////////// 583 584 // Registers controlled by the CONFIG fsm 584 585 /////////////////////////////////////////////////////// 585 586 586 sc_signal<int> r_config_fsm; // FSM state 587 sc_signal<bool> r_config_lock; // lock protecting exclusive access 588 sc_signal<int> r_config_cmd; // config request status 589 sc_signal<addr_t> r_config_address; // target buffer physical address 590 sc_signal<size_t> r_config_srcid; // config request srcid 591 sc_signal<size_t> r_config_trdid; // config request trdid 592 sc_signal<size_t> r_config_pktid; // config request pktid 593 sc_signal<size_t> r_config_nlines; // number of lines covering the buffer 594 sc_signal<size_t> r_config_dir_way; // DIR: selected way 595 sc_signal<size_t> r_config_dir_count; // DIR: number of copies 596 sc_signal<bool> r_config_dir_is_cnt; // DIR: counter mode (broadcast required) 597 sc_signal<size_t> r_config_dir_copy_srcid; // DIR: first copy SRCID 598 sc_signal<bool> r_config_dir_copy_inst; // DIR: first copy L1 type 599 sc_signal<size_t> r_config_dir_next_ptr; // DIR: index of next copy in HEAP 600 sc_signal<size_t> r_config_heap_next; // current pointer to scan HEAP 601 602 sc_signal<size_t> r_config_ivt_index; // IVT index 587 sc_signal<int> r_config_fsm; // FSM state 588 sc_signal<bool> r_config_lock; // lock protecting exclusive access 589 sc_signal<int> r_config_cmd; // config request type 590 sc_signal<addr_t> r_config_address; // target buffer physical address 591 sc_signal<size_t> r_config_srcid; // config request srcid 592 sc_signal<size_t> r_config_trdid; // config request trdid 593 sc_signal<size_t> r_config_pktid; // config request pktid 594 sc_signal<size_t> r_config_cmd_lines; // number of lines to be handled 595 sc_signal<size_t> r_config_rsp_lines; // number of lines not completed 596 sc_signal<size_t> r_config_dir_way; // DIR: selected way 597 sc_signal<bool> r_config_dir_lock; // DIR: locked entry 598 sc_signal<size_t> r_config_dir_count; // DIR: number of copies 599 sc_signal<bool> r_config_dir_is_cnt; // DIR: counter mode (broadcast) 600 sc_signal<size_t> r_config_dir_copy_srcid; // DIR: first copy SRCID 601 sc_signal<bool> r_config_dir_copy_inst; // DIR: first copy L1 type 602 sc_signal<size_t> r_config_dir_ptr; // DIR: index of next copy in HEAP 603 sc_signal<size_t> r_config_heap_next; // current pointer to scan HEAP 604 sc_signal<size_t> r_config_trt_index; // selected entry in TRT 605 sc_signal<size_t> r_config_ivt_index; // selected entry in IVT 606 607 // Buffer between CONFIG fsm and IXR_CMD fsm 608 sc_signal<bool> r_config_to_ixr_cmd_req; // valid request 609 sc_signal<size_t> r_config_to_ixr_cmd_index; // TRT index 610 603 611 604 612 // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache) … … 617 625 GenericFifo<size_t> m_config_to_cc_send_srcid_fifo; // fifo for owners srcid 618 626 619 #if L1_MULTI_CACHE620 GenericFifo<size_t> m_config_to_cc_send_cache_id_fifo; // fifo for cache_id621 #endif622 623 627 /////////////////////////////////////////////////////// 624 628 // Registers controlled by the READ fsm 625 629 /////////////////////////////////////////////////////// 626 630 627 sc_signal<int> r_read_fsm; // FSM state 628 sc_signal<size_t> r_read_copy; // Srcid of the first copy 629 sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy 630 sc_signal<bool> r_read_copy_inst; // Type of the first copy 631 sc_signal<tag_t> r_read_tag; // cache line tag (in directory) 632 sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory) 633 sc_signal<bool> r_read_lock; // lock bit (in directory) 634 sc_signal<bool> r_read_dirty; // dirty bit (in directory) 635 sc_signal<size_t> r_read_count; // number of copies 636 sc_signal<size_t> r_read_ptr; // pointer to the heap 637 sc_signal<data_t> * r_read_data; // data (one cache line) 638 sc_signal<size_t> r_read_way; // associative way (in cache) 639 sc_signal<size_t> r_read_trt_index; // Transaction Table index 640 sc_signal<size_t> r_read_next_ptr; // Next entry to point to 641 sc_signal<bool> r_read_last_free; // Last free entry 642 sc_signal<addr_t> r_read_ll_key; // LL key from the llsc_global_table 643 644 // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM) 645 sc_signal<bool> r_read_to_ixr_cmd_req; // valid request 646 sc_signal<addr_t> r_read_to_ixr_cmd_nline; // cache line index 647 sc_signal<size_t> r_read_to_ixr_cmd_trdid; // index in Transaction Table 631 sc_signal<int> r_read_fsm; // FSM state 632 sc_signal<size_t> r_read_copy; // Srcid of the first copy 633 sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy 634 sc_signal<bool> r_read_copy_inst; // Type of the first copy 635 sc_signal<tag_t> r_read_tag; // cache line tag (in directory) 636 sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory) 637 sc_signal<bool> r_read_lock; // lock bit (in directory) 638 sc_signal<bool> r_read_dirty; // dirty bit (in directory) 639 sc_signal<size_t> r_read_count; // number of copies 640 sc_signal<size_t> r_read_ptr; // pointer to the heap 641 sc_signal<data_t> * r_read_data; // data (one cache line) 642 sc_signal<size_t> r_read_way; // associative way (in cache) 643 sc_signal<size_t> r_read_trt_index; // Transaction Table index 644 sc_signal<size_t> r_read_next_ptr; // Next entry to point to 645 sc_signal<bool> r_read_last_free; // Last free entry 646 sc_signal<addr_t> r_read_ll_key; // LL key from llsc_global_table 647 648 // Buffer between READ fsm and IXR_CMD fsm 649 sc_signal<bool> r_read_to_ixr_cmd_req; // valid request 650 sc_signal<size_t> r_read_to_ixr_cmd_index; // TRT index 648 651 649 652 // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache) 650 sc_signal<bool> r_read_to_tgt_rsp_req; // valid request651 sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid652 sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid653 sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid654 sc_signal<data_t> * r_read_to_tgt_rsp_data; // data (one cache line)655 sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response656 sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response657 sc_signal<addr_t> r_read_to_tgt_rsp_ll_key; // LL key from thellsc_global_table653 sc_signal<bool> r_read_to_tgt_rsp_req; // valid request 654 sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid 655 sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid 656 sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid 657 sc_signal<data_t> * r_read_to_tgt_rsp_data; // data (one cache line) 658 sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response 659 sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response 660 sc_signal<addr_t> r_read_to_tgt_rsp_ll_key; // LL key from llsc_global_table 658 661 659 662 /////////////////////////////////////////////////////////////// … … 661 664 /////////////////////////////////////////////////////////////// 662 665 663 sc_signal<int> r_write_fsm; // FSM state664 sc_signal<addr_t> r_write_address; // first word address665 sc_signal<size_t> r_write_word_index; // first word index in line666 sc_signal<size_t> r_write_word_count; // number of words in line667 sc_signal<size_t> r_write_srcid; // transaction srcid668 sc_signal<size_t> r_write_trdid; // transaction trdid669 sc_signal<size_t> r_write_pktid; // transaction pktid670 sc_signal<data_t> * r_write_data; // data (one cache line)671 sc_signal<be_t> * r_write_be; // one byte enable per word672 sc_signal<bool> r_write_byte; // (BE != 0X0) and (BE != 0xF)673 sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory)674 sc_signal<bool> r_write_lock; // lock bit (in directory)675 sc_signal<tag_t> r_write_tag; // cache line tag (in directory)676 sc_signal<size_t> r_write_copy; // first owner of the line677 sc_signal<size_t> r_write_copy_cache; // first owner of the line678 sc_signal<bool> r_write_copy_inst; // is this owner a ICache ?679 sc_signal<size_t> r_write_count; // number of copies680 sc_signal<size_t> r_write_ptr; // pointer to the heap681 sc_signal<size_t> r_write_next_ptr; // next pointer to the heap682 sc_signal<bool> r_write_to_dec; // need to decrement update counter683 sc_signal<size_t> r_write_way; // way of the line684 sc_signal<size_t> r_write_trt_index; // index in Transaction Table685 sc_signal<size_t> r_write_upt_index; // index in Update Table686 sc_signal<bool> r_write_sc_fail; // sc command failed687 sc_signal<bool> r_write_pending_sc; // sc command pending666 sc_signal<int> r_write_fsm; // FSM state 667 sc_signal<addr_t> r_write_address; // first word address 668 sc_signal<size_t> r_write_word_index; // first word index in line 669 sc_signal<size_t> r_write_word_count; // number of words in line 670 sc_signal<size_t> r_write_srcid; // transaction srcid 671 sc_signal<size_t> r_write_trdid; // transaction trdid 672 sc_signal<size_t> r_write_pktid; // transaction pktid 673 sc_signal<data_t> * r_write_data; // data (one cache line) 674 sc_signal<be_t> * r_write_be; // one byte enable per word 675 sc_signal<bool> r_write_byte; // (BE != 0X0) and (BE != 0xF) 676 sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory) 677 sc_signal<bool> r_write_lock; // lock bit (in directory) 678 sc_signal<tag_t> r_write_tag; // cache line tag (in directory) 679 sc_signal<size_t> r_write_copy; // first owner of the line 680 sc_signal<size_t> r_write_copy_cache; // first owner of the line 681 sc_signal<bool> r_write_copy_inst; // is this owner a ICache ? 682 sc_signal<size_t> r_write_count; // number of copies 683 sc_signal<size_t> r_write_ptr; // pointer to the heap 684 sc_signal<size_t> r_write_next_ptr; // next pointer to the heap 685 sc_signal<bool> r_write_to_dec; // need to decrement update counter 686 sc_signal<size_t> r_write_way; // way of the line 687 sc_signal<size_t> r_write_trt_index; // index in Transaction Table 688 sc_signal<size_t> r_write_upt_index; // index in Update Table 689 sc_signal<bool> r_write_sc_fail; // sc command failed 690 sc_signal<bool> r_write_pending_sc; // sc command pending 688 691 689 692 // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1) … … 694 697 sc_signal<bool> r_write_to_tgt_rsp_sc_fail; // sc command failed 695 698 696 // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM) 697 sc_signal<bool> r_write_to_ixr_cmd_req; // valid request 698 sc_signal<bool> r_write_to_ixr_cmd_write; // write request 699 sc_signal<addr_t> r_write_to_ixr_cmd_nline; // cache line index 700 sc_signal<data_t> * r_write_to_ixr_cmd_data; // cache line data 701 sc_signal<size_t> r_write_to_ixr_cmd_trdid; // index in Transaction Table 699 // Buffer between WRITE fsm and IXR_CMD fsm 700 sc_signal<bool> r_write_to_ixr_cmd_req; // valid request 701 sc_signal<bool> r_write_to_ixr_cmd_put; // request type (GET/PUT) 702 sc_signal<size_t> r_write_to_ixr_cmd_index; // TRT index 702 703 703 704 // Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches) … … 713 714 GenericFifo<size_t> m_write_to_cc_send_srcid_fifo; // fifo for srcids 714 715 715 #if L1_MULTI_CACHE716 GenericFifo<size_t> m_write_to_cc_send_cache_id_fifo; // fifo for srcids717 #endif718 719 716 // Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry) 720 717 sc_signal<bool> r_write_to_multi_ack_req; // valid request … … 732 729 sc_signal<addr_t> r_multi_ack_nline; // pending write nline 733 730 734 // signaling completion of multi-inval to CONFIG fsm735 sc_signal<bool> r_multi_ack_to_config_ack;736 737 731 // Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction) 738 732 sc_signal<bool> r_multi_ack_to_tgt_rsp_req; // valid request … … 751 745 sc_signal<addr_t> r_cleanup_nline; // cache line index 752 746 753 #if L1_MULTI_CACHE754 sc_signal<size_t> r_cleanup_pktid; // transaction pktid755 #endif756 747 757 748 sc_signal<copy_t> r_cleanup_copy; // first copy … … 780 771 sc_signal<size_t> r_cleanup_index; // index of the INVAL line (in the UPT) 781 772 782 // signaling completion of broadcast-inval to CONFIG fsm783 sc_signal<bool> r_cleanup_to_config_ack;784 785 773 // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1) 786 774 sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request … … 793 781 /////////////////////////////////////////////////////// 794 782 795 sc_signal<int> r_cas_fsm; // FSM state796 sc_signal<data_t> r_cas_wdata; // write data word797 sc_signal<data_t> * r_cas_rdata; // read data word798 sc_signal<uint32_t> r_cas_lfsr; // lfsr for random introducing799 sc_signal<size_t> r_cas_cpt; // size of command800 sc_signal<copy_t> r_cas_copy; // Srcid of the first copy801 sc_signal<copy_t> r_cas_copy_cache; // Srcid of the first copy802 sc_signal<bool> r_cas_copy_inst; // Type of the first copy803 sc_signal<size_t> r_cas_count; // number of copies804 sc_signal<size_t> r_cas_ptr; // pointer to the heap805 sc_signal<size_t> r_cas_next_ptr; // next pointer to the heap806 sc_signal<bool> r_cas_is_cnt; // is_cnt bit (in directory)807 sc_signal<bool> r_cas_dirty; // dirty bit (in directory)808 sc_signal<size_t> r_cas_way; // way in directory809 sc_signal<size_t> r_cas_set; // set in directory810 sc_signal<data_t> r_cas_tag; // cache line tag (in directory)811 sc_signal<size_t> r_cas_trt_index; // Transaction Table index812 sc_signal<size_t> r_cas_upt_index; // Update Table index813 sc_signal<data_t> * r_cas_data; // cache line data814 815 // Buffer between CAS fsm and IXR_CMD fsm (XRAM write)783 sc_signal<int> r_cas_fsm; // FSM state 784 sc_signal<data_t> r_cas_wdata; // write data word 785 sc_signal<data_t> * r_cas_rdata; // read data word 786 sc_signal<uint32_t> r_cas_lfsr; // lfsr for random introducing 787 sc_signal<size_t> r_cas_cpt; // size of command 788 sc_signal<copy_t> r_cas_copy; // Srcid of the first copy 789 sc_signal<copy_t> r_cas_copy_cache; // Srcid of the first copy 790 sc_signal<bool> r_cas_copy_inst; // Type of the first copy 791 sc_signal<size_t> r_cas_count; // number of copies 792 sc_signal<size_t> r_cas_ptr; // pointer to the heap 793 sc_signal<size_t> r_cas_next_ptr; // next pointer to the heap 794 sc_signal<bool> r_cas_is_cnt; // is_cnt bit (in directory) 795 sc_signal<bool> r_cas_dirty; // dirty bit (in directory) 796 sc_signal<size_t> r_cas_way; // way in directory 797 sc_signal<size_t> r_cas_set; // set in directory 798 sc_signal<data_t> r_cas_tag; // cache line tag (in directory) 799 sc_signal<size_t> r_cas_trt_index; // Transaction Table index 800 sc_signal<size_t> r_cas_upt_index; // Update Table index 801 sc_signal<data_t> * r_cas_data; // cache line data 802 803 // Buffer between CAS fsm and IXR_CMD fsm 816 804 sc_signal<bool> r_cas_to_ixr_cmd_req; // valid request 817 sc_signal<addr_t> r_cas_to_ixr_cmd_nline; // cache line index 818 sc_signal<size_t> r_cas_to_ixr_cmd_trdid; // index in Transaction Table 819 sc_signal<bool> r_cas_to_ixr_cmd_write; // write request 820 sc_signal<data_t> * r_cas_to_ixr_cmd_data; // cache line data 821 805 sc_signal<bool> r_cas_to_ixr_cmd_put; // request type (GET/PUT) 806 sc_signal<size_t> r_cas_to_ixr_cmd_index; // TRT index 822 807 823 808 // Buffer between CAS fsm and TGT_RSP fsm … … 840 825 GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo; // fifo for srcids 841 826 842 #if L1_MULTI_CACHE843 GenericFifo<size_t> m_cas_to_cc_send_cache_id_fifo; // fifo for srcids844 #endif845 846 827 //////////////////////////////////////////////////// 847 828 // Registers controlled by the IXR_RSP fsm 848 829 //////////////////////////////////////////////////// 849 830 850 sc_signal<int> r_ixr_rsp_fsm; // FSM state 851 sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index 852 sc_signal<size_t> r_ixr_rsp_cpt; // word counter 831 sc_signal<int> r_ixr_rsp_fsm; // FSM state 832 sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index 833 sc_signal<size_t> r_ixr_rsp_cpt; // word counter 834 835 // Buffer between IXR_RSP fsm and CONFIG fsm (response from the XRAM) 836 sc_signal<bool> r_ixr_rsp_to_config_ack; // one single bit 853 837 854 838 // Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM) 855 sc_signal<bool> * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready839 sc_signal<bool> * r_ixr_rsp_to_xram_rsp_rok; // one bit per TRT entry 856 840 857 841 //////////////////////////////////////////////////// … … 896 880 GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo; // fifo for srcids 897 881 898 #if L1_MULTI_CACHE 899 GenericFifo<size_t> m_xram_rsp_to_cc_send_cache_id_fifo; // fifo for srcids 900 #endif 901 902 // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write) 882 // Buffer between XRAM_RSP fsm and IXR_CMD fsm 903 883 sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request 904 sc_signal<addr_t> r_xram_rsp_to_ixr_cmd_nline; // cache line index 905 sc_signal<data_t> * r_xram_rsp_to_ixr_cmd_data; // cache line data 906 sc_signal<size_t> r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table 884 sc_signal<size_t> r_xram_rsp_to_ixr_cmd_index; // TRT index 907 885 908 886 //////////////////////////////////////////////////// … … 911 889 912 890 sc_signal<int> r_ixr_cmd_fsm; 913 sc_signal<size_t> r_ixr_cmd_cpt; 891 sc_signal<size_t> r_ixr_cmd_word; // word index for a put 892 sc_signal<size_t> r_ixr_cmd_trdid; // TRT index value 893 sc_signal<addr_t> r_ixr_cmd_address; // address to XRAM 894 sc_signal<data_t> * r_ixr_cmd_wdata; // cache line buffer 895 sc_signal<bool> r_ixr_cmd_get; // transaction type (PUT/GET) 914 896 915 897 ////////////////////////////////////////////////////
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