Ignore:
Timestamp:
Aug 12, 2013, 11:43:13 AM (11 years ago)
Author:
devigne
Message:

generic_tlb : pte flag CC => NCC
vci_cc_vcache_wrapper : Fixing deadlock
(go to CC_CHECK only when CC_SEND is available)
vci_mem_cache : merge modification on llsc.sw(args)

File:
1 edited

Legend:

Unmodified
Added
Removed
  • branches/ODCCP/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp

    r479 r492  
    3636#define DEBUG_CLEANUP             1
    3737#define INSTRUMENTATION       1
    38 #define FETCH_ON_WRITE_ENABLE 1
     38#define FETCH_ON_WRITE_ENABLE 0
    3939#define DEBUG_CMD                 0
    4040
     
    10931093
    10941094        // coherence interrupt
    1095         if ( r_cc_receive_icache_req.read())
     1095        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() )
    10961096        {
    10971097            r_icache_fsm = ICACHE_CC_CHECK;
     
    13301330
    13311331        // coherence interrupt
    1332         if ( r_cc_receive_icache_req.read() )
     1332        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() )
    13331333        {
    13341334            r_icache_fsm = ICACHE_CC_CHECK;
     
    13821382
    13831383        // coherence request (from CC_RECEIVE FSM)
    1384         if ( r_cc_receive_icache_req.read() )
     1384        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() )
    13851385        {
    13861386            r_icache_fsm = ICACHE_CC_CHECK;
     
    15891589
    15901590        // coherence interrupt
    1591         if ( r_cc_receive_icache_req.read() )
     1591        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() )
    15921592        {
    15931593            r_icache_fsm = ICACHE_CC_CHECK;
     
    16861686
    16871687        // coherence interrupt
    1688         if ( r_cc_receive_icache_req.read() )
     1688        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() )
    16891689        {
    16901690            r_icache_fsm = ICACHE_CC_CHECK;
     
    17651765
    17661766        // coherence interrupt
    1767         if ( r_cc_receive_icache_req.read() )
     1767        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() )
    17681768        {
    17691769            r_icache_fsm = ICACHE_CC_CHECK;
     
    18441844
    18451845        // coherence interrupt
    1846         if ( r_cc_receive_icache_req.read() )
     1846        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() )
    18471847        {
    18481848            r_icache_fsm = ICACHE_CC_CHECK;
     
    18831883        paddr_t  mask  = ~((m_icache_words<<2)-1);
    18841884
     1885        // CLACK handler
     1886        // We switch the directory slot to EMPTY state
     1887        // and reset r_icache_miss_clack if the cleanup ack
     1888        // is matching a pending miss.
     1889        if ( r_icache_clack_req.read() )
     1890        {
     1891
     1892            if ( m_ireq.valid ) m_cost_ins_miss_frz++;
     1893
     1894#ifdef INSTRUMENTATION
     1895m_cpt_icache_dir_write++;
     1896#endif
     1897            r_icache.write_dir( 0,
     1898                                r_icache_clack_way.read(),
     1899                                r_icache_clack_set.read(),
     1900                                CACHE_SLOT_STATE_EMPTY);
     1901
     1902            if ( (r_icache_miss_set.read() == r_icache_clack_set.read()) and
     1903                 (r_icache_miss_way.read() == r_icache_clack_way.read()) )
     1904            {
     1905                r_icache_miss_clack = false;
     1906            }
     1907
     1908            r_icache_clack_req = false;
     1909
     1910            // return to cc_save state
     1911            r_icache_fsm = r_icache_fsm_save.read();
     1912
     1913#if DEBUG_ICACHE
     1914if ( m_debug_activated )
     1915{
     1916    std::cout << "  <PROC " << name()
     1917        << " ICACHE_CC_CHECK>  CC_TYPE_CLACK slot returns to empty state"
     1918        << " set = " << r_icache_clack_set.read()
     1919        << " / way = " << r_icache_clack_way.read() << std::endl;
     1920}
     1921#endif
     1922
     1923            break;
     1924        }
    18851925
    18861926        // Match between MISS address and CC address
     
    19221962        }
    19231963
    1924         // CLACK handler
    1925         // We switch the directory slot to EMPTY state
    1926         // and reset r_icache_miss_clack if the cleanup ack
    1927         // is matching a pending miss.
    1928         if ( r_icache_clack_req.read() )
    1929         {
    1930 
    1931             if ( m_ireq.valid ) m_cost_ins_miss_frz++;
    1932 
    1933 #ifdef INSTRUMENTATION
    1934 m_cpt_icache_dir_write++;
    1935 #endif
    1936             r_icache.write_dir( 0,
    1937                                 r_icache_clack_way.read(),
    1938                                 r_icache_clack_set.read(),
    1939                                 CACHE_SLOT_STATE_EMPTY);
    1940 
    1941             if ( (r_icache_miss_set.read() == r_icache_clack_set.read()) and
    1942                  (r_icache_miss_way.read() == r_icache_clack_way.read()) )
    1943             {
    1944                 r_icache_miss_clack = false;
    1945             }
    1946 
    1947             r_icache_clack_req = false;
    1948 
    1949             // return to cc_save state if no pending CC request
    1950             if ( not r_cc_receive_icache_req.read() )
    1951                 r_icache_fsm = r_icache_fsm_save.read();
    1952 
    1953 #if DEBUG_ICACHE
    1954 if ( m_debug_activated )
    1955 {
    1956     std::cout << "  <PROC " << name()
    1957         << " ICACHE_CC_CHECK>  CC_TYPE_CLACK slot returns to empty state"
    1958         << " set = " << r_icache_clack_set.read()
    1959         << " / way = " << r_icache_clack_way.read() << std::endl;
    1960 }
    1961 #endif
    1962 
    1963             break;
    1964         }
    1965 
    1966         // wait if pending request to CC_SEND. This way if there are pending
    1967         // CLACK they can be treated in this state and then a deadlock
    1968         // situation is avoided
    1969         if ( r_icache_cc_send_req.read() ) break;
     1964
     1965        assert ( not r_icache_cc_send_req.read() and "CC_SEND must be available in ICACHE_CC_CHECK");
    19701966
    19711967        // CC request handler
     
    24072403        }
    24082404        // coherence request (from CC_RECEIVE FSM)
    2409         else if ( r_cc_receive_dcache_req.read() )
     2405        else if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
    24102406        {
    24112407            r_dcache_fsm = DCACHE_CC_CHECK;
     
    27622758                                r_dcache_fsm          = DCACHE_MISS_SELECT;
    27632759                               
    2764                                 /*ODCCP*/ // if tlb's flag cc egal 0 that means line is no coherent
    2765                                 bool ncc = ((tlb_flags.cc == 0) and (r_mmu_mode.read() & DATA_TLB_MASK));
     2760                                /*ODCCP*/ // if tlb's flag ncc egal 1 that means line is no coherent
     2761                                bool ncc = ((tlb_flags.ncc == 1) and (r_mmu_mode.read() & DATA_TLB_MASK));
    27662762
    27672763                                if(ncc)
     
    28802876#endif
    28812877                            // check if line is ncc or cc.
    2882                             bool ncc = ((tlb_flags.cc == 0) and (r_mmu_mode.read() & DATA_TLB_MASK));
     2878                            bool ncc = ((tlb_flags.ncc == 1) and (r_mmu_mode.read() & DATA_TLB_MASK));
    28832879
    28842880                            // cleaning llsc buffer if address matching
     
    31113107
    31123108        // coherence request (from CC_RECEIVE FSM)
    3113         if ( r_cc_receive_dcache_req.read() )
     3109        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
    31143110        {
    31153111            r_dcache_fsm = DCACHE_CC_CHECK;
     
    34183414
    34193415        // coherence request (from CC_RECEIVE FSM)
    3420         if ( r_cc_receive_dcache_req.read() )
     3416        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
    34213417        {
    34223418            r_dcache_fsm = DCACHE_CC_CHECK;
     
    37253721
    37263722        // coherence request (from CC_RECEIVE FSM)
    3727         if ( r_cc_receive_dcache_req.read() )
     3723        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
    37283724        {
    37293725            r_dcache_fsm = DCACHE_CC_CHECK;
     
    38043800
    38053801        // coherence request (from CC_RECEIVE FSM)
    3806         if ( r_cc_receive_dcache_req.read() )
     3802        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
    38073803        {
    38083804            r_dcache_fsm = DCACHE_CC_CHECK;
     
    38343830
    38353831        // coherence request (from CC_RECEIVE FSM)
    3836         if ( r_cc_receive_dcache_req.read() )
     3832        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
    38373833        {
    38383834            r_dcache_fsm = DCACHE_CC_CHECK;
     
    38773873
    38783874        // coherence request (from CC_RECEIVE FSM)
    3879         if ( r_cc_receive_dcache_req.read() )
     3875        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
    38803876        {
    38813877            r_dcache_fsm = DCACHE_CC_CHECK;
     
    42854281
    42864282        // coherence request (from CC_RECEIVE FSM)
    4287         if ( r_cc_receive_dcache_req.read() )
     4283        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
    42884284        {
    42894285            r_dcache_fsm = DCACHE_CC_CHECK;
     
    44794475
    44804476        // coherence request (from CC_RECEIVE FSM)
    4481         if ( r_cc_receive_dcache_req.read() )
     4477        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
    44824478        {
    44834479            r_dcache_fsm = DCACHE_CC_CHECK;
     
    46024598
    46034599        // coherence request (from CC_RECEIVE FSM)
    4604         if ( r_cc_receive_dcache_req.read() )
     4600        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
    46054601        {
    46064602            r_dcache_fsm = DCACHE_CC_CHECK;
     
    47164712
    47174713        // coherence request (from CC_RECEIVE FSM)
    4718         if ( r_cc_receive_dcache_req.read() )
     4714        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
    47194715        {
    47204716            r_dcache_fsm = DCACHE_CC_CHECK;
     
    47614757
    47624758        // coherence request (from CC_RECEIVE FSM)
    4763         if ( r_cc_receive_dcache_req.read() )
     4759        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
    47644760        {
    47654761            r_dcache_fsm = DCACHE_CC_CHECK;
     
    48154811
    48164812        // coherence request (from CC_RECEIVE FSM)
    4817         if ( r_cc_receive_dcache_req.read() )
     4813        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
    48184814        {
    48194815            r_dcache_fsm = DCACHE_CC_CHECK;
     
    49154911
    49164912        // coherence request (from CC_RECEIVE FSM)
    4917         if ( r_cc_receive_dcache_req.read() )
     4913        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
    49184914        {
    49194915            r_dcache_fsm = DCACHE_CC_CHECK;
     
    49714967}
    49724968#endif
     4969        // CLACK handler
     4970        // We switch the directory slot to EMPTY state and reset
     4971        // r_dcache_miss_clack if the cleanup ack is matching a pending miss.
     4972        if ( r_dcache_clack_req.read() )
     4973        {
     4974            if ( m_dreq.valid ) m_cost_data_miss_frz++;
     4975
     4976#ifdef INSTRUMENTATION
     4977m_cpt_dcache_dir_write++;
     4978#endif
     4979            r_dcache.write_dir( 0,
     4980                                r_dcache_clack_way.read(),
     4981                                r_dcache_clack_set.read(),
     4982                                CACHE_SLOT_STATE_EMPTY);
     4983            /*STATS DIRTY*/
     4984            for (size_t word = 0; word < m_dcache_words; word++)
     4985            {
     4986                dirty_stats[(r_cc_receive_dcache_way * m_dcache_sets + r_cc_receive_dcache_set) * m_dcache_words + word] = false;
     4987            }
     4988
     4989            if ( (r_dcache_miss_set.read() == r_dcache_clack_set.read()) and
     4990                 (r_dcache_miss_way.read() == r_dcache_clack_way.read()) )
     4991            {
     4992                  r_dcache_miss_clack = false;
     4993            }
     4994
     4995            r_dcache_clack_req = false;
     4996
     4997            // return to cc_save state
     4998            r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
     4999
     5000#if DEBUG_DCACHE
     5001if ( m_debug_activated )
     5002{
     5003    std::cout << "  <PROC " << name()
     5004              << " DCACHE_CC_CHECK> CC_TYPE_CLACK Switch slot to EMPTY state"
     5005              << " set = " << r_dcache_clack_set.read()
     5006              << " / way = " << r_dcache_clack_way.read() << std::endl;
     5007}
     5008#endif
     5009            break;
     5010        }
    49735011
    49745012       
     
    50125050        }
    50135051
    5014         // CLACK handler
    5015         // We switch the directory slot to EMPTY state and reset
    5016         // r_dcache_miss_clack if the cleanup ack is matching a pending miss.
    5017         if ( r_dcache_clack_req.read() )
    5018         {
    5019             if ( m_dreq.valid ) m_cost_data_miss_frz++;
    5020 
    5021 #ifdef INSTRUMENTATION
    5022 m_cpt_dcache_dir_write++;
    5023 #endif
    5024             r_dcache.write_dir( 0,
    5025                                 r_dcache_clack_way.read(),
    5026                                 r_dcache_clack_set.read(),
    5027                                 CACHE_SLOT_STATE_EMPTY);
    5028             /*STATS DIRTY*/
    5029             for (size_t word = 0; word < m_dcache_words; word++)
    5030             {
    5031                 dirty_stats[(r_cc_receive_dcache_way * m_dcache_sets + r_cc_receive_dcache_set) * m_dcache_words + word] = false;
    5032             }
    5033 
    5034             if ( (r_dcache_miss_set.read() == r_dcache_clack_set.read()) and
    5035                  (r_dcache_miss_way.read() == r_dcache_clack_way.read()) )
    5036             {
    5037                   r_dcache_miss_clack = false;
    5038             }
    5039 
    5040             r_dcache_clack_req = false;
    5041 
    5042             // return to cc_save state if no pending CC request
    5043             if ( not r_cc_receive_dcache_req.read() )
    5044             {
    5045                 r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
    5046             }
    5047 
    5048 #if DEBUG_DCACHE
    5049 if ( m_debug_activated )
    5050 {
    5051     std::cout << "  <PROC " << name()
    5052               << " DCACHE_CC_CHECK> CC_TYPE_CLACK Switch slot to EMPTY state"
    5053               << " set = " << r_dcache_clack_set.read()
    5054               << " / way = " << r_dcache_clack_way.read() << std::endl;
    5055 }
    5056 #endif
    5057             break;
    5058         }
    5059 
    5060         // wait if pending request to CC_SEND. This way if there are pending
    5061         // CLACK they can be treated in this state and then a deadlock
    5062         // situation is avoided
    5063         if ( r_dcache_cc_send_req.read() ) break;
     5052
     5053        assert ( not r_dcache_cc_send_req.read() and "CC_SEND must be available in DCACHE_CC_CHECK");
    50645054
    50655055        // CC request handler
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