- Timestamp:
- Aug 20, 2013, 2:13:08 PM (11 years ago)
- Location:
- branches/ODCCP/modules/vci_mem_cache
- Files:
-
- 2 edited
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branches/ODCCP/modules/vci_mem_cache
- Property svn:mergeinfo changed
/trunk/modules/vci_mem_cache merged: 481-483,489,491
- Property svn:mergeinfo changed
-
branches/ODCCP/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r479 r494 25 25 * SOCLIB_LGPL_HEADER_END 26 26 * 27 * Maintainers: alain eric.guthmuller@polytechnique.edu 27 * Maintainers: alain.greiner@lip6.fr 28 * eric.guthmuller@polytechnique.edu 28 29 * cesar.fuguet-tortolero@lip6.fr 29 30 * alexandre.joannou@lip6.fr … … 150 151 MULTI_ACK_UPT_LOCK, 151 152 MULTI_ACK_UPT_CLEAR, 152 MULTI_ACK_WRITE_RSP, 153 MULTI_ACK_CONFIG_ACK 153 MULTI_ACK_WRITE_RSP 154 154 }; 155 155 … … 159 159 CONFIG_IDLE, 160 160 CONFIG_LOOP, 161 CONFIG_WAIT, 161 162 CONFIG_RSP, 162 163 CONFIG_DIR_REQ, 163 164 CONFIG_DIR_ACCESS, 164 CONFIG_ DIR_IVT_LOCK,165 CONFIG_IVT_LOCK, 165 166 CONFIG_BC_SEND, 166 CONFIG_BC_WAIT, 167 CONFIG_INV_SEND, 167 CONFIG_INVAL_SEND, 168 168 CONFIG_HEAP_REQ, 169 169 CONFIG_HEAP_SCAN, 170 170 CONFIG_HEAP_LAST, 171 CONFIG_INV_WAIT 171 CONFIG_TRT_LOCK, 172 CONFIG_TRT_SET, 173 CONFIG_PUT_REQ 172 174 }; 173 175 … … 197 199 WRITE_DIR_REQ, 198 200 WRITE_DIR_LOCK, 199 WRITE_DIR_READ,200 201 WRITE_DIR_HIT, 201 202 WRITE_UPT_LOCK, … … 209 210 WRITE_MISS_TRT_SET, 210 211 WRITE_MISS_XRAM_REQ, 212 WRITE_BC_DIR_READ, 211 213 WRITE_BC_TRT_LOCK, 212 214 WRITE_BC_IVT_LOCK, … … 235 237 XRAM_RSP_DIR_UPDT, 236 238 XRAM_RSP_DIR_RSP, 237 XRAM_RSP_I NVAL_LOCK,239 XRAM_RSP_IVT_LOCK, 238 240 XRAM_RSP_INVAL_WAIT, 239 241 XRAM_RSP_INVAL, … … 254 256 IXR_CMD_XRAM_IDLE, 255 257 IXR_CMD_CLEANUP_IDLE, 256 IXR_CMD_TRT_LOCK, 257 IXR_CMD_READ, 258 IXR_CMD_WRITE, 259 IXR_CMD_CAS, 260 IXR_CMD_XRAM, 261 IXR_CMD_CLEANUP_DATA 258 IXR_CMD_CONFIG_IDLE, 259 IXR_CMD_READ_TRT, 260 IXR_CMD_WRITE_TRT, 261 IXR_CMD_CAS_TRT, 262 IXR_CMD_XRAM_TRT, 263 IXR_CMD_CLEANUP_TRT, 264 IXR_CMD_CONFIG_TRT, 265 IXR_CMD_READ_SEND, 266 IXR_CMD_WRITE_SEND, 267 IXR_CMD_CAS_SEND, 268 IXR_CMD_XRAM_SEND, 269 IXR_CMD_CLEANUP_DATA_SEND, 270 IXR_CMD_CONFIG_SEND 262 271 }; 263 272 … … 306 315 CLEANUP_IVT_CLEAR, 307 316 CLEANUP_WRITE_RSP, 308 CLEANUP_CONFIG_ACK,309 317 CLEANUP_IXR_REQ, 310 318 CLEANUP_WAIT, … … 333 341 ALLOC_TRT_IXR_RSP, 334 342 ALLOC_TRT_CLEANUP, 335 ALLOC_TRT_IXR_CMD 343 ALLOC_TRT_IXR_CMD, 344 ALLOC_TRT_CONFIG 336 345 }; 337 346 … … 394 403 }; 395 404 396 /* Configuration commands */ 397 enum cmd_config_type_e 398 { 399 CMD_CONFIG_INVAL = 0, 400 CMD_CONFIG_SYNC = 1 401 }; 402 403 // debug variables (for each FSM) 405 // debug variables 404 406 bool m_debug; 405 407 bool m_debug_previous_valid; 406 408 size_t m_debug_previous_count; 407 409 bool m_debug_previous_dirty; 408 sc_signal<data_t>* m_debug_previous_data; 409 sc_signal<data_t>* m_debug_data; 410 411 bool m_monitor_ok; 412 addr_t m_monitor_base; 413 addr_t m_monitor_length; 410 data_t * m_debug_previous_data; 411 data_t * m_debug_data; 414 412 415 413 // instrumentation counters … … 619 617 uint32_t m_broadcast_boundaries; 620 618 621 //////////////////////////////////////////////////622 // Registers controlled by the TGT_CMD fsm623 //////////////////////////////////////////////////624 625 sc_signal<int> r_tgt_cmd_fsm;626 627 619 // Fifo between TGT_CMD fsm and READ fsm 628 620 GenericFifo<addr_t> m_cmd_read_addr_fifo; … … 668 660 sc_signal<size_t> r_tgt_cmd_config_cmd; 669 661 662 ////////////////////////////////////////////////// 663 // Registers controlled by the TGT_CMD fsm 664 ////////////////////////////////////////////////// 665 666 sc_signal<int> r_tgt_cmd_fsm; 667 sc_signal<size_t> r_tgt_cmd_srcid; // srcid for response to config 668 sc_signal<size_t> r_tgt_cmd_trdid; // trdid for response to config 669 sc_signal<size_t> r_tgt_cmd_pktid; // pktid for response to config 670 670 671 /////////////////////////////////////////////////////// 671 672 // Registers controlled by the CONFIG fsm 672 673 /////////////////////////////////////////////////////// 673 674 674 sc_signal<int> r_config_fsm; // FSM state 675 sc_signal<bool> r_config_lock; // lock protecting exclusive access 676 sc_signal<int> r_config_cmd; // config request status 677 sc_signal<addr_t> r_config_address; // target buffer physical address 678 sc_signal<size_t> r_config_srcid; // config request srcid 679 sc_signal<size_t> r_config_trdid; // config request trdid 680 sc_signal<size_t> r_config_pktid; // config request pktid 681 sc_signal<size_t> r_config_nlines; // number of lines covering the buffer 682 sc_signal<size_t> r_config_dir_way; // DIR: selected way 683 sc_signal<size_t> r_config_dir_count; // DIR: number of copies 684 sc_signal<bool> r_config_dir_is_cnt; // DIR: counter mode (broadcast required) 685 sc_signal<size_t> r_config_dir_copy_srcid; // DIR: first copy SRCID 686 sc_signal<bool> r_config_dir_copy_inst; // DIR: first copy L1 type 687 sc_signal<size_t> r_config_dir_next_ptr; // DIR: index of next copy in HEAP 688 sc_signal<size_t> r_config_heap_next; // current pointer to scan HEAP 689 690 sc_signal<size_t> r_config_ivt_index; // IVT index 675 sc_signal<int> r_config_fsm; // FSM state 676 sc_signal<bool> r_config_lock; // lock protecting exclusive access 677 sc_signal<int> r_config_cmd; // config request type 678 sc_signal<addr_t> r_config_address; // target buffer physical address 679 sc_signal<size_t> r_config_srcid; // config request srcid 680 sc_signal<size_t> r_config_trdid; // config request trdid 681 sc_signal<size_t> r_config_pktid; // config request pktid 682 sc_signal<size_t> r_config_cmd_lines; // number of lines to be handled 683 sc_signal<size_t> r_config_rsp_lines; // number of lines not completed 684 sc_signal<size_t> r_config_dir_way; // DIR: selected way 685 sc_signal<bool> r_config_dir_lock; // DIR: locked entry 686 sc_signal<size_t> r_config_dir_count; // DIR: number of copies 687 sc_signal<bool> r_config_dir_is_cnt; // DIR: counter mode (broadcast) 688 sc_signal<size_t> r_config_dir_copy_srcid; // DIR: first copy SRCID 689 sc_signal<bool> r_config_dir_copy_inst; // DIR: first copy L1 type 690 sc_signal<size_t> r_config_dir_ptr; // DIR: index of next copy in HEAP 691 sc_signal<size_t> r_config_heap_next; // current pointer to scan HEAP 692 sc_signal<size_t> r_config_trt_index; // selected entry in TRT 693 sc_signal<size_t> r_config_ivt_index; // selected entry in IVT 694 695 // Buffer between CONFIG fsm and IXR_CMD fsm 696 sc_signal<bool> r_config_to_ixr_cmd_req; // valid request 697 sc_signal<size_t> r_config_to_ixr_cmd_index; // TRT index 698 691 699 692 700 // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache) … … 705 713 GenericFifo<size_t> m_config_to_cc_send_srcid_fifo; // fifo for owners srcid 706 714 707 #if L1_MULTI_CACHE708 GenericFifo<size_t> m_config_to_cc_send_cache_id_fifo; // fifo for cache_id709 #endif710 711 715 /////////////////////////////////////////////////////// 712 716 // Registers controlled by the READ fsm 713 717 /////////////////////////////////////////////////////// 714 718 715 sc_signal<int> r_read_fsm; // FSM state 716 sc_signal<size_t> r_read_copy; // Srcid of the first copy 717 sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy 718 sc_signal<bool> r_read_copy_inst; // Type of the first copy 719 sc_signal<tag_t> r_read_tag; // cache line tag (in directory) 720 sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory) 721 sc_signal<bool> r_read_lock; // lock bit (in directory) 722 sc_signal<bool> r_read_dirty; // dirty bit (in directory) 723 sc_signal<size_t> r_read_count; // number of copies 724 sc_signal<size_t> r_read_ptr; // pointer to the heap 725 sc_signal<data_t> * r_read_data; // data (one cache line) 726 sc_signal<size_t> r_read_way; // associative way (in cache) 727 sc_signal<size_t> r_read_trt_index; // Transaction Table index 728 sc_signal<size_t> r_read_next_ptr; // Next entry to point to 729 sc_signal<bool> r_read_last_free; // Last free entry 730 sc_signal<addr_t> r_read_ll_key; // LL key from the llsc_global_table 731 732 // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM) 733 sc_signal<bool> r_read_to_ixr_cmd_req; // valid request 734 sc_signal<addr_t> r_read_to_ixr_cmd_nline; // cache line index 735 sc_signal<size_t> r_read_to_ixr_cmd_trdid; // index in Transaction Table 719 sc_signal<int> r_read_fsm; // FSM state 720 sc_signal<size_t> r_read_copy; // Srcid of the first copy 721 sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy 722 sc_signal<bool> r_read_copy_inst; // Type of the first copy 723 sc_signal<tag_t> r_read_tag; // cache line tag (in directory) 724 sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory) 725 sc_signal<bool> r_read_lock; // lock bit (in directory) 726 sc_signal<bool> r_read_dirty; // dirty bit (in directory) 727 sc_signal<size_t> r_read_count; // number of copies 728 sc_signal<size_t> r_read_ptr; // pointer to the heap 729 sc_signal<data_t> * r_read_data; // data (one cache line) 730 sc_signal<size_t> r_read_way; // associative way (in cache) 731 sc_signal<size_t> r_read_trt_index; // Transaction Table index 732 sc_signal<size_t> r_read_next_ptr; // Next entry to point to 733 sc_signal<bool> r_read_last_free; // Last free entry 734 sc_signal<addr_t> r_read_ll_key; // LL key from llsc_global_table 735 736 // Buffer between READ fsm and IXR_CMD fsm 737 sc_signal<bool> r_read_to_ixr_cmd_req; // valid request 738 sc_signal<size_t> r_read_to_ixr_cmd_index; // TRT index 736 739 737 740 // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache) 738 sc_signal<bool> r_read_to_tgt_rsp_req; // valid request739 sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid740 sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid741 sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid742 sc_signal<data_t> * r_read_to_tgt_rsp_data; // data (one cache line)743 sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response744 sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response745 sc_signal<addr_t> r_read_to_tgt_rsp_ll_key; // LL key from thellsc_global_table741 sc_signal<bool> r_read_to_tgt_rsp_req; // valid request 742 sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid 743 sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid 744 sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid 745 sc_signal<data_t> * r_read_to_tgt_rsp_data; // data (one cache line) 746 sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response 747 sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response 748 sc_signal<addr_t> r_read_to_tgt_rsp_ll_key; // LL key from llsc_global_table 746 749 747 750 /////////////////////////////////////////////////////////////// … … 749 752 /////////////////////////////////////////////////////////////// 750 753 751 sc_signal<int> r_write_fsm; // FSM state752 sc_signal<addr_t> r_write_address; // first word address753 sc_signal<size_t> r_write_word_index; // first word index in line754 sc_signal<size_t> r_write_word_count; // number of words in line755 sc_signal<size_t> r_write_srcid; // transaction srcid756 sc_signal<size_t> r_write_trdid; // transaction trdid757 sc_signal<size_t> r_write_pktid; // transaction pktid758 sc_signal<data_t> * r_write_data; // data (one cache line)759 sc_signal<be_t> * r_write_be; // one byte enable per word760 sc_signal<bool> r_write_byte; // (BE != 0X0) and (BE != 0xF)761 sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory)762 sc_signal<bool> r_write_lock; // lock bit (in directory)763 sc_signal<tag_t> r_write_tag; // cache line tag (in directory)764 sc_signal<size_t> r_write_copy; // first owner of the line765 sc_signal<size_t> r_write_copy_cache; // first owner of the line766 sc_signal<bool> r_write_copy_inst; // is this owner a ICache ?767 sc_signal<size_t> r_write_count; // number of copies768 sc_signal<size_t> r_write_ptr; // pointer to the heap769 sc_signal<size_t> r_write_next_ptr; // next pointer to the heap770 sc_signal<bool> r_write_to_dec; // need to decrement update counter771 sc_signal<size_t> r_write_way; // way of the line772 sc_signal<size_t> r_write_trt_index; // index in Transaction Table773 sc_signal<size_t> r_write_upt_index; // index in Update Table774 sc_signal<bool> r_write_sc_fail; // sc command failed775 sc_signal<bool> r_write_pending_sc; // sc command pending754 sc_signal<int> r_write_fsm; // FSM state 755 sc_signal<addr_t> r_write_address; // first word address 756 sc_signal<size_t> r_write_word_index; // first word index in line 757 sc_signal<size_t> r_write_word_count; // number of words in line 758 sc_signal<size_t> r_write_srcid; // transaction srcid 759 sc_signal<size_t> r_write_trdid; // transaction trdid 760 sc_signal<size_t> r_write_pktid; // transaction pktid 761 sc_signal<data_t> * r_write_data; // data (one cache line) 762 sc_signal<be_t> * r_write_be; // one byte enable per word 763 sc_signal<bool> r_write_byte; // (BE != 0X0) and (BE != 0xF) 764 sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory) 765 sc_signal<bool> r_write_lock; // lock bit (in directory) 766 sc_signal<tag_t> r_write_tag; // cache line tag (in directory) 767 sc_signal<size_t> r_write_copy; // first owner of the line 768 sc_signal<size_t> r_write_copy_cache; // first owner of the line 769 sc_signal<bool> r_write_copy_inst; // is this owner a ICache ? 770 sc_signal<size_t> r_write_count; // number of copies 771 sc_signal<size_t> r_write_ptr; // pointer to the heap 772 sc_signal<size_t> r_write_next_ptr; // next pointer to the heap 773 sc_signal<bool> r_write_to_dec; // need to decrement update counter 774 sc_signal<size_t> r_write_way; // way of the line 775 sc_signal<size_t> r_write_trt_index; // index in Transaction Table 776 sc_signal<size_t> r_write_upt_index; // index in Update Table 777 sc_signal<bool> r_write_sc_fail; // sc command failed 778 sc_signal<bool> r_write_pending_sc; // sc command pending 776 779 777 780 // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1) … … 782 785 sc_signal<bool> r_write_to_tgt_rsp_sc_fail; // sc command failed 783 786 784 // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM) 785 sc_signal<bool> r_write_to_ixr_cmd_req; // valid request 786 sc_signal<bool> r_write_to_ixr_cmd_write; // write request 787 sc_signal<addr_t> r_write_to_ixr_cmd_nline; // cache line index 788 sc_signal<data_t> * r_write_to_ixr_cmd_data; // cache line data 789 sc_signal<size_t> r_write_to_ixr_cmd_trdid; // index in Transaction Table 787 // Buffer between WRITE fsm and IXR_CMD fsm 788 sc_signal<bool> r_write_to_ixr_cmd_req; // valid request 789 sc_signal<bool> r_write_to_ixr_cmd_put; // request type (GET/PUT) 790 sc_signal<size_t> r_write_to_ixr_cmd_index; // TRT index 790 791 791 792 // Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches) … … 801 802 GenericFifo<size_t> m_write_to_cc_send_srcid_fifo; // fifo for srcids 802 803 803 #if L1_MULTI_CACHE804 GenericFifo<size_t> m_write_to_cc_send_cache_id_fifo; // fifo for srcids805 #endif806 807 804 // Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry) 808 805 sc_signal<bool> r_write_to_multi_ack_req; // valid request … … 820 817 sc_signal<addr_t> r_multi_ack_nline; // pending write nline 821 818 822 // signaling completion of multi-inval to CONFIG fsm823 sc_signal<bool> r_multi_ack_to_config_ack;824 825 819 // Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction) 826 820 sc_signal<bool> r_multi_ack_to_tgt_rsp_req; // valid request … … 839 833 sc_signal<addr_t> r_cleanup_nline; // cache line index 840 834 841 #if L1_MULTI_CACHE842 sc_signal<size_t> r_cleanup_pktid; // transaction pktid843 #endif844 835 845 836 sc_signal<copy_t> r_cleanup_copy; // first copy … … 868 859 sc_signal<size_t> r_cleanup_index; // index of the INVAL line (in the UPT) 869 860 870 // signaling completion of broadcast-inval to CONFIG fsm871 sc_signal<bool> r_cleanup_to_config_ack;872 873 861 // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1) 874 862 sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request … … 881 869 /////////////////////////////////////////////////////// 882 870 883 sc_signal<int> r_cas_fsm; // FSM state884 sc_signal<data_t> r_cas_wdata; // write data word885 sc_signal<data_t> * r_cas_rdata; // read data word886 sc_signal<uint32_t> r_cas_lfsr; // lfsr for random introducing887 sc_signal<size_t> r_cas_cpt; // size of command888 sc_signal<copy_t> r_cas_copy; // Srcid of the first copy889 sc_signal<copy_t> r_cas_copy_cache; // Srcid of the first copy890 sc_signal<bool> r_cas_copy_inst; // Type of the first copy891 sc_signal<size_t> r_cas_count; // number of copies892 sc_signal<size_t> r_cas_ptr; // pointer to the heap893 sc_signal<size_t> r_cas_next_ptr; // next pointer to the heap894 sc_signal<bool> r_cas_is_cnt; // is_cnt bit (in directory)895 sc_signal<bool> r_cas_dirty; // dirty bit (in directory)896 sc_signal<size_t> r_cas_way; // way in directory897 sc_signal<size_t> r_cas_set; // set in directory898 sc_signal<data_t> r_cas_tag; // cache line tag (in directory)899 sc_signal<size_t> r_cas_trt_index; // Transaction Table index900 sc_signal<size_t> r_cas_upt_index; // Update Table index901 sc_signal<data_t> * r_cas_data; // cache line data902 903 // Buffer between CAS fsm and IXR_CMD fsm (XRAM write)871 sc_signal<int> r_cas_fsm; // FSM state 872 sc_signal<data_t> r_cas_wdata; // write data word 873 sc_signal<data_t> * r_cas_rdata; // read data word 874 sc_signal<uint32_t> r_cas_lfsr; // lfsr for random introducing 875 sc_signal<size_t> r_cas_cpt; // size of command 876 sc_signal<copy_t> r_cas_copy; // Srcid of the first copy 877 sc_signal<copy_t> r_cas_copy_cache; // Srcid of the first copy 878 sc_signal<bool> r_cas_copy_inst; // Type of the first copy 879 sc_signal<size_t> r_cas_count; // number of copies 880 sc_signal<size_t> r_cas_ptr; // pointer to the heap 881 sc_signal<size_t> r_cas_next_ptr; // next pointer to the heap 882 sc_signal<bool> r_cas_is_cnt; // is_cnt bit (in directory) 883 sc_signal<bool> r_cas_dirty; // dirty bit (in directory) 884 sc_signal<size_t> r_cas_way; // way in directory 885 sc_signal<size_t> r_cas_set; // set in directory 886 sc_signal<data_t> r_cas_tag; // cache line tag (in directory) 887 sc_signal<size_t> r_cas_trt_index; // Transaction Table index 888 sc_signal<size_t> r_cas_upt_index; // Update Table index 889 sc_signal<data_t> * r_cas_data; // cache line data 890 891 // Buffer between CAS fsm and IXR_CMD fsm 904 892 sc_signal<bool> r_cas_to_ixr_cmd_req; // valid request 905 sc_signal<addr_t> r_cas_to_ixr_cmd_nline; // cache line index 906 sc_signal<size_t> r_cas_to_ixr_cmd_trdid; // index in Transaction Table 907 sc_signal<bool> r_cas_to_ixr_cmd_write; // write request 908 sc_signal<data_t> * r_cas_to_ixr_cmd_data; // cache line data 909 893 sc_signal<bool> r_cas_to_ixr_cmd_put; // request type (GET/PUT) 894 sc_signal<size_t> r_cas_to_ixr_cmd_index; // TRT index 910 895 911 896 // Buffer between CAS fsm and TGT_RSP fsm … … 928 913 GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo; // fifo for srcids 929 914 930 #if L1_MULTI_CACHE931 GenericFifo<size_t> m_cas_to_cc_send_cache_id_fifo; // fifo for srcids932 #endif933 934 915 //////////////////////////////////////////////////// 935 916 // Registers controlled by the IXR_RSP fsm 936 917 //////////////////////////////////////////////////// 937 918 938 sc_signal<int> r_ixr_rsp_fsm; // FSM state 939 sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index 940 sc_signal<size_t> r_ixr_rsp_cpt; // word counter 919 sc_signal<int> r_ixr_rsp_fsm; // FSM state 920 sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index 921 sc_signal<size_t> r_ixr_rsp_cpt; // word counter 922 923 // Buffer between IXR_RSP fsm and CONFIG fsm (response from the XRAM) 924 sc_signal<bool> r_ixr_rsp_to_config_ack; // one single bit 941 925 942 926 // Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM) 943 sc_signal<bool> * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready927 sc_signal<bool> * r_ixr_rsp_to_xram_rsp_rok; // one bit per TRT entry 944 928 sc_signal<bool> * r_ixr_rsp_to_xram_rsp_no_coherent; // A xram response is ready and no coherent (ODCCP) 945 929 … … 986 970 GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo; // fifo for srcids 987 971 988 #if L1_MULTI_CACHE 989 GenericFifo<size_t> m_xram_rsp_to_cc_send_cache_id_fifo; // fifo for srcids 990 #endif 991 992 // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write) 972 // Buffer between XRAM_RSP fsm and IXR_CMD fsm 993 973 sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request 994 sc_signal<addr_t> r_xram_rsp_to_ixr_cmd_nline; // cache line index 995 sc_signal<data_t> * r_xram_rsp_to_ixr_cmd_data; // cache line data 996 sc_signal<size_t> r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table 974 sc_signal<size_t> r_xram_rsp_to_ixr_cmd_index; // TRT index 997 975 998 976 //////////////////////////////////////////////////// … … 1001 979 1002 980 sc_signal<int> r_ixr_cmd_fsm; 1003 sc_signal<size_t> r_ixr_cmd_cpt; 981 sc_signal<size_t> r_ixr_cmd_word; // word index for a put 982 sc_signal<size_t> r_ixr_cmd_trdid; // TRT index value 983 sc_signal<addr_t> r_ixr_cmd_address; // address to XRAM 984 sc_signal<data_t> * r_ixr_cmd_wdata; // cache line buffer 985 sc_signal<bool> r_ixr_cmd_get; // transaction type (PUT/GET) 1004 986 1005 987 //////////////////////////////////////////////////// … … 1076 1058 sc_signal<uint32_t> r_cleanup_to_ixr_cmd_srcid; 1077 1059 sc_signal<bool> r_cleanup_to_ixr_cmd_l1_dirty_ncc; // this cleanup was dirty in L1 1078 sc_signal<uint32_t> r_cleanup_to_ixr_cmd_ trdid;1060 sc_signal<uint32_t> r_cleanup_to_ixr_cmd_index; 1079 1061 sc_signal<uint32_t> r_cleanup_to_ixr_cmd_pktid; 1080 1062 sc_signal<addr_t> r_cleanup_to_ixr_cmd_nline;
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