- Timestamp:
- Aug 22, 2013, 6:45:38 PM (11 years ago)
- Location:
- branches/RWT/modules/vci_mem_cache/caba/source/include
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branches/RWT/modules/vci_mem_cache/caba/source/include
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/branches/ODCCP/modules/vci_mem_cache/caba/source/include merged eligible /branches/v5/modules/vci_mem_cache/caba/source/include 441-467
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branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
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/branches/ODCCP/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h merged eligible /trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h merged eligible /branches/v5/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h 441-467
r477 r495 25 25 * SOCLIB_LGPL_HEADER_END 26 26 * 27 * Maintainers: alain eric.guthmuller@polytechnique.edu 27 * Maintainers: alain.greiner@lip6.fr 28 * eric.guthmuller@polytechnique.edu 28 29 * cesar.fuguet-tortolero@lip6.fr 29 30 * alexandre.joannou@lip6.fr … … 154 155 MULTI_ACK_UPT_LOCK, 155 156 MULTI_ACK_UPT_CLEAR, 156 MULTI_ACK_WRITE_RSP, 157 MULTI_ACK_CONFIG_ACK 157 MULTI_ACK_WRITE_RSP 158 158 }; 159 159 … … 163 163 CONFIG_IDLE, 164 164 CONFIG_LOOP, 165 CONFIG_WAIT, 165 166 CONFIG_RSP, 166 167 CONFIG_DIR_REQ, 167 168 CONFIG_DIR_ACCESS, 168 CONFIG_ DIR_IVT_LOCK,169 CONFIG_IVT_LOCK, 169 170 CONFIG_BC_SEND, 170 CONFIG_BC_WAIT, 171 CONFIG_INV_SEND, 171 CONFIG_INVAL_SEND, 172 172 CONFIG_HEAP_REQ, 173 173 CONFIG_HEAP_SCAN, 174 174 CONFIG_HEAP_LAST, 175 CONFIG_INV_WAIT 175 CONFIG_TRT_LOCK, 176 CONFIG_TRT_SET, 177 CONFIG_PUT_REQ 176 178 }; 177 179 … … 204 206 WRITE_DIR_LOCK, 205 207 WRITE_IVT_LOCK_HIT_WB, 206 WRITE_DIR_READ,207 208 WRITE_DIR_HIT, 208 209 WRITE_UPT_LOCK, … … 217 218 WRITE_MISS_TRT_SET, 218 219 WRITE_MISS_XRAM_REQ, 220 WRITE_BC_DIR_READ, 219 221 WRITE_BC_TRT_LOCK, 220 222 WRITE_BC_IVT_LOCK, … … 243 245 XRAM_RSP_DIR_UPDT, 244 246 XRAM_RSP_DIR_RSP, 245 XRAM_RSP_I NVAL_LOCK,247 XRAM_RSP_IVT_LOCK, 246 248 XRAM_RSP_INVAL_WAIT, 247 249 XRAM_RSP_INVAL, … … 262 264 IXR_CMD_XRAM_IDLE, 263 265 IXR_CMD_CLEANUP_IDLE, 264 IXR_CMD_READ, 265 IXR_CMD_WRITE, 266 IXR_CMD_CAS, 267 IXR_CMD_XRAM, 268 IXR_CMD_CLEANUP_DATA 266 IXR_CMD_CONFIG_IDLE, 267 IXR_CMD_READ_TRT, 268 IXR_CMD_WRITE_TRT, 269 IXR_CMD_CAS_TRT, 270 IXR_CMD_XRAM_TRT, 271 IXR_CMD_CLEANUP_TRT, 272 IXR_CMD_CONFIG_TRT, 273 IXR_CMD_READ_SEND, 274 IXR_CMD_WRITE_SEND, 275 IXR_CMD_CAS_SEND, 276 IXR_CMD_XRAM_SEND, 277 IXR_CMD_CLEANUP_DATA_SEND, 278 IXR_CMD_CONFIG_SEND 269 279 }; 270 280 … … 318 328 CLEANUP_IXR_REQ, 319 329 CLEANUP_WAIT, 320 CLEANUP_CONFIG_ACK,321 330 CLEANUP_SEND_CLACK 322 331 }; … … 342 351 ALLOC_TRT_XRAM_RSP, 343 352 ALLOC_TRT_IXR_RSP, 344 ALLOC_TRT_CLEANUP 353 ALLOC_TRT_CLEANUP, 354 ALLOC_TRT_IXR_CMD, 355 ALLOC_TRT_CONFIG 345 356 }; 346 357 … … 404 415 }; 405 416 406 /* Configuration commands */ 407 enum cmd_config_type_e 408 { 409 CMD_CONFIG_INVAL = 0, 410 CMD_CONFIG_SYNC = 1 411 }; 412 413 // debug variables (for each FSM) 417 // debug variables 414 418 bool m_debug; 415 419 bool m_debug_previous_valid; 416 420 size_t m_debug_previous_count; 417 421 bool m_debug_previous_dirty; 418 sc_signal<data_t>* m_debug_previous_data; 419 sc_signal<data_t>* m_debug_data; 420 421 bool m_monitor_ok; 422 addr_t m_monitor_base; 423 addr_t m_monitor_length; 422 data_t * m_debug_previous_data; 423 data_t * m_debug_data; 424 424 425 425 // instrumentation counters … … 644 644 uint32_t m_broadcast_boundaries; 645 645 646 //////////////////////////////////////////////////647 // Registers controlled by the TGT_CMD fsm648 //////////////////////////////////////////////////649 650 sc_signal<int> r_tgt_cmd_fsm;651 652 646 // Fifo between TGT_CMD fsm and READ fsm 653 647 GenericFifo<addr_t> m_cmd_read_addr_fifo; … … 693 687 sc_signal<size_t> r_tgt_cmd_config_cmd; 694 688 689 ////////////////////////////////////////////////// 690 // Registers controlled by the TGT_CMD fsm 691 ////////////////////////////////////////////////// 692 693 sc_signal<int> r_tgt_cmd_fsm; 694 sc_signal<size_t> r_tgt_cmd_srcid; // srcid for response to config 695 sc_signal<size_t> r_tgt_cmd_trdid; // trdid for response to config 696 sc_signal<size_t> r_tgt_cmd_pktid; // pktid for response to config 697 695 698 /////////////////////////////////////////////////////// 696 699 // Registers controlled by the CONFIG fsm 697 700 /////////////////////////////////////////////////////// 698 701 699 sc_signal<int> r_config_fsm; // FSM state 700 sc_signal<bool> r_config_lock; // lock protecting exclusive access 701 sc_signal<int> r_config_cmd; // config request status 702 sc_signal<addr_t> r_config_address; // target buffer physical address 703 sc_signal<size_t> r_config_srcid; // config request srcid 704 sc_signal<size_t> r_config_trdid; // config request trdid 705 sc_signal<size_t> r_config_pktid; // config request pktid 706 sc_signal<size_t> r_config_nlines; // number of lines covering the buffer 707 sc_signal<size_t> r_config_dir_way; // DIR: selected way 708 sc_signal<size_t> r_config_dir_count; // DIR: number of copies 709 sc_signal<bool> r_config_dir_is_cnt; // DIR: counter mode (broadcast required) 710 sc_signal<size_t> r_config_dir_copy_srcid; // DIR: first copy SRCID 711 sc_signal<bool> r_config_dir_copy_inst; // DIR: first copy L1 type 712 sc_signal<size_t> r_config_dir_next_ptr; // DIR: index of next copy in HEAP 713 sc_signal<size_t> r_config_heap_next; // current pointer to scan HEAP 714 715 sc_signal<size_t> r_config_ivt_index; // IVT index 702 sc_signal<int> r_config_fsm; // FSM state 703 sc_signal<bool> r_config_lock; // lock protecting exclusive access 704 sc_signal<int> r_config_cmd; // config request type 705 sc_signal<addr_t> r_config_address; // target buffer physical address 706 sc_signal<size_t> r_config_srcid; // config request srcid 707 sc_signal<size_t> r_config_trdid; // config request trdid 708 sc_signal<size_t> r_config_pktid; // config request pktid 709 sc_signal<size_t> r_config_cmd_lines; // number of lines to be handled 710 sc_signal<size_t> r_config_rsp_lines; // number of lines not completed 711 sc_signal<size_t> r_config_dir_way; // DIR: selected way 712 sc_signal<bool> r_config_dir_lock; // DIR: locked entry 713 sc_signal<size_t> r_config_dir_count; // DIR: number of copies 714 sc_signal<bool> r_config_dir_is_cnt; // DIR: counter mode (broadcast) 715 sc_signal<size_t> r_config_dir_copy_srcid; // DIR: first copy SRCID 716 sc_signal<bool> r_config_dir_copy_inst; // DIR: first copy L1 type 717 sc_signal<size_t> r_config_dir_ptr; // DIR: index of next copy in HEAP 718 sc_signal<size_t> r_config_heap_next; // current pointer to scan HEAP 719 sc_signal<size_t> r_config_trt_index; // selected entry in TRT 720 sc_signal<size_t> r_config_ivt_index; // selected entry in IVT 721 722 // Buffer between CONFIG fsm and IXR_CMD fsm 723 sc_signal<bool> r_config_to_ixr_cmd_req; // valid request 724 sc_signal<size_t> r_config_to_ixr_cmd_index; // TRT index 725 716 726 717 727 // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache) … … 730 740 GenericFifo<size_t> m_config_to_cc_send_srcid_fifo; // fifo for owners srcid 731 741 732 #if L1_MULTI_CACHE733 GenericFifo<size_t> m_config_to_cc_send_cache_id_fifo; // fifo for cache_id734 #endif735 736 742 /////////////////////////////////////////////////////// 737 743 // Registers controlled by the READ fsm 738 744 /////////////////////////////////////////////////////// 739 745 740 sc_signal<int> r_read_fsm; // FSM state 741 sc_signal<size_t> r_read_copy; // Srcid of the first copy 742 sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy 743 sc_signal<bool> r_read_copy_inst; // Type of the first copy 744 sc_signal<tag_t> r_read_tag; // cache line tag (in directory) 745 sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory) 746 sc_signal<bool> r_read_lock; // lock bit (in directory) 747 sc_signal<bool> r_read_dirty; // dirty bit (in directory) 748 sc_signal<size_t> r_read_count; // number of copies 749 sc_signal<size_t> r_read_ptr; // pointer to the heap 750 sc_signal<data_t> * r_read_data; // data (one cache line) 751 sc_signal<size_t> r_read_way; // associative way (in cache) 752 sc_signal<size_t> r_read_trt_index; // Transaction Table index 753 sc_signal<size_t> r_read_next_ptr; // Next entry to point to 754 sc_signal<bool> r_read_last_free; // Last free entry 755 sc_signal<addr_t> r_read_ll_key; // LL key from the llsc_global_table 756 757 // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM) 758 sc_signal<bool> r_read_to_ixr_cmd_req; // valid request 759 sc_signal<addr_t> r_read_to_ixr_cmd_nline; // cache line index 760 sc_signal<size_t> r_read_to_ixr_cmd_trdid; // index in Transaction Table 746 sc_signal<int> r_read_fsm; // FSM state 747 sc_signal<size_t> r_read_copy; // Srcid of the first copy 748 sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy 749 sc_signal<bool> r_read_copy_inst; // Type of the first copy 750 sc_signal<tag_t> r_read_tag; // cache line tag (in directory) 751 sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory) 752 sc_signal<bool> r_read_lock; // lock bit (in directory) 753 sc_signal<bool> r_read_dirty; // dirty bit (in directory) 754 sc_signal<size_t> r_read_count; // number of copies 755 sc_signal<size_t> r_read_ptr; // pointer to the heap 756 sc_signal<data_t> * r_read_data; // data (one cache line) 757 sc_signal<size_t> r_read_way; // associative way (in cache) 758 sc_signal<size_t> r_read_trt_index; // Transaction Table index 759 sc_signal<size_t> r_read_next_ptr; // Next entry to point to 760 sc_signal<bool> r_read_last_free; // Last free entry 761 sc_signal<addr_t> r_read_ll_key; // LL key from llsc_global_table 762 763 // Buffer between READ fsm and IXR_CMD fsm 764 sc_signal<bool> r_read_to_ixr_cmd_req; // valid request 765 sc_signal<size_t> r_read_to_ixr_cmd_index; // TRT index 761 766 762 767 // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache) 763 sc_signal<bool> r_read_to_tgt_rsp_req; // valid request764 sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid765 sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid766 sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid767 sc_signal<data_t> * r_read_to_tgt_rsp_data; // data (one cache line)768 sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response769 sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response770 sc_signal<addr_t> r_read_to_tgt_rsp_ll_key; // LL key from thellsc_global_table768 sc_signal<bool> r_read_to_tgt_rsp_req; // valid request 769 sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid 770 sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid 771 sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid 772 sc_signal<data_t> * r_read_to_tgt_rsp_data; // data (one cache line) 773 sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response 774 sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response 775 sc_signal<addr_t> r_read_to_tgt_rsp_ll_key; // LL key from llsc_global_table 771 776 772 777 //RWT: Buffer between READ fsm and CC_SEND fsm (send inval) … … 795 800 /////////////////////////////////////////////////////////////// 796 801 797 sc_signal<int> r_write_fsm; // FSM state798 sc_signal<addr_t> r_write_address; // first word address799 sc_signal<size_t> r_write_word_index; // first word index in line800 sc_signal<size_t> r_write_word_count; // number of words in line801 sc_signal<size_t> r_write_srcid; // transaction srcid802 sc_signal<size_t> r_write_trdid; // transaction trdid803 sc_signal<size_t> r_write_pktid; // transaction pktid804 sc_signal<data_t> * r_write_data; // data (one cache line)805 sc_signal<be_t> * r_write_be; // one byte enable per word806 sc_signal<bool> r_write_byte; // (BE != 0X0) and (BE != 0xF)807 sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory)808 sc_signal<bool> r_write_lock; // lock bit (in directory)809 sc_signal<tag_t> r_write_tag; // cache line tag (in directory)810 sc_signal<size_t> r_write_copy; // first owner of the line811 sc_signal<size_t> r_write_copy_cache; // first owner of the line812 sc_signal<bool> r_write_copy_inst; // is this owner a ICache ?813 sc_signal<size_t> r_write_count; // number of copies814 sc_signal<size_t> r_write_ptr; // pointer to the heap815 sc_signal<size_t> r_write_next_ptr; // next pointer to the heap816 sc_signal<bool> r_write_to_dec; // need to decrement update counter817 sc_signal<size_t> r_write_way; // way of the line818 sc_signal<size_t> r_write_trt_index; // index in Transaction Table819 sc_signal<size_t> r_write_upt_index; // index in Update Table820 sc_signal<bool> r_write_sc_fail; // sc command failed821 sc_signal<bool> r_write_pending_sc; // sc command pending802 sc_signal<int> r_write_fsm; // FSM state 803 sc_signal<addr_t> r_write_address; // first word address 804 sc_signal<size_t> r_write_word_index; // first word index in line 805 sc_signal<size_t> r_write_word_count; // number of words in line 806 sc_signal<size_t> r_write_srcid; // transaction srcid 807 sc_signal<size_t> r_write_trdid; // transaction trdid 808 sc_signal<size_t> r_write_pktid; // transaction pktid 809 sc_signal<data_t> * r_write_data; // data (one cache line) 810 sc_signal<be_t> * r_write_be; // one byte enable per word 811 sc_signal<bool> r_write_byte; // (BE != 0X0) and (BE != 0xF) 812 sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory) 813 sc_signal<bool> r_write_lock; // lock bit (in directory) 814 sc_signal<tag_t> r_write_tag; // cache line tag (in directory) 815 sc_signal<size_t> r_write_copy; // first owner of the line 816 sc_signal<size_t> r_write_copy_cache; // first owner of the line 817 sc_signal<bool> r_write_copy_inst; // is this owner a ICache ? 818 sc_signal<size_t> r_write_count; // number of copies 819 sc_signal<size_t> r_write_ptr; // pointer to the heap 820 sc_signal<size_t> r_write_next_ptr; // next pointer to the heap 821 sc_signal<bool> r_write_to_dec; // need to decrement update counter 822 sc_signal<size_t> r_write_way; // way of the line 823 sc_signal<size_t> r_write_trt_index; // index in Transaction Table 824 sc_signal<size_t> r_write_upt_index; // index in Update Table 825 sc_signal<bool> r_write_sc_fail; // sc command failed 826 sc_signal<bool> r_write_pending_sc; // sc command pending 822 827 823 828 // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1) … … 828 833 sc_signal<bool> r_write_to_tgt_rsp_sc_fail; // sc command failed 829 834 830 // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM) 831 sc_signal<bool> r_write_to_ixr_cmd_req; // valid request 832 sc_signal<bool> r_write_to_ixr_cmd_write; // write request 833 sc_signal<addr_t> r_write_to_ixr_cmd_nline; // cache line index 834 sc_signal<data_t> * r_write_to_ixr_cmd_data; // cache line data 835 sc_signal<size_t> r_write_to_ixr_cmd_trdid; // index in Transaction Table 835 // Buffer between WRITE fsm and IXR_CMD fsm 836 sc_signal<bool> r_write_to_ixr_cmd_req; // valid request 837 sc_signal<bool> r_write_to_ixr_cmd_put; // request type (GET/PUT) 838 sc_signal<size_t> r_write_to_ixr_cmd_index; // TRT index 836 839 837 840 // Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches) … … 847 850 GenericFifo<size_t> m_write_to_cc_send_srcid_fifo; // fifo for srcids 848 851 849 #if L1_MULTI_CACHE850 GenericFifo<size_t> m_write_to_cc_send_cache_id_fifo; // fifo for srcids851 #endif852 853 852 // Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry) 854 853 sc_signal<bool> r_write_to_multi_ack_req; // valid request … … 878 877 sc_signal<addr_t> r_multi_ack_nline; // pending write nline 879 878 880 // signaling completion of multi-inval to CONFIG fsm881 sc_signal<bool> r_multi_ack_to_config_ack;882 883 879 // Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction) 884 880 sc_signal<bool> r_multi_ack_to_tgt_rsp_req; // valid request … … 897 893 sc_signal<addr_t> r_cleanup_nline; // cache line index 898 894 899 #if L1_MULTI_CACHE900 sc_signal<size_t> r_cleanup_pktid; // transaction pktid901 #endif902 895 903 896 sc_signal<copy_t> r_cleanup_copy; // first copy … … 926 919 sc_signal<size_t> r_cleanup_index; // index of the INVAL line (in the UPT) 927 920 928 // signaling completion of broadcast-inval to CONFIG fsm929 sc_signal<bool> r_cleanup_to_config_ack;930 931 921 // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1) 932 922 sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request … … 950 940 /////////////////////////////////////////////////////// 951 941 952 sc_signal<int> r_cas_fsm; // FSM state953 sc_signal<data_t> r_cas_wdata; // write data word954 sc_signal<data_t> * r_cas_rdata; // read data word955 sc_signal<uint32_t> r_cas_lfsr; // lfsr for random introducing956 sc_signal<size_t> r_cas_cpt; // size of command957 sc_signal<copy_t> r_cas_copy; // Srcid of the first copy958 sc_signal<copy_t> r_cas_copy_cache; // Srcid of the first copy959 sc_signal<bool> r_cas_copy_inst; // Type of the first copy960 sc_signal<size_t> r_cas_count; // number of copies961 sc_signal<size_t> r_cas_ptr; // pointer to the heap962 sc_signal<size_t> r_cas_next_ptr; // next pointer to the heap963 sc_signal<bool> r_cas_is_cnt; // is_cnt bit (in directory)964 sc_signal<bool> r_cas_dirty; // dirty bit (in directory)965 sc_signal<size_t> r_cas_way; // way in directory966 sc_signal<size_t> r_cas_set; // set in directory967 sc_signal<data_t> r_cas_tag; // cache line tag (in directory)968 sc_signal<size_t> r_cas_trt_index; // Transaction Table index969 sc_signal<size_t> r_cas_upt_index; // Update Table index970 sc_signal<data_t> * r_cas_data; // cache line data942 sc_signal<int> r_cas_fsm; // FSM state 943 sc_signal<data_t> r_cas_wdata; // write data word 944 sc_signal<data_t> * r_cas_rdata; // read data word 945 sc_signal<uint32_t> r_cas_lfsr; // lfsr for random introducing 946 sc_signal<size_t> r_cas_cpt; // size of command 947 sc_signal<copy_t> r_cas_copy; // Srcid of the first copy 948 sc_signal<copy_t> r_cas_copy_cache; // Srcid of the first copy 949 sc_signal<bool> r_cas_copy_inst; // Type of the first copy 950 sc_signal<size_t> r_cas_count; // number of copies 951 sc_signal<size_t> r_cas_ptr; // pointer to the heap 952 sc_signal<size_t> r_cas_next_ptr; // next pointer to the heap 953 sc_signal<bool> r_cas_is_cnt; // is_cnt bit (in directory) 954 sc_signal<bool> r_cas_dirty; // dirty bit (in directory) 955 sc_signal<size_t> r_cas_way; // way in directory 956 sc_signal<size_t> r_cas_set; // set in directory 957 sc_signal<data_t> r_cas_tag; // cache line tag (in directory) 958 sc_signal<size_t> r_cas_trt_index; // Transaction Table index 959 sc_signal<size_t> r_cas_upt_index; // Update Table index 960 sc_signal<data_t> * r_cas_data; // cache line data 971 961 972 962 sc_signal<bool> r_cas_coherent; … … 974 964 // Buffer between CAS fsm and IXR_CMD fsm (XRAM write) 975 965 sc_signal<bool> r_cas_to_ixr_cmd_req; // valid request 976 sc_signal<addr_t> r_cas_to_ixr_cmd_nline; // cache line index 977 sc_signal<size_t> r_cas_to_ixr_cmd_trdid; // index in Transaction Table 978 sc_signal<bool> r_cas_to_ixr_cmd_write; // write request 979 sc_signal<data_t> * r_cas_to_ixr_cmd_data; // cache line data 980 966 sc_signal<bool> r_cas_to_ixr_cmd_put; // request type (GET/PUT) 967 sc_signal<size_t> r_cas_to_ixr_cmd_index; // TRT index 981 968 982 969 // Buffer between CAS fsm and TGT_RSP fsm … … 999 986 GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo; // fifo for srcids 1000 987 1001 #if L1_MULTI_CACHE1002 GenericFifo<size_t> m_cas_to_cc_send_cache_id_fifo; // fifo for srcids1003 #endif1004 1005 988 //////////////////////////////////////////////////// 1006 989 // Registers controlled by the IXR_RSP fsm 1007 990 //////////////////////////////////////////////////// 1008 991 1009 sc_signal<int> r_ixr_rsp_fsm; // FSM state 1010 sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index 1011 sc_signal<size_t> r_ixr_rsp_cpt; // word counter 992 sc_signal<int> r_ixr_rsp_fsm; // FSM state 993 sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index 994 sc_signal<size_t> r_ixr_rsp_cpt; // word counter 995 996 // Buffer between IXR_RSP fsm and CONFIG fsm (response from the XRAM) 997 sc_signal<bool> r_ixr_rsp_to_config_ack; // one single bit 1012 998 1013 999 // Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM) 1014 sc_signal<bool> * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready1000 sc_signal<bool> * r_ixr_rsp_to_xram_rsp_rok; // one bit per TRT entry 1015 1001 1016 1002 //////////////////////////////////////////////////// … … 1055 1041 GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo; // fifo for srcids 1056 1042 1057 #if L1_MULTI_CACHE 1058 GenericFifo<size_t> m_xram_rsp_to_cc_send_cache_id_fifo; // fifo for srcids 1059 #endif 1060 1061 // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write) 1043 // Buffer between XRAM_RSP fsm and IXR_CMD fsm 1062 1044 sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request 1063 sc_signal<addr_t> r_xram_rsp_to_ixr_cmd_nline; // cache line index 1064 sc_signal<data_t> * r_xram_rsp_to_ixr_cmd_data; // cache line data 1065 sc_signal<size_t> r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table 1045 sc_signal<size_t> r_xram_rsp_to_ixr_cmd_index; // TRT index 1066 1046 1067 1047 //RWT … … 1073 1053 1074 1054 sc_signal<int> r_ixr_cmd_fsm; 1075 sc_signal<size_t> r_ixr_cmd_cpt; 1055 sc_signal<size_t> r_ixr_cmd_word; // word index for a put 1056 sc_signal<size_t> r_ixr_cmd_trdid; // TRT index value 1057 sc_signal<addr_t> r_ixr_cmd_address; // address to XRAM 1058 sc_signal<data_t> * r_ixr_cmd_wdata; // cache line buffer 1059 sc_signal<bool> r_ixr_cmd_get; // transaction type (PUT/GET) 1076 1060 1077 1061 //////////////////////////////////////////////////// … … 1149 1133 sc_signal<data_t> *r_cleanup_to_ixr_cmd_data; 1150 1134 sc_signal<uint32_t> r_cleanup_to_ixr_cmd_srcid; 1151 sc_signal<uint32_t> r_cleanup_to_ixr_cmd_ trdid;1135 sc_signal<uint32_t> r_cleanup_to_ixr_cmd_index; 1152 1136 sc_signal<uint32_t> r_cleanup_to_ixr_cmd_pktid; 1153 1137 sc_signal<addr_t> r_cleanup_to_ixr_cmd_nline; -
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