Index: branches/RWT/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
===================================================================
--- branches/RWT/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp	(revision 477)
+++ branches/RWT/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp	(revision 495)
@@ -45,5 +45,5 @@
 #define DEBUG_MEMC_WRITE     1 // detailed trace of WRITE FSM
 #define DEBUG_MEMC_CAS       1 // detailed trace of CAS FSM
-#define DEBUG_MEMC_IXR_CMD   1 // detailed trace of IXR_RSP FSM
+#define DEBUG_MEMC_IXR_CMD   1 // detailed trace of IXR_CMD FSM
 #define DEBUG_MEMC_IXR_RSP   1 // detailed trace of IXR_RSP FSM
 #define DEBUG_MEMC_XRAM_RSP  1 // detailed trace of XRAM_RSP FSM
@@ -129,5 +129,4 @@
   "MULTI_ACK_UPT_CLEAR",
   "MULTI_ACK_WRITE_RSP",
-  "MULTI_ACK_CONFIG_ACK"
 };
 const char *config_fsm_str[] =
@@ -135,15 +134,17 @@
   "CONFIG_IDLE",
   "CONFIG_LOOP",
+  "CONFIG_WAIT"
   "CONFIG_RSP",
   "CONFIG_DIR_REQ",
   "CONFIG_DIR_ACCESS",
-  "CONFIG_DIR_IVT_LOCK",
+  "CONFIG_IVT_LOCK",
   "CONFIG_BC_SEND",
-  "CONFIG_BC_WAIT",
-  "CONFIG_INV_SEND",
+  "CONFIG_INVAL_SEND"
   "CONFIG_HEAP_REQ",
   "CONFIG_HEAP_SCAN",
   "CONFIG_HEAP_LAST",
-  "CONFIG_INV_WAIT"
+  "CONFIG_TRT_LOCK",
+  "CONFIG_TRT_SET",
+  "CONFIG_PUT_REQ"
 };
 const char *read_fsm_str[] =
@@ -172,5 +173,4 @@
   "WRITE_DIR_LOCK",
   "WRITE_IVT_LOCK_HIT_WB",
-  "WRITE_DIR_READ",
   "WRITE_DIR_HIT",
   "WRITE_UPT_LOCK",
@@ -185,4 +185,5 @@
   "WRITE_MISS_TRT_SET",
   "WRITE_MISS_XRAM_REQ",
+  "WRITE_BC_DIR_READ",
   "WRITE_BC_TRT_LOCK",
   "WRITE_BC_IVT_LOCK",
@@ -207,5 +208,5 @@
   "XRAM_RSP_DIR_UPDT",
   "XRAM_RSP_DIR_RSP",
-  "XRAM_RSP_INVAL_LOCK",
+  "XRAM_RSP_IVT_LOCK",
   "XRAM_RSP_INVAL_WAIT",
   "XRAM_RSP_INVAL",
@@ -224,9 +225,17 @@
   "IXR_CMD_XRAM_IDLE",
   "IXR_CMD_CLEANUP_IDLE",
-  "IXR_CMD_READ",
-  "IXR_CMD_WRITE",
-  "IXR_CMD_CAS",
-  "IXR_CMD_XRAM",
-  "IXR_CMD_CLEANUP_DATA"
+  "IXR_CMD_CONFIG_IDLE",
+  "IXR_CMD_READ_TRT",
+  "IXR_CMD_WRITE_TRT",
+  "IXR_CMD_CAS_TRT",
+  "IXR_CMD_XRAM_TRT",
+  "IXR_CMD_CLEANUP_TRT",
+  "IXR_CMD_CONFIG_TRT",
+  "IXR_CMD_READ_SEND",
+  "IXR_CMD_WRITE_SEND",
+  "IXR_CMD_CAS_SEND",
+  "IXR_CMD_XRAM_SEND",
+  "IXR_CMD_CLEANUP_DATA_SEND",
+  "IXR_CMD_CONFIG_SEND"
 };
 const char *cas_fsm_str[] =
@@ -276,5 +285,4 @@
   "CLEANUP_IXR_REQ",
   "CLEANUP_WAIT",
-  "CLEANUP_CONFIG_ACK",
   "CLEANUP_SEND_CLACK"
 };
@@ -297,4 +305,6 @@
   "ALLOC_TRT_IXR_RSP",
   "ALLOC_TRT_CLEANUP"
+  "ALLOC_TRT_IXR_CMD",
+  "ALLOC_TRT_CONFIG"
 };
 const char *alloc_upt_fsm_str[] =
@@ -357,5 +367,4 @@
   : soclib::caba::BaseModule(name),
 
-    m_monitor_ok(false),
     p_clk( "p_clk" ),
     p_resetn( "p_resetn" ),
@@ -437,7 +446,4 @@
     m_write_to_cc_send_inst_fifo("m_write_to_cc_send_inst_fifo",8),
     m_write_to_cc_send_srcid_fifo("m_write_to_cc_send_srcid_fifo",8),
-#if L1_MULTI_CACHE
-    m_write_to_cc_send_cache_id_fifo("m_write_to_cc_send_cache_id_fifo",8),
-#endif
 
     r_multi_ack_fsm("r_multi_ack_fsm"),
@@ -449,7 +455,4 @@
     m_cas_to_cc_send_inst_fifo("m_cas_to_cc_send_inst_fifo",8),
     m_cas_to_cc_send_srcid_fifo("m_cas_to_cc_send_srcid_fifo",8),
-#if L1_MULTI_CACHE
-    m_cas_to_cc_send_cache_id_fifo("m_cas_to_cc_send_cache_id_fifo",8),
-#endif
 
     r_ixr_rsp_fsm("r_ixr_rsp_fsm"),
@@ -458,7 +461,4 @@
     m_xram_rsp_to_cc_send_inst_fifo("m_xram_rsp_to_cc_send_inst_fifo",8),
     m_xram_rsp_to_cc_send_srcid_fifo("m_xram_rsp_to_cc_send_srcid_fifo",8),
-#if L1_MULTI_CACHE
-    m_xram_rsp_to_cc_send_cache_id_fifo("m_xram_rsp_to_cc_send_cache_id_fifo",8),
-#endif
 
     r_ixr_cmd_fsm("r_ixr_cmd_fsm"),
@@ -528,5 +528,5 @@
     r_xram_rsp_victim_data     = new sc_signal<data_t>[nwords];
     r_xram_rsp_to_tgt_rsp_data = new sc_signal<data_t>[nwords];
-    r_xram_rsp_to_ixr_cmd_data = new sc_signal<data_t>[nwords];
+    //r_xram_rsp_to_ixr_cmd_data = new sc_signal<data_t>[nwords];
 
     // Allocation for READ FSM
@@ -539,10 +539,13 @@
     r_write_to_cc_send_data    = new sc_signal<data_t>[nwords];
     r_write_to_cc_send_be      = new sc_signal<be_t>[nwords];
-    r_write_to_ixr_cmd_data    = new sc_signal<data_t>[nwords];
+    //r_write_to_ixr_cmd_data    = new sc_signal<data_t>[nwords];
 
     // Allocation for CAS FSM
-    r_cas_to_ixr_cmd_data      = new sc_signal<data_t>[nwords];
+    //r_cas_to_ixr_cmd_data      = new sc_signal<data_t>[nwords];
     r_cas_data                 = new sc_signal<data_t>[nwords];
     r_cas_rdata                = new sc_signal<data_t>[2];
+
+    // Allocation for IXR_CMD FSM
+    r_ixr_cmd_wdata            = new sc_signal<data_t>[nwords];
 
     // Allocation for ODCCP
@@ -553,6 +556,6 @@
 
     // Allocation for debug
-    m_debug_previous_data      = new sc_signal<data_t>[nwords];
-    m_debug_data               = new sc_signal<data_t>[nwords];
+    m_debug_previous_data      = new data_t[nwords];
+    m_debug_data               = new data_t[nwords];
 
     SC_METHOD(transition);
@@ -564,37 +567,4 @@
     sensitive << p_clk.neg();
 } // end constructor
-
-///////////////////////////////////////////////////////////////////////
-tmpl(void) ::start_monitor(addr_t addr, addr_t length)
-///////////////////////////////////////////////////////////////////////
-{
-  m_monitor_ok        = true;
-  m_monitor_base      = addr;
-  m_monitor_length    = length;
-}
-
-///////////////////////////////////////////////////////////////////////
-tmpl(void) ::stop_monitor()
-///////////////////////////////////////////////////////////////////////
-{
-  m_monitor_ok        = false;
-}
-
-////////////////////////////////////////////////
-tmpl(void) ::check_monitor( addr_t      addr,
-                            data_t      data,
-                            bool        read )
-////////////////////////////////////////////////
-{
-  if((addr >= m_monitor_base) and
-      (addr < m_monitor_base + m_monitor_length))
-  {
-    if ( read ) std::cout << " Monitor MEMC Read ";
-    else        std::cout << " Monitor MEMC Write";
-    std::cout << " / Address = " << std::hex << addr
-              << " / Data = " << data
-              << " at cycle " << std::dec << m_cpt_cycles << std::endl;
-  }
-}
 
 /////////////////////////////////////////////////////
@@ -609,33 +579,53 @@
 
     if ( entry.valid )
-    {
-        m_cache_data.read_line( way, set, m_debug_data );
-
-        for ( size_t i = 0 ; i<m_words ; i++ )
-        {
-            if ( m_debug_previous_valid and
-                 (m_debug_data[i].read() != m_debug_previous_data[i].read()) )
-                 data_change = true;
-            m_debug_previous_data[i] = m_debug_data[i].read();
-        }
-    }
-    
+     {
+        for ( size_t word = 0 ; word<m_words ; word++ )
+        {
+            m_debug_data[word] = m_cache_data.read(way, set, word);
+            if ( m_debug_previous_valid and 
+                 (m_debug_data[word] != m_debug_previous_data[word]) )
+            {
+                data_change = true;
+            }
+         }
+     }
+   
+    // print values if any change
     if ( (entry.valid != m_debug_previous_valid) or
          (entry.valid and (entry.count != m_debug_previous_count)) or
          (entry.valid and (entry.dirty != m_debug_previous_dirty)) or data_change )
     {
-        std::cout << "Monitor MEMC " << name()
-                  << " at cycle " << std::dec << m_cpt_cycles
-                  << " for address " << std::hex << addr
-                  << " / HIT = " << std::dec << entry.valid
-                  << " / WAY = " << way
-                  << " / COUNT = " << entry.count 
-                  << " / DIRTY = " << entry.dirty
-                  << " / DATA_CHANGE = " << entry.count 
-                  << std::endl;
+         std::cout << "Monitor MEMC " << name()
+                   << " at cycle " << std::dec << m_cpt_cycles
+                   << " for address " << std::hex << addr
+                   << " / VAL = " << std::dec << entry.valid
+                   << " / WAY = " << way
+                   << " / COUNT = " << entry.count 
+                   << " / DIRTY = " << entry.dirty
+                   << " / DATA_CHANGE = " << data_change 
+                   << std::endl;
+         std::cout << std::hex << "     /0:" << m_debug_data[0]
+                   << "/1:" << m_debug_data[1]
+                   << "/2:" << m_debug_data[2]
+                   << "/3:" << m_debug_data[3]
+                   << "/4:" << m_debug_data[4]
+                   << "/5:" << m_debug_data[5]
+                   << "/6:" << m_debug_data[6]
+                   << "/7:" << m_debug_data[7]
+                   << "/8:" << m_debug_data[8]
+                   << "/9:" << m_debug_data[9]
+                   << "/A:" << m_debug_data[10]
+                   << "/B:" << m_debug_data[11]
+                   << "/C:" << m_debug_data[12]
+                   << "/D:" << m_debug_data[13]
+                   << "/E:" << m_debug_data[14]
+                   << "/F:" << m_debug_data[15]
+                   << std::endl;
     }
     m_debug_previous_count = entry.count;
     m_debug_previous_valid = entry.valid;
     m_debug_previous_dirty = entry.dirty;
+    for( size_t word=0 ; word<m_words ; word++ ) 
+        m_debug_previous_data[word] = m_debug_data[word];
 }
 
@@ -836,5 +826,4 @@
   delete [] r_xram_rsp_victim_data;
   delete [] r_xram_rsp_to_tgt_rsp_data;
-  delete [] r_xram_rsp_to_ixr_cmd_data;
 
   delete [] r_read_data;
@@ -919,7 +908,4 @@
     m_config_to_cc_send_inst_fifo.init();
     m_config_to_cc_send_srcid_fifo.init();
-#if L1_MULTI_CACHE
-    m_config_to_cc_send_cache_id_fifo.init();
-#endif
 
     r_tgt_cmd_to_tgt_rsp_req = false;
@@ -938,7 +924,4 @@
     m_write_to_cc_send_inst_fifo.init();
     m_write_to_cc_send_srcid_fifo.init();
-#if L1_MULTI_CACHE
-    m_write_to_cc_send_cache_id_fifo.init();
-#endif
 
     r_cleanup_to_tgt_rsp_req      = false;
@@ -954,6 +937,6 @@
     r_cas_lfsr                    = -1   ;
     r_cas_to_ixr_cmd_req          = false;
-    r_cas_to_cc_send_multi_req   = false;
-    r_cas_to_cc_send_brdcast_req = false;
+    r_cas_to_cc_send_multi_req    = false;
+    r_cas_to_cc_send_brdcast_req  = false;
 
     m_cas_to_cc_send_inst_fifo.init();
@@ -969,6 +952,6 @@
 
     r_xram_rsp_to_tgt_rsp_req          = false;
-    r_xram_rsp_to_cc_send_multi_req   = false;
-    r_xram_rsp_to_cc_send_brdcast_req = false;
+    r_xram_rsp_to_cc_send_multi_req    = false;
+    r_xram_rsp_to_cc_send_brdcast_req  = false;
     r_xram_rsp_to_ixr_cmd_req          = false;
     r_xram_rsp_trt_index               = 0;
@@ -976,9 +959,5 @@
     m_xram_rsp_to_cc_send_inst_fifo.init();
     m_xram_rsp_to_cc_send_srcid_fifo.init();
-#if L1_MULTI_CACHE
-    m_xram_rsp_to_cc_send_cache_id_fifo.init();
-#endif
-
-    r_ixr_cmd_cpt          = 0;
+
     r_alloc_dir_reset_cpt  = 0;
     r_alloc_heap_reset_cpt = 0;
@@ -996,5 +975,4 @@
     r_cleanup_to_ixr_cmd_req   = false;
     r_cleanup_to_ixr_cmd_srcid = 0;
-    r_cleanup_to_ixr_cmd_trdid = 0;
     r_cleanup_to_ixr_cmd_pktid = 0;
     r_cleanup_to_ixr_cmd_nline = 0;
@@ -1095,8 +1073,4 @@
   size_t  write_to_cc_send_fifo_srcid = 0;
 
-#if L1_MULTI_CACHE
-  size_t  write_to_cc_send_fifo_cache_id = 0;
-#endif
-
   bool    xram_rsp_to_cc_send_fifo_put   = false;
   bool    xram_rsp_to_cc_send_fifo_get   = false;
@@ -1104,8 +1078,4 @@
   size_t  xram_rsp_to_cc_send_fifo_srcid = 0;
 
-#if L1_MULTI_CACHE
-  size_t  xram_rsp_to_cc_send_fifo_cache_id = 0;
-#endif
-
   bool    config_to_cc_send_fifo_put   = false;
   bool    config_to_cc_send_fifo_get   = false;
@@ -1117,8 +1087,4 @@
   bool    cas_to_cc_send_fifo_inst  = false;
   size_t  cas_to_cc_send_fifo_srcid = 0;
-
-#if L1_MULTI_CACHE
-  size_t  cas_to_cc_send_fifo_cache_id = 0;
-#endif
 
   m_debug = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
@@ -1275,5 +1241,5 @@
     case TGT_CMD_ERROR:  // response error must be sent
 
-    // wait if pending TGT_CMD request to TGT_RSP FSM
+    // wait if pending request
     if(r_tgt_cmd_to_tgt_rsp_req.read()) break;
 
@@ -1309,4 +1275,5 @@
         size_t   error;  
         uint32_t rdata = 0;         // default value
+        uint32_t wdata = p_vci_tgt.wdata.read();     
 
         if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ)         // get lock
@@ -1317,7 +1284,15 @@
             error            = 0;
             r_config_lock    = true;
+            if ( rdata == 0 )
+            {
+                r_tgt_cmd_srcid = p_vci_tgt.srcid.read();
+                r_tgt_cmd_trdid = p_vci_tgt.trdid.read();
+                r_tgt_cmd_pktid = p_vci_tgt.pktid.read();
+            }
+
         }
         else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)  // release lock
-                   and (cell == MEMC_LOCK) )
+                   and (cell == MEMC_LOCK) 
+                   and (p_vci_tgt.srcid.read() == r_tgt_cmd_srcid.read()) )
         {
             need_rsp         = true;
@@ -1326,6 +1301,10 @@
         }
         else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set addr_lo
-                   and (cell == MEMC_ADDR_LO) )
-        {
+                   and (cell == MEMC_ADDR_LO) 
+                   and (p_vci_tgt.srcid.read() == r_tgt_cmd_srcid.read()) )
+        {
+            assert( ((wdata % (m_words*vci_param_int::B)) == 0) and
+            "VCI_MEM_CACHE CONFIG ERROR: The buffer must be aligned on a cache line");
+
             need_rsp         = true;
             error            = 0;
@@ -1334,5 +1313,6 @@
         }
         else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set addr_hi
-                   and (cell == MEMC_ADDR_HI) )
+                   and (cell == MEMC_ADDR_HI)
+                   and (p_vci_tgt.srcid.read() == r_tgt_cmd_srcid.read()) )
         {
             need_rsp         = true;
@@ -1342,14 +1322,17 @@
         }
         else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set buf_lines
-                   and (cell == MEMC_BUF_LENGTH) )
+                   and (cell == MEMC_BUF_LENGTH)
+                   and (p_vci_tgt.srcid.read() == r_tgt_cmd_srcid.read()) )
         {
             need_rsp         = true;
             error            = 0;
             size_t lines = (size_t)(p_vci_tgt.wdata.read()/(m_words<<2));
-            if ( r_config_address.read()/(m_words*vci_param_int::B) ) lines++;
-            r_config_nlines  = lines;
+            if ( r_config_address.read()%(m_words*4) ) lines++;
+            r_config_cmd_lines  = lines;
+            r_config_rsp_lines  = lines;
         }
         else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set cmd type
-                   and (cell == MEMC_CMD_TYPE) )
+                   and (cell == MEMC_CMD_TYPE)
+                   and (p_vci_tgt.srcid.read() == r_tgt_cmd_srcid.read()) )
         {
             need_rsp         = false;
@@ -1386,4 +1369,5 @@
           << " address = " << std::hex << p_vci_tgt.address.read()
           << " / wdata = " << p_vci_tgt.wdata.read()
+          << " / need_rsp = " << need_rsp
           << " / error = " << error << std::endl;
 #endif
@@ -1489,7 +1473,6 @@
   //    MULTI_ACK FSM
   /////////////////////////////////////////////////////////////////////////
-  // This FSM controls the response to the multicast update or multicast
-  // inval coherence requests sent by the memory cache to the L1 caches and
-  // update the UPT.
+  // This FSM controls the response to the multicast update requests sent 
+  // by the memory cache to the L1 caches and update the UPT.
   //
   // - The FSM decrements the proper entry in UPT,
@@ -1497,9 +1480,7 @@
   // - If required, it sends a request to the TGT_RSP FSM to complete
   //   a pending  write transaction.
-  // - If required, it sends an acknowledge to the CONFIG FSM to signal 
-  //   completion of a line inval.
   //
   // All those multi-ack packets are one flit packet.
-  // The index in the UPT is defined in the UPDTID field.
+  // The index in the UPT is defined in the TRDID field.
   ////////////////////////////////////////////////////////////////////////
 
@@ -1618,5 +1599,4 @@
         r_multi_ack_nline = m_upt.nline(r_multi_ack_upt_index.read());
         bool need_rsp     = m_upt.need_rsp(r_multi_ack_upt_index.read());
-        bool need_ack     = m_upt.need_ack(r_multi_ack_upt_index.read());
 
         // clear the UPT entry
@@ -1624,5 +1604,4 @@
 
         if      ( need_rsp ) r_multi_ack_fsm = MULTI_ACK_WRITE_RSP;
-        else if ( need_ack ) r_multi_ack_fsm = MULTI_ACK_CONFIG_ACK;
         else                 r_multi_ack_fsm = MULTI_ACK_IDLE;
 
@@ -1655,20 +1634,4 @@
         break;
     }
-    //////////////////////////
-    case MULTI_ACK_CONFIG_ACK:    // Signals multi-inval completion to CONFIG FSM
-                                  // Wait if pending request 
-    {
-        if ( r_multi_ack_to_config_ack.read() ) break;
-
-        r_multi_ack_to_config_ack   = true;
-        r_multi_ack_fsm              = MULTI_ACK_IDLE;
-
-#if DEBUG_MEMC_MULTI_ACK
-if(m_debug)
-std::cout << "  <MEMC " << name() << " MULTI_ACK_CONFIG_ACK>"
-          << " Signals inval completion to CONFIG FSM" << std::endl;
-#endif
-        break;
-    }
   } // end switch r_multi_ack_fsm
 
@@ -1678,29 +1641,46 @@
   // The CONFIG FSM handles the VCI configuration requests (INVAL & SYNC).
   // The target buffer can have any size, and there is one single command for
-  // all cache lines covered by the target buffer. 
-  // An INVAL or SYNC configuration request is defined by the followinf registers:
-  // - bool      r_config_cmd        : INVAL / SYNC / NOP)
+  // all cache lines covered by the target buffer.
+  //
+  // An INVAL or SYNC configuration operation is defined by the following registers:
+  // - bool      r_config_cmd        : INVAL / SYNC / NOP
+
   // - uint64_t  r_config_address    : buffer base address
-  // - uint32_t  r_config_nlines     : number of lines covering buffer
+  // - uint32_t  r_config_cmd_lines  : number of lines to be handled
+  // - uint32_t  r_config_rsp_lines  : number of lines not completed
+ 
   //
   // For both INVAL and SYNC commands, the CONFIG FSM contains the loop handling 
-  // all cache lines covered by the target buffer.
   //
+  // all cache lines covered by the buffer. The various lines of a given buffer
+  // can be pipelined: the CONFIG FSM does not wait the response for line (n) to send
+  // the command for line (n+1). It decrements the r_config_cmd_lines counter until 
+  // the last request has been registered in TRT (for a SYNC), or in IVT (for an INVAL).
+  // 
   // - INVAL request:
-  //   For each line, it access to the DIR array. 
+  //   For each line, it access to the DIR. 
   //   In case of miss, it does nothing, and a response is requested to TGT_RSP FSM. 
   //   In case of hit, with no copies in L1 caches, the line is invalidated and
   //   a response is requested to TGT_RSP FSM.
   //   If there is copies, a multi-inval, or a broadcast-inval coherence transaction
-  //   is launched and registered in UPT. The multi-inval transaction is signaled
-  //   by the r_multi_ack_to config_ack or r_cleanup_to_config_ack flip-flops.
-  //   The config inval response is sent only when the last line has been invalidated.
   //
+  //   is launched and registered in UPT. The multi-inval transaction completion
+  //   is signaled by the CLEANUP FSM by decrementing the r_config_rsp_lines counter.
+  //   The CONFIG INVAL response is sent only when the last line has been invalidated.
+  //   TODO : The target buffer address must be aligned on a cache line boundary.
+  //   This constraint can be released, but it requires to make 2 PUT transactions
+  //   for the first and the last line...
+  // 
   // - SYNC request:
-  //
-  //  ...  Not implemented yet ...
+  //   For each line, it access to the DIR. 
+  //   In case of miss, it does nothing, and a response is requested to TGT_RSP FSM. 
+  //   In case of hit, a PUT transaction is registered in TRT and a request is sent
+  //   to IXR_CMD FSM. The IXR_RSP FSM decrements the r_config_rsp_lines counter
+  //   when a PUT response is received.
+  //   The CONFIG SYNC response is sent only when the last PUT response is received.
   //
   // From the software point of view, a configuration request is a sequence
-  // of 6 atomic accesses in an uncached segment:
+  // of 6 atomic accesses in an uncached segment. A dedicated lock is used 
+  // to handle only one configuration command at a given time:
   // - Read  MEMC_LOCK       : Get the lock
   // - Write MEMC_ADDR_LO    : Set the buffer address LSB
@@ -1724,5 +1704,5 @@
 std::cout << "  <MEMC " << name() << " CONFIG_IDLE> Config Request received" 
           << " address = " << std::hex << r_config_address.read()
-          << " / nlines = " << std::dec << r_config_nlines.read()
+          << " / nlines = " << std::dec << r_config_cmd_lines.read()
           << " / type = " << r_config_cmd.read() << std::endl;
 #endif
@@ -1731,10 +1711,10 @@
       }
       /////////////////
-      case CONFIG_LOOP:   // test last line 
-      {
-          if ( r_config_nlines.read() == 0 )
+      case CONFIG_LOOP:   // test last line to be handled 
+      {
+          if ( r_config_cmd_lines.read() == 0 )
           {
               r_config_cmd = MEMC_CMD_NOP;
-              r_config_fsm = CONFIG_RSP;
+              r_config_fsm = CONFIG_WAIT;
           }
           else
@@ -1747,9 +1727,49 @@
 std::cout << "  <MEMC " << name() << " CONFIG_LOOP>" 
           << " address = " << std::hex << r_config_address.read()    
-          << " / nlines = " << std::dec << r_config_nlines.read() 
+          << " / nlines = " << std::dec << r_config_cmd_lines.read() 
           << " / command = " << r_config_cmd.read() << std::endl;
 #endif
           break;
       }
+      /////////////////
+      case CONFIG_WAIT:   // wait completion (last response) 
+      {
+          if ( r_config_rsp_lines.read() == 0 )  // last response received
+          {
+              r_config_fsm = CONFIG_RSP;
+          }
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_WAIT>" 
+          << " / lines to do = " << std::dec << r_config_rsp_lines.read() << std::endl;
+#endif
+          break;
+      }
+      ////////////////
+      case CONFIG_RSP:  // request TGT_RSP FSM to return response 
+      {
+          if ( not r_config_to_tgt_rsp_req.read() )
+          {
+              r_config_to_tgt_rsp_srcid  = r_config_srcid.read();
+              r_config_to_tgt_rsp_trdid  = r_config_trdid.read();
+              r_config_to_tgt_rsp_pktid  = r_config_pktid.read();
+              r_config_to_tgt_rsp_error  = false;
+              r_config_to_tgt_rsp_req    = true;
+              r_config_fsm               = CONFIG_IDLE;
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_RSP> Request TGT_RSP FSM to return response:"
+          << " error = " << r_config_to_tgt_rsp_error.read()
+          << " / rsrcid = " << std::hex << r_config_srcid.read()
+          << " / rtrdid = " << std::hex << r_config_trdid.read()
+          << " / rpktid = " << std::hex << r_config_pktid.read() << std::endl;
+#endif
+          }
+          break;
+
+      }
+
       ////////////////////
       case CONFIG_DIR_REQ:  // Request directory lock
@@ -1770,4 +1790,7 @@
       case CONFIG_DIR_ACCESS:   // Access directory and decode config command
       {
+          assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and
+          "MEMC ERROR in CONFIG_DIR_ACCESS state: bad DIR allocation");
+
           size_t way = 0;
           DirectoryEntry entry = m_cache_directory.read(r_config_address.read(), way);
@@ -1781,7 +1804,8 @@
               r_config_dir_is_cnt     = entry.is_cnt;
               r_config_dir_count      = entry.count;
-              r_config_dir_next_ptr   = entry.ptr;
-
-              r_config_fsm    = CONFIG_DIR_IVT_LOCK;
+              r_config_dir_lock       = entry.lock;
+              r_config_dir_ptr        = entry.ptr;
+
+              r_config_fsm    = CONFIG_IVT_LOCK;
           }
           else if ( entry.valid and                       // hit & sync command
@@ -1789,13 +1813,13 @@
                     (r_config_cmd.read() == MEMC_CMD_SYNC) )
           { 
-              std::cout << "VCI_MEM_CACHE ERROR: "
-                        << "SYNC config request not implemented yet" << std::endl;
-              exit(0);
+              r_config_fsm = CONFIG_TRT_LOCK;
           }
           else                                            // return to LOOP 
           {
-              r_config_nlines  = r_config_nlines.read() - 1;
-              r_config_address = r_config_address.read() + (m_words<<2);
-              r_config_fsm     = CONFIG_LOOP;
+              r_config_cmd_lines = r_config_cmd_lines.read() - 1;
+              r_config_rsp_lines = r_config_rsp_lines.read() - 1;
+              r_config_cmd_lines = r_config_cmd_lines.read() - 1;
+              r_config_address   = r_config_address.read() + (m_words<<2);
+              r_config_fsm       = CONFIG_LOOP;
           }
 
@@ -1811,11 +1835,132 @@
           break;
       }
-      /////////////////////////
-      case CONFIG_DIR_IVT_LOCK:  // enter this state in case of INVAL command
-                                 // Try to get both DIR & IVT locks, and return
-                                 // to LOOP state if IVT full.
-                                 // Register inval in IVT, and invalidate the
-                                 // directory if IVT not full. 
-      {
+      /////////////////////
+      case CONFIG_TRT_LOCK:      // enter this state in case of SYNC command
+                                 // to a dirty cache line 
+                                 // keep DIR lock, and try to get TRT lock
+                                 // return to LOOP state if TRT full
+                                 // reset dirty bit in DIR and register a PUT
+                                 // trabsaction in TRT if not full.
+      {
+          assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and
+          "MEMC ERROR in CONFIG_TRT_LOCK state: bad DIR allocation");
+
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_CONFIG )
+          {
+              size_t index = 0;
+              bool   wok   = not m_trt.full(index);
+
+              if ( not wok )
+              {
+                  r_config_fsm = CONFIG_LOOP;
+              }
+              else
+              {
+                  size_t          way = r_config_dir_way.read();
+                  size_t          set = m_y[r_config_address.read()];
+
+                  // reset dirty bit in DIR
+                  DirectoryEntry  entry;
+                  entry.valid       = true;
+                  entry.dirty       = false;
+                  entry.tag         = m_z[r_config_address.read()];
+                  entry.is_cnt      = r_config_dir_is_cnt.read();
+                  entry.lock        = r_config_dir_lock.read();
+                  entry.ptr         = r_config_dir_ptr.read();
+                  entry.count       = r_config_dir_count.read();
+                  entry.owner.inst  = r_config_dir_copy_inst.read();
+                  entry.owner.srcid = r_config_dir_copy_srcid.read();
+                  m_cache_directory.write( set, 
+                                           way, 
+                                           entry );
+
+                  r_config_trt_index = index;
+                  r_config_fsm       = CONFIG_TRT_SET;
+              }
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_TRT_LOCK> Access TRT: "
+          << " wok = " << std::dec << wok
+          << " index = " << index << std::endl;
+#endif
+          }
+          break;
+      }
+      ////////////////////
+      case CONFIG_TRT_SET:       // read data in cache
+                                 // and post a PUT request in TRT
+      {
+          assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and
+          "MEMC ERROR in CONFIG_TRT_SET state: bad DIR allocation");
+
+          assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_CONFIG) and
+          "MEMC ERROR in CONFIG_TRT_SET state: bad TRT allocation");
+
+          // read data into cache
+          size_t          way = r_config_dir_way.read();
+          size_t          set = m_y[r_config_address.read()];
+
+          sc_signal<data_t> config_data[16];
+          m_cache_data.read_line( way, 
+                                  set, 
+                                  config_data );
+            
+          // post a PUT request in TRT
+          std::vector<data_t> data_vector;
+          data_vector.clear();
+          for(size_t i=0; i<m_words; i++) data_vector.push_back(config_data[i].read());
+          m_trt.set( r_config_trt_index.read(),
+                     false,                               // PUT
+                     m_nline[r_config_address.read()],    // nline
+                     0,                                   // srcid:       unused
+                     0,                                   // trdid:       unused
+                     0,                                   // pktid:       unused
+                     false,                               // not proc_read
+                     0,                                   // read_length: unused
+                     0,                                   // word_index:  unused
+                     std::vector<be_t>(m_words,0xF),                         
+                     data_vector);
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+          m_trt.print(0);
+std::cout << "  <MEMC " << name() << " CONFIG_TRT_SET> PUT request in TRT:"
+          << " address = " << std::hex << r_config_address.read()
+          << " index = " << std::dec << r_config_trt_index.read() << std::endl;
+#endif
+          break;
+      }
+      ////////////////////
+      case CONFIG_PUT_REQ:       // PUT request to IXR_CMD_FSM
+      {
+          if ( not r_config_to_ixr_cmd_req.read() )
+          {
+              r_config_to_ixr_cmd_req   = true;
+              r_config_to_ixr_cmd_index = r_config_trt_index.read();
+
+              // prepare next iteration
+              r_config_cmd_lines              = r_config_cmd_lines.read() - 1;
+              r_config_address                = r_config_address.read() + (m_words<<2);
+              r_config_fsm                    = CONFIG_LOOP;
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_PUT_REQ> PUT request to IXR_CMD_FSM"
+          << " / address = " << std::hex << r_config_address.read() << std::endl; 
+#endif
+          }
+          break;
+      }
+      /////////////////////
+      case CONFIG_IVT_LOCK:  // enter this state in case of INVAL command
+                             // Keep DIR lock and Try to get IVT lock.
+                             // Return to LOOP state if IVT full.
+                             // Register inval in IVT, and invalidate the
+                             // directory if IVT not full. 
+      {
+          assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and
+          "MEMC ERROR in CONFIG_IVT_LOCK state: bad DIR allocation");
+
           if ( r_alloc_ivt_fsm.read() == ALLOC_IVT_CONFIG )
           {
@@ -1826,11 +1971,12 @@
               {
                   m_cache_directory.inval( way, set );
-                  r_config_nlines  = r_config_nlines.read() - 1;
-                  r_config_address = r_config_address.read() + (m_words<<2);
-                  r_config_fsm     = CONFIG_LOOP;
-
-#if DEBUG_MEMC_CONFIG
-if(m_debug)
-std::cout << "  <MEMC " << name() << " CONFIG_DIR_IVT_LOCK>"
+                  r_config_cmd_lines  = r_config_cmd_lines.read() - 1;
+                  r_config_rsp_lines  = r_config_rsp_lines.read() - 1;
+                  r_config_address    = r_config_address.read() + (m_words<<2);
+                  r_config_fsm        = CONFIG_LOOP;
+
+ #if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_IVT_LOCK>"
           << " No copies in L1 : inval DIR entry"  << std::endl;
 #endif
@@ -1863,9 +2009,9 @@
                       r_config_ivt_index = index;
                       if ( broadcast )  r_config_fsm = CONFIG_BC_SEND;
-                      else              r_config_fsm = CONFIG_INV_SEND;
+                      else              r_config_fsm = CONFIG_INVAL_SEND;
 
 #if DEBUG_MEMC_CONFIG
 if(m_debug)
-std::cout << "  <MEMC " << name() << " CONFIG_DIR_IVT_LOCK>"
+std::cout << "  <MEMC " << name() << " CONFIG_IVT_LOCK>"
           << " Inval DIR entry and register inval in IVT"
           << " : index = " << std::dec << index
@@ -1879,5 +2025,5 @@
 #if DEBUG_MEMC_CONFIG
 if(m_debug)
-std::cout << "  <MEMC " << name() << " CONFIG_DIR_IVT_LOCK>"
+std::cout << "  <MEMC " << name() << " CONFIG_IVT_LOCK>"
           << " IVT full : release DIR & IVT locks and retry" << std::endl;
 #endif
@@ -1893,10 +2039,14 @@
               not r_config_to_cc_send_brdcast_req.read() )
           {
+              // post bc inval request
               r_config_to_cc_send_multi_req   = false;
               r_config_to_cc_send_brdcast_req = true;
               r_config_to_cc_send_trdid       = r_config_ivt_index.read();
               r_config_to_cc_send_nline       = m_nline[(addr_t)(r_config_address.read())];
-              r_cleanup_to_config_ack         = false;
-              r_config_fsm                    = CONFIG_BC_WAIT;
+
+              // prepare next iteration
+              r_config_cmd_lines              = r_config_cmd_lines.read() - 1;
+              r_config_address                = r_config_address.read() + (m_words<<2);
+              r_config_fsm                    = CONFIG_LOOP;
 
 #if DEBUG_MEMC_CONFIG
@@ -1909,24 +2059,6 @@
           break;
       }
-      ////////////////////
-      case CONFIG_BC_WAIT:      // wait broadcast completion to return to LOOP
-      {
-          if ( r_cleanup_to_config_ack.read() ) 
-          {
-              r_config_fsm     = CONFIG_LOOP;
-              r_config_nlines  = r_config_nlines.read() - 1;
-              r_config_address = r_config_address.read() + (m_words<<2);
-          }
-
-#if DEBUG_MEMC_CONFIG
-if(m_debug)
-std::cout << "  <MEMC " << name() << " CONFIG_BC_WAIT> Waiting BC completion " 
-          << " done = " << r_cleanup_to_config_ack.read() 
-          << std::endl; 
-#endif
-          break;
-      }
-      /////////////////////
-      case CONFIG_INV_SEND:    // Post a multi inval request to CC_SEND FSM
+      ///////////////////////
+      case CONFIG_INVAL_SEND:    // Post a multi inval request to CC_SEND FSM
       {
           if( not r_config_to_cc_send_multi_req.read() and 
@@ -1937,16 +2069,25 @@
               r_config_to_cc_send_trdid       = r_config_ivt_index.read();
               r_config_to_cc_send_nline       = m_nline[(addr_t)(r_config_address.read())];
-              r_multi_ack_to_config_ack       = false;
-
+
+              // post data into FIFO
               config_to_cc_send_fifo_srcid    = r_config_dir_copy_srcid.read();
               config_to_cc_send_fifo_inst     = r_config_dir_copy_inst.read();
               config_to_cc_send_fifo_put      = true;
 
-              if ( r_config_dir_count.read() == 1 )  r_config_fsm = CONFIG_INV_WAIT;
-              else                                   r_config_fsm = CONFIG_HEAP_REQ;
-
+              if ( r_config_dir_count.read() == 1 )  // one copy
+              {
+                  // prepare next iteration
+                  r_config_cmd_lines          = r_config_cmd_lines.read() - 1;
+                  r_config_address            = r_config_address.read() + (m_words<<2);
+                  r_config_fsm                = CONFIG_LOOP;
+              }
+              else                                   // several copies
+              {
+                  r_config_fsm = CONFIG_HEAP_REQ;
+              }
+ 
 #if DEBUG_MEMC_CONFIG
 if(m_debug)
-std::cout << "  <MEMC " << name() << " CONFIG_INV_SEND>"
+std::cout << "  <MEMC " << name() << " CONFIG_INVAL_SEND>"
           << " Post multi inval request to CC_SEND FSM" 
           << " / address = " << std::hex << r_config_address.read() 
@@ -1963,5 +2104,5 @@
           {
               r_config_fsm       = CONFIG_HEAP_SCAN;
-              r_config_heap_next = r_config_dir_next_ptr.read();
+              r_config_heap_next = r_config_dir_ptr.read();
           }
 
@@ -2010,5 +2151,5 @@
           if ( m_heap.is_full() )
           {
-              last_entry.next = r_config_dir_next_ptr.read();
+              last_entry.next = r_config_dir_ptr.read();
               m_heap.unset_full();
           }
@@ -2018,7 +2159,11 @@
           }
 
-          m_heap.write_free_ptr( r_config_dir_next_ptr.read() );
+          m_heap.write_free_ptr( r_config_dir_ptr.read() );
           m_heap.write( r_config_heap_next.read(), last_entry );
-          r_config_fsm = CONFIG_INV_WAIT;
+
+          // prepare next iteration
+          r_config_cmd_lines          = r_config_cmd_lines.read() - 1;
+          r_config_address            = r_config_address.read() + (m_words<<2);
+          r_config_fsm                = CONFIG_LOOP;
 
 #if DEBUG_MEMC_CONFIG
@@ -2028,45 +2173,4 @@
 #endif
           break;
-      }
-      /////////////////////
-      case CONFIG_INV_WAIT:      // wait inval completion to return to LOOP
-      {
-          if ( r_multi_ack_to_config_ack.read() )
-          {
-              r_config_fsm     = CONFIG_LOOP;
-              r_config_nlines  = r_config_nlines.read() - 1;
-              r_config_address = r_config_address.read() + (m_words<<2);
-          }
-
-#if DEBUG_MEMC_CONFIG
-if(m_debug)
-std::cout << "  <MEMC " << name() << " CONFIG_INV_WAIT> Waiting inval completion " 
-          << " done = " << r_multi_ack_to_config_ack.read() 
-          << std::endl; 
-#endif
-          break;
-      }
-
-      ////////////////
-      case CONFIG_RSP:  // request TGT_RSP FSM to return response 
-      {
-          if ( not r_config_to_tgt_rsp_req.read() )
-          {
-              r_config_to_tgt_rsp_srcid  = r_config_srcid.read();
-              r_config_to_tgt_rsp_trdid  = r_config_trdid.read();
-              r_config_to_tgt_rsp_pktid  = r_config_pktid.read();
-              r_config_to_tgt_rsp_error  = false;
-              r_config_to_tgt_rsp_req    = true;
-              r_config_fsm               = CONFIG_IDLE;
-
-#if DEBUG_MEMC_CONFIG
-if(m_debug)
-std::cout << "  <MEMC " << name() << " CONFIG_RSP> Request TGT_RSP FSM to return response:"
-          << " error = " << r_config_to_tgt_rsp_error.read()
-          << " / rsrcid = " << std::hex << r_config_srcid.read() << std::endl;
-#endif
-          }
-          break;
-
       }
   }  // end switch r_config_fsm
@@ -2122,9 +2226,9 @@
     case READ_DIR_REQ:  // Get the lock to the directory
     {
-      if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ)
-      {
-        r_read_fsm = READ_DIR_LOCK;
-        m_cpt_read_fsm_n_dir_lock++;
-      }
+        if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ)
+        {
+          r_read_fsm = READ_DIR_LOCK;
+          m_cpt_read_fsm_n_dir_lock++;
+    }
 
 #if DEBUG_MEMC_READ
@@ -2141,9 +2245,10 @@
     case READ_DIR_LOCK:  // check directory for hit / miss
     {
-      if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ)
-      {
+        assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_READ) and
+        "MEMC ERROR in READ_DIR_LOCK state: Bad DIR allocation");
+
         size_t way = 0;
         DirectoryEntry entry =
-          m_cache_directory.read(m_cmd_read_addr_fifo.read(), way);
+        m_cache_directory.read(m_cmd_read_addr_fifo.read(), way);
         if(((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) and not r_read_ll_done.read())   // access the global table ONLY when we have an LL cmd
         {
@@ -2164,7 +2269,4 @@
         r_read_copy       = entry.owner.srcid;
 
-#if L1_MULTI_CACHE
-        r_read_copy_cache = entry.owner.cache_id;
-#endif
         r_read_copy_inst  = entry.owner.inst;
         r_read_ptr        = entry.ptr; // pointer to the heap
@@ -2216,11 +2318,4 @@
 }
 #endif
-      }
-      else
-      {
-        std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_DIR_LOCK state"
-                  << "Bad DIR allocation"   << std::endl;
-        exit(0);
-      }
       break;
     }
@@ -2318,6 +2413,6 @@
 
     {
-      if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ)
-      {
+         assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_READ) and
+        "MEMC ERROR in READ_DIR_HIT state: Bad DIR allocation");
         // check if this is an instruction read, this means pktid is either
         // TYPE_READ_INS_UNC   0bX010 with TSAR encoding
@@ -2335,6 +2430,4 @@
 
         m_cache_data.read_line(way, set, r_read_data);
-
-        if(m_monitor_ok) check_monitor( m_cmd_read_addr_fifo.read(), r_read_data[0], true);
 
         // update the cache directory
@@ -2353,7 +2446,4 @@
           {
             entry.owner.srcid    = m_cmd_read_srcid_fifo.read();
-#if L1_MULTI_CACHE
-            entry.owner.cache_id = m_cmd_read_pktid_fifo.read();
-#endif
             entry.owner.inst     = inst_read;
             entry.count          = r_read_count.read() + 1;
@@ -2362,7 +2452,4 @@
           {
             entry.owner.srcid    = 0;
-#if L1_MULTI_CACHE
-            entry.owner.cache_id = 0;
-#endif
             entry.owner.inst     = false;
             entry.count          = r_read_count.read() + 1;
@@ -2372,7 +2459,4 @@
         {
           entry.owner.srcid     = r_read_copy.read();
-#if L1_MULTI_CACHE
-          entry.owner.cache_id  = r_read_copy_cache.read();
-#endif
           entry.owner.inst      = r_read_copy_inst.read();
           entry.count           = r_read_count.read();
@@ -2394,6 +2478,5 @@
         m_cache_directory.write(set, way, entry);
         r_read_fsm    = READ_RSP;
-      }
-      break;
+        break;
     }
     ///////////////////
@@ -2436,6 +2519,4 @@
 
         m_cache_data.read_line(way, set, r_read_data);
-
-        if(m_monitor_ok) check_monitor( m_cmd_read_addr_fifo.read(), r_read_data[0], true);
 
         // update the cache directory
@@ -2452,7 +2533,4 @@
         {
           entry.owner.srcid    = r_read_copy.read();
-#if L1_MULTI_CACHE
-          entry.owner.cache_id = r_read_copy_cache.read();
-#endif
           entry.owner.inst     = r_read_copy_inst.read();
           entry.ptr            = m_heap.next_free_ptr();   // set pointer on the heap
@@ -2461,7 +2539,4 @@
         {
           entry.owner.srcid    = 0;
-#if L1_MULTI_CACHE
-          entry.owner.cache_id = 0;
-#endif
           entry.owner.inst     = false;
           entry.ptr            = 0;
@@ -2529,7 +2604,4 @@
         HeapEntry heap_entry;
         heap_entry.owner.srcid    = m_cmd_read_srcid_fifo.read();
-#if L1_MULTI_CACHE
-        heap_entry.owner.cache_id = m_cmd_read_pktid_fifo.read();
-#endif
         heap_entry.owner.inst     = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0);
 
@@ -2595,7 +2667,4 @@
         HeapEntry last_entry;
         last_entry.owner.srcid    = 0;
-#if L1_MULTI_CACHE
-        last_entry.owner.cache_id = 0;
-#endif
         last_entry.owner.inst     = false;
 
@@ -2718,5 +2787,6 @@
 #if DEBUG_MEMC_READ
 if(m_debug)
-std::cout << "  <MEMC " << name() << " READ_TRT_SET> Write in Transaction Table:"
+          m_trt.print(0);
+std::cout << "  <MEMC " << name() << " READ_TRT_SET> Set a GET in TGT:"
           << " address = " << std::hex << m_cmd_read_addr_fifo.read()
           << " / srcid = " << std::hex << m_cmd_read_srcid_fifo.read() << std::endl;
@@ -2734,6 +2804,6 @@
         cmd_read_fifo_get       = true;
         r_read_to_ixr_cmd_req   = true;
-        r_read_to_ixr_cmd_nline = m_nline[(addr_t)(m_cmd_read_addr_fifo.read())];
-        r_read_to_ixr_cmd_trdid = r_read_trt_index.read();
+        //r_read_to_ixr_cmd_nline = m_nline[(addr_t)(m_cmd_read_addr_fifo.read())];
+        r_read_to_ixr_cmd_index = r_read_trt_index.read();
         r_read_fsm              = READ_IDLE;
 
@@ -2762,7 +2832,6 @@
   //   If the data is cached by other processors, a coherence transaction must
   //   be launched (sc requests always require a coherence transaction):
-  //   It is a multicast update if the line is not in counter mode, and the processor
+  //   It is a multicast update if the line is not in counter mode: the processor
   //   takes the lock protecting the Update Table (UPT) to register this transaction.
-  //   It is a broadcast invalidate if the line is in counter mode.
   //   If the UPT is full, it releases the lock(s) and retry. Then, it sends
   //   a multi-update request to all owners of the line (but the writer),
@@ -2770,9 +2839,12 @@
   //   does not respond to the writing processor, as this response will be sent by
   //   the MULTI_ACK FSM when all update responses have been received.
+  //   It is a broadcast invalidate if the line is in counter mode: The line
+  //   should be erased in memory cache, and written in XRAM with a PUT transaction,
+  //   after registration in TRT.
   //
   // - In case of MISS, the WRITE FSM takes the lock protecting the transaction
   //   table (TRT). If a read transaction to the XRAM for this line already exists,
   //   it writes in the TRT (write buffer). Otherwise, if a TRT entry is free,
-  //   the WRITE FSM register a new transaction in TRT, and sends a read line request
+  //   the WRITE FSM register a new transaction in TRT, and sends a GET request
   //   to the XRAM. If the TRT is full, it releases the lock, and waits.
   //   Finally, the WRITE FSM returns an aknowledge response to the writing processor.
@@ -2849,12 +2921,7 @@
 
         // check that the next word is in the same cache line
-        if((m_nline[(addr_t)(r_write_address.read())]       !=
-            m_nline[(addr_t)(m_cmd_write_addr_fifo.read())]))
-        {
-          std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_NEXT state" << std::endl
-                    << "all words in a write burst must be in same cache line" << std::endl;
-
-          exit(0);
-        }
+        assert( (m_nline[(addr_t)(r_write_address.read())] == 
+               m_nline[(addr_t)(m_cmd_write_addr_fifo.read())]) and
+        "MEMC ERROR in WRITE_NEXT state: Illegal write burst");
 
         // consume a word in the FIFO & write it in the local buffer
@@ -2922,5 +2989,5 @@
         // erase any possible new reservation when we release the lock on the
         // directory
-        m_llsc_table.sw(nline);
+        m_llsc_table.sw(m_nline[(addr_t)r_write_address.read()],r_write_word_index.read(),r_write_word_index.read()+r_write_word_count.read());
 
         //m_llsc_table.sw(r_write_address.read());
@@ -2944,6 +3011,6 @@
     case WRITE_DIR_LOCK:     // access directory to check hit/miss
     {
-      if(r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE)
-      {
+        assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and
+        "MEMC ERROR in ALLOC_DIR_LOCK state: Bad DIR allocation");
         size_t  way = 0;
         DirectoryEntry entry(m_cache_directory.read(r_write_address.read(), way));
@@ -2956,7 +3023,4 @@
           r_write_tag        = entry.tag;
           r_write_copy       = entry.owner.srcid;
-#if L1_MULTI_CACHE
-          r_write_copy_cache = entry.owner.cache_id;
-#endif
           r_write_copy_inst  = entry.owner.inst;
           r_write_count      = entry.count;
@@ -2970,5 +3034,5 @@
             if(entry.is_cnt && entry.count)
             {
-              r_write_fsm = WRITE_DIR_READ;
+              r_write_fsm = WRITE_BC_DIR_READ;
             }
             else
@@ -3012,13 +3076,4 @@
 }
 #endif
-      }
-      else
-      {
-        std::cout << "VCI_MEM_CACHE ERROR " << name()
-                  << " WRITE_DIR_LOCK state"        << std::endl
-                  << "bad DIR allocation"           << std::endl;
-
-        exit(0);
-      }
       break;
     }
@@ -3076,39 +3131,10 @@
     }
 
-
-    ////////////////////
-    case WRITE_DIR_READ:  // read the cache and complete the buffer when be!=0xF
-    {
-      // update local buffer
-      size_t set  = m_y[(addr_t)(r_write_address.read())];
-      size_t way  = r_write_way.read();
-      for(size_t word=0 ; word<m_words ; word++)
-      {
-        data_t mask = 0;
-        if(r_write_be[word].read() & 0x1) mask = mask | 0x000000FF;
-        if(r_write_be[word].read() & 0x2) mask = mask | 0x0000FF00;
-        if(r_write_be[word].read() & 0x4) mask = mask | 0x00FF0000;
-        if(r_write_be[word].read() & 0x8) mask = mask | 0xFF000000;
-
-        // complete only if mask is not null (for energy consumption)
-        r_write_data[word]  = (r_write_data[word].read() & mask) |
-                              (m_cache_data.read(way, set, word) & ~mask);
-
-      } // end for
-
-      // test if a coherence broadcast is required
-      r_write_fsm = WRITE_BC_TRT_LOCK;
-
-#if DEBUG_MEMC_WRITE
-if(m_debug)
-std::cout << "  <MEMC " << name() << " WRITE_DIR_READ>"
-          << " Read the cache to complete local buffer" << std::endl;
-#endif
-      break;
-    }
-
     ///////////////////
     case WRITE_DIR_HIT:
     {
+      assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and
+      "MEMC ERROR in ALLOC_DIR_HIT state: Bad DIR allocation");
+ 
       // update the cache directory
       // update directory with Dirty bit
@@ -3121,7 +3147,4 @@
       entry.lock           = r_write_lock.read();
       entry.owner.srcid    = r_write_copy.read();
-#if L1_MULTI_CACHE
-      entry.owner.cache_id = r_write_copy_cache.read();
-#endif
       entry.owner.inst     = r_write_copy_inst.read();
       entry.count          = r_write_count.read();
@@ -3154,9 +3177,4 @@
           m_cache_data.write(way, set, word, r_write_data[word].read(), r_write_be[word].read());
 
-          if(m_monitor_ok)
-          {
-            addr_t address = (r_write_address.read() & ~(addr_t) 0x3F) | word<<2;
-            check_monitor( address, r_write_data[word].read(), false);
-          }
         }
       }
@@ -3242,14 +3260,9 @@
                                r_write_be[word].read());
 
-            if(m_monitor_ok)
-            {
-              addr_t address = (r_write_address.read() & ~(addr_t) 0x3F) | word<<2;
-              check_monitor( address, r_write_data[word].read(), false);
-            }
           }
         }
 
 #if DEBUG_MEMC_WRITE
-if(m_debug)
+if(m_debug and wok)
 {
     if(wok)
@@ -3317,9 +3330,5 @@
       for(size_t i=min ; i<max ; i++) r_write_to_cc_send_data[i] = r_write_data[i];
 
-      if((r_write_copy.read() != r_write_srcid.read()) or(r_write_pktid.read() == TYPE_SC) or
-#if L1_MULTI_CACHE
-          (r_write_copy_cache.read() != r_write_pktid.read()) or
-#endif
-          r_write_copy_inst.read())
+      if((r_write_copy.read() != r_write_srcid.read()) or(r_write_pktid.read() == TYPE_SC) or r_write_copy_inst.read())
       {
         // put the first srcid in the fifo
@@ -3327,7 +3336,4 @@
         write_to_cc_send_fifo_inst    = r_write_copy_inst.read();
         write_to_cc_send_fifo_srcid   = r_write_copy.read();
-#if L1_MULTI_CACHE
-        write_to_cc_send_fifo_cache_id= r_write_copy_cache.read();
-#endif
         if(r_write_count.read() == 1)
         {
@@ -3380,9 +3386,5 @@
       bool dec_upt_counter;
 
-      if(((entry.owner.srcid != r_write_srcid.read()) or (r_write_pktid.read() == TYPE_SC)) or
-#if L1_MULTI_CACHE
-          (entry.owner.cache_id != r_write_pktid.read()) or
-#endif
-          entry.owner.inst)             // put the next srcid in the fifo
+      if(((entry.owner.srcid != r_write_srcid.read()) or (r_write_pktid.read() == TYPE_SC)) or entry.owner.inst)             // put the next srcid in the fifo
       {
         dec_upt_counter                = false;
@@ -3390,7 +3392,4 @@
         write_to_cc_send_fifo_inst     = entry.owner.inst;
         write_to_cc_send_fifo_srcid    = entry.owner.srcid;
-#if L1_MULTI_CACHE
-        write_to_cc_send_fifo_cache_id = entry.owner.cache_id;
-#endif
 
 #if DEBUG_MEMC_WRITE
@@ -3573,5 +3572,5 @@
         bool    hit_read  = m_trt.hit_read(m_nline[addr], hit_index);
         bool    hit_write = m_trt.hit_write(m_nline[addr]);
-        bool    wok       = !m_trt.full(wok_index);
+        bool    wok       = not m_trt.full(wok_index);
         //std::cout << "MEMCACHE : WRITE MISS at " << std::hex << (uint32_t)addr << std::dec << std::endl;
         if(hit_read)      // register the modified data in TRT
@@ -3641,4 +3640,5 @@
 #if DEBUG_MEMC_WRITE
 if(m_debug)
+        m_trt.print(0);
 std::cout << "  <MEMC " << name() << " WRITE_MISS_TRT_SET> Set a new entry in TRT" << std::endl;
 #endif
@@ -3662,6 +3662,6 @@
         }
         m_trt.write_data_mask(r_write_trt_index.read(),
-                                          be_vector,
-                                          data_vector);
+                              be_vector,
+                              data_vector);
         r_write_fsm = WRITE_RSP;
 
@@ -3677,10 +3677,9 @@
     case WRITE_MISS_XRAM_REQ: // send a GET request to IXR_CMD FSM
     {
-      if(!r_write_to_ixr_cmd_req)
+      if(not r_write_to_ixr_cmd_req.read())
       {
         r_write_to_ixr_cmd_req   = true;
-        r_write_to_ixr_cmd_write = false;
-        r_write_to_ixr_cmd_nline = m_nline[(addr_t)(r_write_address.read())];
-        r_write_to_ixr_cmd_trdid = r_write_trt_index.read();
+        r_write_to_ixr_cmd_put   = false;
+        r_write_to_ixr_cmd_index = r_write_trt_index.read();
         r_write_fsm              = WRITE_RSP;
 
@@ -3694,10 +3693,47 @@
 
     ///////////////////////
-    case WRITE_BC_TRT_LOCK:     // Check TRT not full
-    {
+    case WRITE_BC_DIR_READ:  // enter this state if a broadcast-inval is required
+                             // the cache line must be erased in mem-cache, and written
+                             // into XRAM. we read the cache and complete the buffer
+    {
+        assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and
+        "MEMC ERROR in WRITE_BC_DIR_READ state: Bad DIR allocation");
+ 
+        // update local buffer
+        size_t set  = m_y[(addr_t)(r_write_address.read())];
+        size_t way  = r_write_way.read();
+        for(size_t word=0 ; word<m_words ; word++)
+        {
+            data_t mask = 0;
+            if(r_write_be[word].read() & 0x1) mask = mask | 0x000000FF;
+            if(r_write_be[word].read() & 0x2) mask = mask | 0x0000FF00;
+            if(r_write_be[word].read() & 0x4) mask = mask | 0x00FF0000;
+            if(r_write_be[word].read() & 0x8) mask = mask | 0xFF000000;
+
+            // complete only if mask is not null (for energy consumption)
+            r_write_data[word]  = (r_write_data[word].read() & mask) |
+                                  (m_cache_data.read(way, set, word) & ~mask);
+        } // end for
+
+        r_write_fsm = WRITE_BC_TRT_LOCK;
+
+#if DEBUG_MEMC_WRITE
+if(m_debug)
+std::cout << "  <MEMC " << name() << " WRITE_BC_DIR_READ>"
+          << " Read the cache to complete local buffer" << std::endl;
+#endif
+        break;
+    }
+
+    ///////////////////////
+    case WRITE_BC_TRT_LOCK:     // get TRT lock to check TRT not full
+    {
+      assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and
+      "MEMC ERROR in WRITE_BC_TRT_LOCK state: Bad DIR allocation");
+
       if(r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE)
       {
         size_t wok_index = 0;
-        bool wok = !m_trt.full(wok_index);
+        bool wok = not m_trt.full(wok_index);
         if(wok)       // set a new entry in TRT
         {
@@ -3726,4 +3762,10 @@
     case WRITE_BC_IVT_LOCK:      // register BC transaction in IVT
     {
+      assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and
+      "MEMC ERROR in WRITE_BC_IVT_LOCK state: Bad DIR allocation");
+
+      assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) and
+      "MEMC ERROR in WRITE_BC_IVT_LOCK state: Bad TRT allocation");
+
       if(r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE)
       {
@@ -3767,27 +3809,28 @@
     case WRITE_BC_DIR_INVAL:
     {
-      // Register a put transaction to XRAM in TRT
-      // and invalidate the line in directory
-      if((r_alloc_trt_fsm.read() != ALLOC_TRT_WRITE) or
-         (r_alloc_ivt_fsm.read() != ALLOC_IVT_WRITE) or
-         (r_alloc_dir_fsm.read() != ALLOC_DIR_WRITE))
-      {
-        std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_BC_DIR_INVAL state" << std::endl;
-        std::cout << "bad TRT, DIR, or IVT allocation" << std::endl;
-        exit(0);
-      }
-
-      // register a write request to XRAM in TRT
-      m_trt.set(r_write_trt_index.read(),
-                            false,    // write request to XRAM
-                            m_nline[(addr_t)(r_write_address.read())],
-                            0,
-                            0,
-                            0,
-                            false,    // not a processor read
-                            0,        // not a single word
-                            0,            // word index
-                            std::vector<be_t> (m_words,0),
-                            std::vector<data_t> (m_words,0));
+      assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and
+      "MEMC ERROR in WRITE_BC_DIR_INVAL state: Bad DIR allocation");
+
+      assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) and
+      "MEMC ERROR in WRITE_BC_DIR_INVAL state: Bad TRT allocation");
+ 
+      assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) and
+      "MEMC ERROR in WRITE_BC_DIR_INVAL state: Bad IVT allocation");
+
+      // register PUT request in TRT
+      std::vector<data_t> data_vector;
+      data_vector.clear();
+      for(size_t i=0; i<m_words; i++) data_vector.push_back(r_write_data[i].read());
+      m_trt.set( r_write_trt_index.read(),
+                 false,             // PUT request
+                 m_nline[(addr_t)(r_write_address.read())],
+                 0,                 // unused
+                 0,                 // unused
+                 0,                 // unused
+                 false,             // not a processor read
+                 0,                 // unused
+                 0,                 // unused
+                 std::vector<be_t> (m_words,0),
+                 data_vector );
 
       // invalidate directory entry
@@ -3796,11 +3839,8 @@
       entry.cache_coherent= false;
       entry.dirty         = false;
-      entry.tag         = 0;
+      entry.tag           = 0;
       entry.is_cnt        = false;
       entry.lock          = false;
       entry.owner.srcid   = 0;
-#if L1_MULTI_CACHE
-      entry.owner.cache_id= 0;
-#endif
       entry.owner.inst    = false;
       entry.ptr           = 0;
@@ -3813,4 +3853,5 @@
 #if DEBUG_MEMC_WRITE
 if(m_debug)
+          m_trt.print(0);
 std::cout << "  <MEMC " << name() << " WRITE_BC_DIR_INVAL> Invalidate the directory entry: @ = "
           << r_write_address.read() << " / register the put transaction in TRT:" << std::endl;
@@ -3851,13 +3892,9 @@
     case WRITE_BC_XRAM_REQ:   // Post a put request to IXR_CMD FSM
     {
-      if(!r_write_to_ixr_cmd_req)
+      if( not r_write_to_ixr_cmd_req.read() )
       {
         r_write_to_ixr_cmd_req     = true;
-        r_write_to_ixr_cmd_write   = true;
-        r_write_to_ixr_cmd_nline   = m_nline[(addr_t)(r_write_address.read())];
-        r_write_to_ixr_cmd_trdid   = r_write_trt_index.read();
-
-        for(size_t i=0; i<m_words; i++) r_write_to_ixr_cmd_data[i] = r_write_data[i];
-
+        r_write_to_ixr_cmd_put     = true;
+        r_write_to_ixr_cmd_index   = r_write_trt_index.read();
         r_write_fsm = WRITE_IDLE;
 
@@ -3876,16 +3913,19 @@
   ///////////////////////////////////////////////////////////////////////
   // The IXR_CMD fsm controls the command packets to the XRAM :
-  // It handles requests from the READ, WRITE, CAS, XRAM_RSP FSMs
-  // with a round-robin priority.
+  // It handles requests from 5 FSMs with a round-robin priority:
+  //  READ > WRITE > CAS > XRAM_RSP > CONFIG
   //
-  // - It sends a single flit VCI read request to the XRAM in case of MISS
-  // posted by the READ, WRITE or CAS FSMs : the TRDID field contains
-  // the Transaction Tab index.
-  // The VCI response is a multi-flit packet : the N cells contain
-  // the N data words.
+  // - It sends a single flit VCI read to the XRAM in case of
+  //   GET request posted by the READ, WRITE or CAS FSMs. 
+  // - It sends a multi-flit VCI write in case of PUT request posted by
+  //   the XRAM_RSP, WRITE, CAS, or CONFIG FSMs.
   //
-  // - It sends a multi-flit VCI write when the XRAM_RSP FSM, WRITE FSM
-  // or CAS FSM request to save a dirty line to the XRAM.
-  // The VCI response is a single flit packet.
+  // For each client, there is three steps:
+  // - IXR_CMD_*_IDLE : round-robin allocation to a client
+  // - IXR_CMD_*_TRT  : access to TRT for address and data
+  // - IXR_CMD_*_SEND : send the PUT or GET VCI command
+  //
+  // The address and data to be written (for a PUT) are stored in TRT.
+  // The trdid field contains always the TRT entry index.
   ////////////////////////////////////////////////////////////////////////
 
@@ -3894,184 +3934,324 @@
     ////////////////////////
     case IXR_CMD_READ_IDLE:
-      if     (r_write_to_ixr_cmd_req)    r_ixr_cmd_fsm = IXR_CMD_WRITE;
-      else if(r_cas_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_CAS;
-      else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM;
-      else if(r_cleanup_to_ixr_cmd_req)  r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA;
-      else if(r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ;
+      if     (r_write_to_ixr_cmd_req.read())      r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;
+      else if(r_cas_to_ixr_cmd_req.read())        r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;
+      else if(r_cleanup_to_ixr_cmd_req.read())    r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;
+      else if(r_xram_rsp_to_ixr_cmd_req.read())   r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;
+      else if(r_config_to_ixr_cmd_req.read())     r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;
+      else if(r_read_to_ixr_cmd_req.read())       r_ixr_cmd_fsm = IXR_CMD_READ_TRT;
       break;
     ////////////////////////
     case IXR_CMD_WRITE_IDLE:
-      if(r_cas_to_ixr_cmd_req)           r_ixr_cmd_fsm = IXR_CMD_CAS;
-      else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM;
-      else if(r_cleanup_to_ixr_cmd_req)  r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA;
-      else if(r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ;
-      else if(r_write_to_ixr_cmd_req)    r_ixr_cmd_fsm = IXR_CMD_WRITE;
+      if     (r_cas_to_ixr_cmd_req.read())        r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;
+      else if(r_cleanup_to_ixr_cmd_req.read())    r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;
+      else if(r_xram_rsp_to_ixr_cmd_req.read())   r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;
+      else if(r_config_to_ixr_cmd_req.read())     r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;
+      else if(r_read_to_ixr_cmd_req.read())       r_ixr_cmd_fsm = IXR_CMD_READ_TRT;
+      else if(r_write_to_ixr_cmd_req.read())      r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;
       break;
     ////////////////////////
     case IXR_CMD_CAS_IDLE:
-      if(r_xram_rsp_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_XRAM;
-      else if(r_cleanup_to_ixr_cmd_req)  r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA;
-      else if(r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ;
-      else if(r_write_to_ixr_cmd_req)    r_ixr_cmd_fsm = IXR_CMD_WRITE;
-      else if(r_cas_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_CAS;
+      if     (r_cleanup_to_ixr_cmd_req.read())    r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;
+      else if(r_xram_rsp_to_ixr_cmd_req.read())   r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;
+      else if(r_config_to_ixr_cmd_req.read())     r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;
+      else if(r_read_to_ixr_cmd_req.read())       r_ixr_cmd_fsm = IXR_CMD_READ_TRT;
+      else if(r_write_to_ixr_cmd_req.read())      r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;
+      else if(r_cas_to_ixr_cmd_req.read())        r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;
       break;
     ////////////////////////
     case IXR_CMD_XRAM_IDLE:
-      if(r_cleanup_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA;
-      else if(r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ;
-      else if(r_write_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_WRITE;
-      else if(r_cas_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_CAS;
-      else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM;
+      if     (r_config_to_ixr_cmd_req.read())     r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;
+      else if(r_read_to_ixr_cmd_req.read())       r_ixr_cmd_fsm = IXR_CMD_READ_TRT;
+      else if(r_write_to_ixr_cmd_req.read())      r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;
+      else if(r_cas_to_ixr_cmd_req.read())        r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;
+      else if(r_cleanup_to_ixr_cmd_req.read())    r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;
+      else if(r_xram_rsp_to_ixr_cmd_req.read())   r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;
       break;
       ////////////////////////
     case IXR_CMD_CLEANUP_IDLE:
       /*ODCCP*///std::cout << "IXR_CMD_CLEANUP_IDLE" << std::endl;
-      if(r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ;
-      else if(r_write_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_WRITE;
-      else if(r_cas_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_CAS;
-      else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM;
-      else if(r_cleanup_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA;
+      if     (r_read_to_ixr_cmd_req.read())       r_ixr_cmd_fsm = IXR_CMD_READ_TRT;
+      else if(r_write_to_ixr_cmd_req.read())      r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;
+      else if(r_cas_to_ixr_cmd_req.read())        r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;
+      else if(r_xram_rsp_to_ixr_cmd_req.read())   r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;
+      else if(r_config_to_ixr_cmd_req.read())     r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;
+      else if(r_cleanup_to_ixr_cmd_req)           r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;
       break;      
-    //////////////////       // send a get from READ FSM
-    case IXR_CMD_READ:
-    {
-      if(p_vci_ixr.cmdack)
-      {
-        r_ixr_cmd_fsm = IXR_CMD_READ_IDLE;
-        r_read_to_ixr_cmd_req = false;
+    /////////////////////////
+    case IXR_CMD_CONFIG_IDLE:
+    {
+      if     (r_read_to_ixr_cmd_req.read())       r_ixr_cmd_fsm = IXR_CMD_READ_TRT;
+      else if(r_write_to_ixr_cmd_req.read())      r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;
+      else if(r_cas_to_ixr_cmd_req.read())        r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;
+      else if(r_cleanup_to_ixr_cmd_req)           r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;
+      else if(r_xram_rsp_to_ixr_cmd_req.read())   r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;
+      else if(r_config_to_ixr_cmd_req.read())     r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;
+      break;
+    }
+ 
+    //////////////////////
+    case IXR_CMD_READ_TRT:       // access TRT for a GET
+    {
+        if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD )
+        {
+            TransactionTabEntry entry = m_trt.read( r_read_to_ixr_cmd_index.read() );
+            r_ixr_cmd_address = entry.nline * (m_words<<2);
+            r_ixr_cmd_trdid   = r_read_to_ixr_cmd_index.read();
+            r_ixr_cmd_get     = true;
+            r_ixr_cmd_word    = 0;
+            r_ixr_cmd_fsm     = IXR_CMD_READ_SEND;
+            for( size_t i=0 ; i<m_words ; i++ ) r_ixr_cmd_wdata[i] = entry.wdata[i];
 
 #if DEBUG_MEMC_IXR_CMD
 if(m_debug)
-std::cout << "  <MEMC " << name() << " IXR_CMD_READ>"
-          << " Send a get request to xram / address = " << std::hex
-          << (addr_t)(r_read_to_ixr_cmd_nline.read()*m_words*4) << std::endl;
-#endif
-      }
-      break;
-    }
-    ///////////////////
-    case IXR_CMD_WRITE:     // send a put or get from WRITE FSM
-    {
-      if(p_vci_ixr.cmdack)
-      {
-        if(r_write_to_ixr_cmd_write.read())   // PUT
-        {
-          if(r_ixr_cmd_cpt.read() == (m_words - 2))
-          {
-            r_ixr_cmd_cpt = 0;
-            r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE;
-            r_write_to_ixr_cmd_req = false;
-          }
-          else
-          {
-            r_ixr_cmd_cpt = r_ixr_cmd_cpt + 2;
-          }
+std::cout << "  <MEMC " << name() << " IXR_CMD_READ_TRT> TRT access"
+          << " index = " << std::dec << r_read_to_ixr_cmd_index.read()
+          << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl;
+#endif
+        }
+        break;
+    }
+    ///////////////////////
+    case IXR_CMD_WRITE_TRT:       // access TRT for a PUT or a GET
+    {
+        if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD )
+        {
+            TransactionTabEntry entry = m_trt.read( r_write_to_ixr_cmd_index.read() );
+            r_ixr_cmd_address = entry.nline * (m_words<<2);
+            r_ixr_cmd_trdid   = r_write_to_ixr_cmd_index.read();
+            r_ixr_cmd_get     = entry.xram_read;
+            r_ixr_cmd_word    = 0;
+            r_ixr_cmd_fsm     = IXR_CMD_WRITE_SEND;
+            for( size_t i=0 ; i<m_words ; i++ ) r_ixr_cmd_wdata[i] = entry.wdata[i];
 
 #if DEBUG_MEMC_IXR_CMD
 if(m_debug)
-std::cout << "  <MEMC " << name() << " IXR_CMD_WRITE>"
-          << " Send a put request to xram / address = " << std::hex
-          << (addr_t)((r_write_to_ixr_cmd_nline.read() * m_words +
-                      r_ixr_cmd_cpt.read()) * 4 ) << std::endl;
-#endif
-        }
-        else                                  // GET
-        {
-          r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE;
-          r_write_to_ixr_cmd_req = false;
+std::cout << "  <MEMC " << name() << " IXR_CMD_WRITE_TRT> TRT access"
+          << " index = " << std::dec << r_write_to_ixr_cmd_index.read()
+          << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl;
+#endif
+        }
+        break;
+    }
+    /////////////////////
+    case IXR_CMD_CAS_TRT:       // access TRT for a PUT or a GET 
+    {
+        if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD )
+        {
+            TransactionTabEntry entry = m_trt.read( r_cas_to_ixr_cmd_index.read() );
+            r_ixr_cmd_address = entry.nline * (m_words<<2);
+            r_ixr_cmd_trdid   = r_cas_to_ixr_cmd_index.read();
+            r_ixr_cmd_get     = entry.xram_read;
+            r_ixr_cmd_word    = 0;
+            r_ixr_cmd_fsm     = IXR_CMD_CAS_SEND;
+            for( size_t i=0 ; i<m_words ; i++ ) r_ixr_cmd_wdata[i] = entry.wdata[i];
 
 #if DEBUG_MEMC_IXR_CMD
 if(m_debug)
-std::cout << "  <MEMC " << name() << " IXR_CMD_WRITE>"
-          << " Send a get request to xram / address = " << std::hex
-          << (addr_t)(r_write_to_ixr_cmd_nline.read()*m_words*4) << std::endl;
-#endif
-        }
-      }
-      break;
-    }
-    /////////////////
-    case IXR_CMD_CAS:      // send a put or get command from CAS FSM
-    {
-      if(p_vci_ixr.cmdack)
-      {
-        if(r_cas_to_ixr_cmd_write.read()) // PUT
-        {
-          if(r_ixr_cmd_cpt.read() == (m_words - 2))
-          {
-            r_ixr_cmd_cpt = 0;
-            r_ixr_cmd_fsm = IXR_CMD_CAS_IDLE;
-            r_cas_to_ixr_cmd_req = false;
-          }
-          else
-          {
-            r_ixr_cmd_cpt = r_ixr_cmd_cpt + 2;
-          }
+std::cout << "  <MEMC " << name() << " IXR_CMD_CAS_TRT> TRT access"
+          << " index = " << std::dec << r_cas_to_ixr_cmd_index.read()
+          << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl;
+#endif
+        }
+        break;
+    }
+    //////////////////////
+    case IXR_CMD_XRAM_TRT:       // access TRT for a PUT 
+    {
+        if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD )
+        {
+            TransactionTabEntry entry = m_trt.read( r_xram_rsp_to_ixr_cmd_index.read() );
+            r_ixr_cmd_address = entry.nline * (m_words<<2);
+            r_ixr_cmd_trdid   = r_xram_rsp_to_ixr_cmd_index.read();
+            r_ixr_cmd_get     = false;
+            r_ixr_cmd_word    = 0;
+            r_ixr_cmd_fsm     = IXR_CMD_XRAM_SEND;
+            for( size_t i=0 ; i<m_words ; i++ ) r_ixr_cmd_wdata[i] = entry.wdata[i];
 
 #if DEBUG_MEMC_IXR_CMD
 if(m_debug)
-std::cout << "  <MEMC " << name() << " IXR_CMD_CAS>"
-          << " Send a put request to xram / address = " << std::hex
-          << (addr_t)( (r_cas_to_ixr_cmd_nline.read() * m_words +
-                      r_ixr_cmd_cpt.read()) * 4 ) << std::endl;
-#endif
-        }
-        else                            // GET
-        {
-          r_ixr_cmd_fsm = IXR_CMD_CAS_IDLE;
-          r_cas_to_ixr_cmd_req = false;
+std::cout << "  <MEMC " << name() << " IXR_CMD_XRAM_TRT> TRT access"
+          << " index = " << std::dec << r_xram_rsp_to_ixr_cmd_index.read()
+          << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl;
+#endif
+        }
+        break;
+    }
+    //////////////////////
+    case IXR_CMD_CLEANUP_TRT:       // access TRT for a PUT 
+    {
+        if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD )
+        {
+          
+            TransactionTabEntry entry = m_trt.read( r_cleanup_to_ixr_cmd_index.read() );
+            r_ixr_cmd_address = entry.nline * (m_words<<2);
+            r_ixr_cmd_trdid   = r_cleanup_to_ixr_cmd_index.read();
+            r_ixr_cmd_get     = false;
+            r_ixr_cmd_word    = 0;
+            r_ixr_cmd_fsm     = IXR_CMD_CLEANUP_DATA_SEND;
+            for( size_t i=0 ; i<m_words ; i++ ) r_ixr_cmd_wdata[i] = entry.wdata[i];
 
 #if DEBUG_MEMC_IXR_CMD
 if(m_debug)
-std::cout << "  <MEMC " << name() << " IXR_CMD_CAS>"
-          << " Send a get request to xram / address = " << std::hex
-          << (addr_t)(r_cas_to_ixr_cmd_nline.read()*m_words*4) << std::endl;
-#endif
-        }
-      }
-      break;
-    }
-    //////////////////
-    case IXR_CMD_XRAM:     // send a put from XRAM_RSP FSM
-    {
-      if(p_vci_ixr.cmdack)
-      {
-        if(r_ixr_cmd_cpt.read() == (m_words - 2))
-        {
-          r_ixr_cmd_cpt = 0;
-          r_ixr_cmd_fsm = IXR_CMD_XRAM_IDLE;
-          r_xram_rsp_to_ixr_cmd_req = false;
+std::cout << "  <MEMC " << name() << " IXR_CMD_CLEANUP_TRT> TRT access"
+          << " index = " << std::dec << r_cleanup_to_ixr_cmd_index.read()
+          << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl;
+#endif
+        }
+        break;
+    }
+    ////////////////////////
+    case IXR_CMD_CONFIG_TRT:       // access TRT for a PUT
+    {
+        if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD )
+        {
+            TransactionTabEntry entry = m_trt.read( r_config_to_ixr_cmd_index.read() );
+            r_ixr_cmd_address = entry.nline * (m_words<<2);
+            r_ixr_cmd_trdid   = r_config_to_ixr_cmd_index.read();
+            r_ixr_cmd_get     = false;
+            r_ixr_cmd_word    = 0;
+            r_ixr_cmd_fsm     = IXR_CMD_CONFIG_SEND;
+            for( size_t i=0 ; i<m_words ; i++ ) r_ixr_cmd_wdata[i] = entry.wdata[i];
+
+#if DEBUG_MEMC_IXR_CMD
+if(m_debug)
+std::cout << "  <MEMC " << name() << " IXR_CMD_CONFIG_TRT> TRT access"
+          << " index = " << std::dec << r_config_to_ixr_cmd_index.read()
+          << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl;
+#endif
+        }
+        break;
+    }
+
+    ///////////////////////
+    case IXR_CMD_READ_SEND:      // send a get from READ FSM
+    {
+        if(p_vci_ixr.cmdack)
+        {
+            r_ixr_cmd_fsm         = IXR_CMD_READ_IDLE;
+            r_read_to_ixr_cmd_req = false;
+
+#if DEBUG_MEMC_IXR_CMD
+if(m_debug)
+std::cout << "  <MEMC " << name() << " IXR_CMD_READ_SEND> GET request:" << std::hex
+          << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl;
+#endif
+        }
+        break;
+    }
+    ////////////////////////
+    case IXR_CMD_WRITE_SEND:     // send a put or get from WRITE FSM
+    {
+        if(p_vci_ixr.cmdack)
+        {
+            if(r_write_to_ixr_cmd_put.read())   // PUT
+            {
+                if(r_ixr_cmd_word.read() == (m_words - 2))
+                {
+                    r_ixr_cmd_fsm          = IXR_CMD_WRITE_IDLE;
+                    r_write_to_ixr_cmd_req = false;
+                }
+                else
+                {
+                    r_ixr_cmd_word = r_ixr_cmd_word.read() + 2;
+                }
+
+#if DEBUG_MEMC_IXR_CMD
+if(m_debug)
+std::cout << "  <MEMC " << name() << " IXR_CMD_WRITE_SEND> PUT request:" << std::hex
+          << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl;
+#endif
+            }
+            else                                  // GET
+            {
+                r_ixr_cmd_fsm          = IXR_CMD_WRITE_IDLE;
+                r_write_to_ixr_cmd_req = false;
+
+#if DEBUG_MEMC_IXR_CMD
+if(m_debug)
+std::cout << "  <MEMC " << name() << " IXR_CMD_WRITE_SEND> GET request:" << std::hex
+          << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl;
+#endif
+            }
+        }
+        break;
+    }
+    //////////////////////
+    case IXR_CMD_CAS_SEND:      // send a put or get command from CAS FSM
+    {
+        if(p_vci_ixr.cmdack)
+        {
+            if(r_cas_to_ixr_cmd_put.read()) // PUT
+            {
+                if(r_ixr_cmd_word.read() == (m_words - 2))
+                {
+                    r_ixr_cmd_fsm        = IXR_CMD_CAS_IDLE;
+                    r_cas_to_ixr_cmd_req = false;
+                }
+                else
+                {
+                    r_ixr_cmd_word = r_ixr_cmd_word.read() + 2;
+                }
+
+#if DEBUG_MEMC_IXR_CMD
+if(m_debug)
+std::cout << "  <MEMC " << name() << " IXR_CMD_CAS_SEND> PUT request:" << std::hex
+          << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl;
+#endif
+            }
+            else                            // GET
+            {
+                r_ixr_cmd_fsm        = IXR_CMD_CAS_IDLE;
+                r_cas_to_ixr_cmd_req = false;
+
+#if DEBUG_MEMC_IXR_CMD
+if(m_debug)
+std::cout << "  <MEMC " << name() << " IXR_CMD_CAS_SEND> GET request:" << std::hex
+          << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl;
+#endif
+            }
+        }
+        break;
+    }
+    ///////////////////////
+    case IXR_CMD_XRAM_SEND:     // send a put from XRAM_RSP FSM
+    {
+        if(p_vci_ixr.cmdack.read())
+        {
+            if(r_ixr_cmd_word.read() == (m_words - 2))
+            {
+                r_ixr_cmd_fsm = IXR_CMD_XRAM_IDLE;
+                r_xram_rsp_to_ixr_cmd_req = false;
+            }
+            else
+            {
+                r_ixr_cmd_word = r_ixr_cmd_word.read() + 2;
+            }
+#if DEBUG_MEMC_IXR_CMD
+if(m_debug)
+std::cout << "  <MEMC " << name() << " IXR_CMD_XRAM_SEND> PUT request:" << std::hex
+          << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl;
+#endif
+        }
+        break;
+    }
+
+      ////////////////////////
+    case IXR_CMD_CLEANUP_DATA_SEND:     // send a put command to XRAM
+    {
+      if(p_vci_ixr.cmdack.read())
+      {
+        /*ODCCP*/ //std::cout << "IXR_CMD_CLEANUP_DATA_SEND STATE at cycle : " << std::dec << m_cpt_cycles << std::endl;
+        if(r_ixr_cmd_word.read() == (m_words - 2))
+        {
+          /*ODCCP*/ //std::cout << "IXR_CMD_CLEANUP_DATA_SEND GO TO IXR_CMD_CLEANUP_IDLE" << std::endl;
+          r_ixr_cmd_fsm = IXR_CMD_CLEANUP_IDLE;
+          r_cleanup_to_ixr_cmd_req = false;
+          //r_ixr_cmd_word = 0;
+          //r_xram_rsp_to_ixr_cmd_inval_ncc_pending = false;
         }
         else
         {
-          r_ixr_cmd_cpt = r_ixr_cmd_cpt + 2;
-        }
-
-#if DEBUG_MEMC_IXR_CMD
-if(m_debug)
-std::cout << "  <MEMC " << name() << " IXR_CMD_XRAM>"
-          << " Send a put request to xram / address = " << std::hex
-          << (addr_t)( (r_xram_rsp_to_ixr_cmd_nline.read() * m_words +
-                       r_ixr_cmd_cpt.read()) * 4 ) << std::endl;
-#endif
-      }
-      break;
-    }
-
-      ////////////////////////
-    case IXR_CMD_CLEANUP_DATA:     // send a put command to XRAM
-      /*ODCCP*///std::cout << "IXR_CMD_CLEANUP_DATA" << std::endl;
-      if(p_vci_ixr.cmdack)
-      {
-        if(r_ixr_cmd_cpt.read() == (m_words - 2))
-        {
-          r_ixr_cmd_cpt = 0;
-          r_ixr_cmd_fsm = IXR_CMD_CLEANUP_IDLE;
-          r_xram_rsp_to_ixr_cmd_inval_ncc_pending = false;
-          r_cleanup_to_ixr_cmd_req = false;
-        }
-        else
-        {
-          r_ixr_cmd_cpt = r_ixr_cmd_cpt.read() + 2;
+          r_ixr_cmd_word = r_ixr_cmd_word.read() + 2;
         }
 
@@ -4079,10 +4259,34 @@
         if(m_debug)
         {
-          std::cout << "  <MEMC " << name() << ".IXR_CMD_CLEANUP_DATA> Send a put request to xram" << std::endl;
-        }
-#endif
-      }
-      break;
-
+          std::cout << "  <MEMC " << name() << ".IXR_CMD_CLEANUP_DATA_SEND> Send a put request to xram" << std::endl;
+        }
+#endif
+      }
+      break;
+    }
+
+    /////////////////////////
+    case IXR_CMD_CONFIG_SEND:     // send a put from CONFIG FSM
+    {
+        if(p_vci_ixr.cmdack.read())
+        {
+            if(r_ixr_cmd_word.read() == (m_words - 2))
+            {
+                r_ixr_cmd_fsm = IXR_CMD_CONFIG_IDLE;
+                r_config_to_ixr_cmd_req = false;
+            }
+            else
+            {
+                r_ixr_cmd_word = r_ixr_cmd_word.read() + 2;
+            }
+
+#if DEBUG_MEMC_IXR_CMD
+if(m_debug)
+std::cout << "  <MEMC " << name() << " IXR_CMD_CONFIG_SEND> PUT request:" << std::hex
+          << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl;
+#endif
+        }
+        break;
+    }
   } // end switch r_ixr_cmd_fsm
 
@@ -4091,17 +4295,19 @@
   ////////////////////////////////////////////////////////////////////////////
   // The IXR_RSP FSM receives the response packets from the XRAM,
-  // for both put transaction, and get transaction.
+  // for both PUT transaction, and GET transaction.
   //
-  // - A response to a put request is a single-cell VCI packet.
-  // The Transaction Tab index is contained in the RTRDID field.
+  // - A response to a PUT request is a single-cell VCI packet.
+  // The TRT index is contained in the RTRDID field.
   // The FSM takes the lock protecting the TRT, and the corresponding
-  // entry is erased.
+  // entry is erased. If an acknowledge was required (in case of software SYNC)
+  // the r_config_rsp_lines counter is decremented.  
   //
-  // - A response to a get request is a multi-cell VCI packet.
-  // The Transaction Tab index is contained in the RTRDID field.
+  // - A response to a GET request is a multi-cell VCI packet.
+  // The TRT index is contained in the RTRDID field.
   // The N cells contain the N words of the cache line in the RDATA field.
   // The FSM takes the lock protecting the TRT to store the line in the TRT
   // (taking into account the write requests already stored in the TRT).
-  // When the line is completely written, the corresponding rok signal is set.
+  // When the line is completely written, the r_ixr_rsp_to_xram_rsp_rok[index]  
+  // signal is set to inform the XRAM_RSP FSM.
   ///////////////////////////////////////////////////////////////////////////////
 
@@ -4111,21 +4317,20 @@
     case IXR_RSP_IDLE:  // test transaction type: PUT/GET
     {
-      if(p_vci_ixr.rspval.read())
-      {
-        r_ixr_rsp_cpt   = 0;
-        r_ixr_rsp_trt_index = p_vci_ixr.rtrdid.read();
-        if(p_vci_ixr.reop.read() and !(p_vci_ixr.rerror.read() &0x1))   // PUT transaction
-        {
-          r_ixr_rsp_fsm = IXR_RSP_ACK;
-
-#if DEBUG_MEMC_IXR_RSP
-if(m_debug)
-std::cout << "  <MEMC " << name()
-          << " IXR_RSP_IDLE> Response from XRAM to a put transaction" << std::endl;
-#endif
-        }
-        else                                                         // GET transaction
-        {
-          r_ixr_rsp_fsm = IXR_RSP_TRT_READ;
+          if(p_vci_ixr.rspval.read())
+          {
+              r_ixr_rsp_cpt       = 0;
+              r_ixr_rsp_trt_index = p_vci_ixr.rtrdid.read();
+
+              assert( ((p_vci_ixr.rerror.read() & 0x1) == 0) and
+              "MEMC ERROR in IXR_RSP state: XRAM response error !");
+
+              if(p_vci_ixr.reop.read())   // PUT
+              {
+                  r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE;
+              }
+
+              else                       // GET transaction
+              {
+                  r_ixr_rsp_fsm = IXR_RSP_TRT_READ;
 
 #if DEBUG_MEMC_IXR_RSP
@@ -4134,27 +4339,27 @@
           << " IXR_RSP_IDLE> Response from XRAM to a get transaction" << std::endl;
 #endif
-        }
-      }
-      break;
-    }
-    /////////////////
-    case IXR_RSP_ACK:        // Aknowledge the VCI response for a PUT
-    {
-      if(p_vci_ixr.rspval.read()) r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE;
-
-#if DEBUG_MEMC_IXR_RSP
-if(m_debug)
-std::cout << "  <MEMC " << name() << " IXR_RSP_ACK>" << std::endl;
-#endif
+              }     
+          } 
       break;
     }
     ////////////////////////
+    case IXR_RSP_ACK:     // Acknowledge PUT transaction
+    {
+        r_ixr_rsp_fsm = IXR_RSP_IDLE;
+        break;
+    }
+
+   ////////////////////////
     case IXR_RSP_TRT_ERASE:   // erase the entry in the TRT
-    {
-      if(r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP)
-      {
-        m_trt.erase(r_ixr_rsp_trt_index.read());
-        r_ixr_rsp_fsm = IXR_RSP_IDLE;
-
+                              // decrease the line counter if config request
+    {
+        if(r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP)
+        {
+            size_t  index = r_ixr_rsp_trt_index.read(); 
+            if (m_trt.is_config(index) ) r_config_rsp_lines = r_config_rsp_lines.read() - 1;
+            m_trt.erase(index);
+            r_ixr_rsp_fsm = IXR_RSP_IDLE;
+
+//            std::cout << "remove a valid slot in trt index = " << r_ixr_rsp_trt_index.read()<< std::endl;
 #if DEBUG_MEMC_IXR_RSP
 if(m_debug)
@@ -4162,36 +4367,32 @@
           << r_ixr_rsp_trt_index.read() << std::endl;
 #endif
-      m_cpt_ixr_fsm_n_trt_lock++;
-      }
-
-      m_cpt_ixr_fsm_trt_lock++;
-
-      break;
+        }
+        break;
     }
     //////////////////////
     case IXR_RSP_TRT_READ:    // write a 64 bits data in the TRT
     {
-      if((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) and  p_vci_ixr.rspval)
-      {
-        size_t      index    = r_ixr_rsp_trt_index.read();
-        bool        eop      = p_vci_ixr.reop.read();
-        wide_data_t data     = p_vci_ixr.rdata.read();
-        bool        error    = ((p_vci_ixr.rerror.read() & 0x1) == 1);
-
-        assert(((eop == (r_ixr_rsp_cpt.read() == (m_words-2))) or p_vci_ixr.rerror.read())
-               and "Error in VCI_MEM_CACHE : invalid length for a response from XRAM");
-
-        m_trt.write_rsp( index,
-                         r_ixr_rsp_cpt.read(),
-                         data,
-                         error);
-
-        r_ixr_rsp_cpt = r_ixr_rsp_cpt.read() + 2;
-
-        if(eop)
-        {
-          r_ixr_rsp_to_xram_rsp_rok[r_ixr_rsp_trt_index.read()]=true;
-          r_ixr_rsp_fsm = IXR_RSP_IDLE;
-        }
+          if((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) and  p_vci_ixr.rspval)
+          {
+              size_t      index    = r_ixr_rsp_trt_index.read();
+              size_t      word     = r_ixr_rsp_cpt.read();
+              bool        eop      = p_vci_ixr.reop.read();
+              wide_data_t data     = p_vci_ixr.rdata.read();
+              bool        error    = ((p_vci_ixr.rerror.read() & 0x1) == 1);
+
+              assert(((eop == (word == (m_words-2))) or error) and
+              "MEMC ERROR in IXR_RSP_TRT_READ state : invalid response from XRAM");
+ 
+              m_trt.write_rsp( index,
+                               word,
+                               data );
+
+              r_ixr_rsp_cpt = word + 2;
+
+              if(eop)
+              {
+                r_ixr_rsp_to_xram_rsp_rok[r_ixr_rsp_trt_index.read()]=true;
+                r_ixr_rsp_fsm = IXR_RSP_IDLE;
+              }
 
 #if DEBUG_MEMC_IXR_RSP
@@ -4199,5 +4400,5 @@
 std::cout << "  <MEMC " << name() << " IXR_RSP_TRT_READ> Writing a word in TRT : "
           << " index = " << std::dec << index
-          << " / word = " << r_ixr_rsp_cpt.read()
+          << " / word = " << word
           << " / data = " << std::hex << data << std::endl;
 #endif
@@ -4212,15 +4413,15 @@
   //                XRAM_RSP FSM
   ////////////////////////////////////////////////////////////////////////////
-  // The XRAM_RSP FSM handles the incoming cache lines from the XRAM.
+  // The XRAM_RSP FSM handles the incoming cache lines after an XRAM GET.
   // The cache line has been written in the TRT by the IXR_CMD_FSM.
   // As the IXR_RSP FSM and the XRAM_RSP FSM are running in parallel,
-  // there is as many flip-flops r_ixr_rsp_to_xram_rsp_rok[i]
-  // as the number of entries in the TRT, that are handled with
-  // a round-robin priority...
+  // there is as many flip-flops r_ixr_rsp_to_xram_rsp_rok[i] as the number 
+  // of entries in the TRT, that are handled with a round-robin priority...
   //
-  // When a response is available, the corresponding TRT entry
-  // is copied in a local buffer to be written in the cache.
-  // The FSM takes the lock protecting the TRT, and the lock protecting the DIR.
-  // It selects a cache slot and writes the line in the cache.
+  // The FSM takes the lock protecting TRT, and the lock protecting DIR.
+  // The selected TRT entry is copied in the local buffer r_xram_rsp_trt_buf.
+  // It selects a cache slot and save the victim line in another local buffer
+  // r_xram_rsp_victim_***.
+  // It writes the line extracted from TRT in the cache.
   // If it was a read MISS, the XRAM_RSP FSM send a request to the TGT_RSP
   // FSM to return the cache line to the registered processor.
@@ -4237,14 +4438,14 @@
     case XRAM_RSP_IDLE: // scan the XRAM responses / select a TRT index (round robin)
     {
-      size_t ptr   = r_xram_rsp_trt_index.read();
-      size_t lines = m_trt_lines;
-      for(size_t i=0 ; i<lines ; i++)
-      {
-        size_t index = (i+ptr+1) %lines;
-        if(r_ixr_rsp_to_xram_rsp_rok[index])
-        {
-          r_xram_rsp_trt_index             = index;
-          r_ixr_rsp_to_xram_rsp_rok[index] = false;
-          r_xram_rsp_fsm                   = XRAM_RSP_DIR_LOCK;
+        size_t old   = r_xram_rsp_trt_index.read();
+        size_t lines = m_trt_lines;
+        for(size_t i=0 ; i<lines ; i++)
+        {
+            size_t index = (i+old+1) %lines;
+            if(r_ixr_rsp_to_xram_rsp_rok[index])
+            {
+                r_xram_rsp_trt_index             = index;
+                r_ixr_rsp_to_xram_rsp_rok[index] = false;
+                r_xram_rsp_fsm                   = XRAM_RSP_DIR_LOCK;
 
 #if DEBUG_MEMC_XRAM_RSP
@@ -4254,7 +4455,7 @@
           << " index = " << std::dec << index << std::endl;
 #endif
-          break;
-        }
-      }
+                break;
+            }
+        } 
       break;
     }
@@ -4269,5 +4470,4 @@
         size_t  index = r_xram_rsp_trt_index.read();
         r_xram_rsp_trt_buf.copy( m_trt.read(index) );
-
         r_xram_rsp_fsm = XRAM_RSP_TRT_COPY;
 
@@ -4288,7 +4488,10 @@
                             // and copy it in a local buffer
     {
-      if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) and
-           (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) )
-      {
+        assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and
+        "MEMC ERROR in XRAM_RSP_TRT_COPY state: Bad DIR allocation");
+
+        assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) and
+        "MEMC ERROR in XRAM_RSP_TRT_COPY state: Bad TRT allocation");
+
         // selects & extracts a victim line from cache
         size_t way = 0;
@@ -4319,86 +4522,65 @@
         r_xram_rsp_victim_dirty     = victim.dirty or (!victim.cache_coherent && (victim.count == 1)); //a NCC line is by default considered as dirty in the L1: we must take a reservation on a TRT entry
 
-
-        if(!r_xram_rsp_trt_buf.rerror)
-        {
-          if (!victim.cache_coherent and r_xram_rsp_to_ixr_cmd_inval_ncc_pending.read()) //there can not be two L2 invalidation on NCC line at the same time
-          {
-            r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
-          }
-          else
-          {
-            r_xram_rsp_fsm = XRAM_RSP_INVAL_LOCK;
-          }
-        }
-        else
-        {
-          r_xram_rsp_fsm = XRAM_RSP_ERROR_ERASE;
-        }
-
-#if DEBUG_MEMC_XRAM_RSP
+        if( not r_xram_rsp_trt_buf.rerror ) r_xram_rsp_fsm = XRAM_RSP_IVT_LOCK;
+        else                                r_xram_rsp_fsm = XRAM_RSP_ERROR_ERASE;
+
+ #if DEBUG_MEMC_XRAM_RSP
 if(m_debug)
 std::cout << "  <MEMC " << name() << " XRAM_RSP_TRT_COPY>"
-          << " Select a slot: "
+          << " Select a victim slot: "
           << " way = " << std::dec << way
           << " / set = " << set
           << " / inval_required = " << inval << std::endl;
 #endif
-      }
-      else
-      {
-        std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_TRT_COPY"
-                  << " bad TRT or DIR allocation" << std::endl;
-        exit(0);
-      }
-      break;
-    }
-    /////////////////////////
-    case XRAM_RSP_INVAL_LOCK: // Take the IVT lock to check a possible pending inval
-    {
-      if(r_alloc_ivt_fsm == ALLOC_IVT_XRAM_RSP)
-      {
-        size_t index = 0;
-        size_t index_victim = 0;
-        if(m_ivt.search_inval(r_xram_rsp_trt_buf.nline, index) or
-           m_ivt.search_inval(r_xram_rsp_victim_nline.read(), index_victim))
-        {
-          r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
+        break;
+    }
+    ///////////////////////
+    case XRAM_RSP_IVT_LOCK:   // Keep DIR and TRT locks and take the IVT lock 
+                              // to check a possible pending inval
+    {
+        assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and
+        "MEMC ERROR in XRAM_RSP_IVT_LOCK state: Bad DIR allocation");
+
+        assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) and
+        "MEMC ERROR in XRAM_RSP_IVT_LOCK state: Bad TRT allocation");
+
+        if(r_alloc_ivt_fsm == ALLOC_IVT_XRAM_RSP)
+        {
+            size_t index = 0;
+            if(m_ivt.search_inval(r_xram_rsp_trt_buf.nline, index))  // pending inval
+            {
+                r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
 
 #if DEBUG_MEMC_XRAM_RSP
 if(m_debug)
-std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL_LOCK>"
+std::cout << "  <MEMC " << name() << " XRAM_RSP_IVT_LOCK>"
           << " Get acces to IVT, but line invalidation registered"
-          << " / nline = " << std::hex << r_xram_rsp_trt_buf.nline
+          << " / address = " << std::hex << r_xram_rsp_trt_buf.nline*m_words*4
           << " / index = " << std::dec << index << std::endl;
 #endif
 
-        }
-        else if(m_ivt.is_full() and r_xram_rsp_victim_inval.read()) // IVT full
-        {
-          r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
-          m_upt.print();
+            }
+            else if(m_ivt.is_full() and r_xram_rsp_victim_inval.read()) // IVT full
+            {
+                r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
 
 #if DEBUG_MEMC_XRAM_RSP
 if(m_debug)
-std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL_LOCK>"
+std::cout << "  <MEMC " << name() << " XRAM_RSP_IVT_LOCK>"
           << " Get acces to IVT, but inval required and IVT full" << std::endl;
 #endif
-        }
-        else
-        {
-          r_xram_rsp_fsm = XRAM_RSP_DIR_UPDT;
+            }
+            else
+            {
+                r_xram_rsp_fsm = XRAM_RSP_DIR_UPDT;
 
 #if DEBUG_MEMC_XRAM_RSP
 if(m_debug)
-std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL_LOCK>"
-          << " Get acces to IVT" << std::endl;
-#endif
-        }
-        m_cpt_xram_rsp_fsm_n_upt_lock++;
-      }
-
-      m_cpt_xram_rsp_fsm_upt_lock++;
-
-      break;
+std::cout << "  <MEMC " << name() << " XRAM_RSP_IVT_LOCK>"
+          << " Get acces to IVT / no pending inval request" << std::endl;
+#endif
+            }
+        }
+        break;
     }
     /////////////////////////
@@ -4415,34 +4597,39 @@
     }
     ///////////////////////
-    case XRAM_RSP_DIR_UPDT:   // updates the cache (both data & directory)
-                              // and possibly set an inval request in IVT
-    {
-      // check if this is an instruction read, this means pktid is either
-      // TYPE_READ_INS_UNC   0bX010 with TSAR encoding
-      // TYPE_READ_INS_MISS  0bX011 with TSAR encoding
-      bool inst_read = (r_xram_rsp_trt_buf.pktid & 0x2) and r_xram_rsp_trt_buf.proc_read;
-
-      // check if this is a cached read, this means pktid is either
-      // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding
-      // TYPE_READ_INS_MISS  0bX011 with TSAR encoding
-      bool cached_read = (r_xram_rsp_trt_buf.pktid & 0x1) and r_xram_rsp_trt_buf.proc_read;
-
-      bool dirty = false;
-
-      // update cache data
-      size_t set   = r_xram_rsp_victim_set.read();
-      size_t way   = r_xram_rsp_victim_way.read();
-      for(size_t word=0; word<m_words ; word++)
-      {
-        m_cache_data.write(way, set, word, r_xram_rsp_trt_buf.wdata[word]);
-
-        dirty = dirty or (r_xram_rsp_trt_buf.wdata_be[word] != 0);
-
-        if(m_monitor_ok)
-        {
-          addr_t address = r_xram_rsp_trt_buf.nline<<6 | word<<2;
-          check_monitor( address, r_xram_rsp_trt_buf.wdata[word], false);
-        }
-      }
+    case XRAM_RSP_DIR_UPDT:   // updates the cache (both data & directory),
+                              // erases the TRT entry if victim not dirty,
+                              // and set inval request in IVT if required
+    {
+        assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and
+        "MEMC ERROR in XRAM_RSP_DIR_UPDT state: Bad DIR allocation");
+
+        assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) and
+        "MEMC ERROR in XRAM_RSP_DIR_UPDT state: Bad TRT allocation");
+ 
+        assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_XRAM_RSP) and
+        "MEMC ERROR in XRAM_RSP_DIR_UPDT state: Bad IVT allocation");
+
+        // check if this is an instruction read, this means pktid is either
+        // TYPE_READ_INS_UNC   0bX010 with TSAR encoding
+        // TYPE_READ_INS_MISS  0bX011 with TSAR encoding
+
+        // check if this is a cached read, this means pktid is either
+        // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding
+        // TYPE_READ_INS_MISS  0bX011 with TSAR encoding
+        bool cached_read = (r_xram_rsp_trt_buf.pktid & 0x1) and r_xram_rsp_trt_buf.proc_read;
+ 
+        bool inst_read = (r_xram_rsp_trt_buf.pktid & 0x2) and r_xram_rsp_trt_buf.proc_read;
+ 
+        bool dirty = false;
+
+        // update cache data
+        size_t set   = r_xram_rsp_victim_set.read();
+        size_t way   = r_xram_rsp_victim_way.read();
+        for(size_t word=0; word<m_words ; word++)
+        {
+          m_cache_data.write(way, set, word, r_xram_rsp_trt_buf.wdata[word]);
+          dirty = dirty or (r_xram_rsp_trt_buf.wdata_be[word] != 0);
+
+        }
 
       // update cache directory
@@ -4458,7 +4645,4 @@
       {
         entry.owner.srcid   = r_xram_rsp_trt_buf.srcid;
-#if L1_MULTI_CACHE
-        entry.owner.cache_id= r_xram_rsp_trt_buf.pktid;
-#endif
         entry.owner.inst    = inst_read;
         entry.count         = 1;
@@ -4466,8 +4650,5 @@
       else
       {
-        entry.owner.srcid    = r_xram_rsp_trt_buf.srcid;
-#if L1_MULTI_CACHE
-        entry.owner.cache_id = 0;
-#endif
+        entry.owner.srcid    = 0;
         entry.owner.inst     = 0;
         entry.count          = 0;
@@ -4495,15 +4676,12 @@
 
         r_xram_rsp_ivt_index = index;
-        if(!wok)
-        {
-          std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_DIR_UPDT"
-                    << " invalidate_tab entry free but write unsuccessful" << std::endl;
-          exit(0);
-        }
+        assert( wok and
+        "MEMC ERROR in XRAM_RSP_DIR_UPDT state: IVT should not be full"); 
+ 
       }
       if (!r_xram_rsp_victim_coherent.read())
       {
         //m_llsc_table.sw(r_xram_rsp_victim_nline.read()*m_words*4);
-        m_llsc_table.sw(r_xram_rsp_victim_nline.read());
+        m_llsc_table.sw(r_xram_rsp_victim_nline.read(), 0, m_words - 1);
       }
 #if DEBUG_MEMC_XRAM_RSP
@@ -4539,25 +4717,33 @@
     case XRAM_RSP_TRT_DIRTY:  // set the TRT entry (write to XRAM) if the victim is dirty or not coherent (RWT)
     {
-      if(r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP)
-      {
-
-        m_trt.set(r_xram_rsp_trt_index.read(),
-                              false,       // write to XRAM
-                              r_xram_rsp_victim_nline.read(),  // line index
-                              0,
-                              0,
-                              0,
-                              false,
-                              0,
-                              0,
-                              std::vector<be_t> (m_words,0),
-                              std::vector<data_t> (m_words,0));
-
-#if DEBUG_MEMC_XRAM_RSP
-if(m_debug)
+        if(r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP)
+        {
+            std::vector<data_t> data_vector;
+            data_vector.clear();
+            for(size_t i=0; i<m_words; i++)
+            {
+                data_vector.push_back(r_xram_rsp_victim_data[i].read());
+            }
+            m_trt.set( r_xram_rsp_trt_index.read(),
+                       false,                             // PUT
+                       r_xram_rsp_victim_nline.read(),    // line index
+                       0,                                 // unused
+                       0,                                 // unused
+                       0,                                 // unused
+                       false,                             // not proc_read
+                       0,                                 // unused
+                       0,                                 // unused
+                       std::vector<be_t>(m_words,0xF),                         
+                       data_vector);
+ #if DEBUG_MEMC_XRAM_RSP
+if(m_debug)
+            m_trt.print(0);
 std::cout << "  <MEMC " << name() << " XRAM_RSP_TRT_DIRTY>"
           << " Set TRT entry for the put transaction"
           << " / dirty victim line = " << r_xram_rsp_victim_nline.read() << std::endl;
 #endif
+        
+        if( not r_xram_rsp_victim_coherent )
+            std::cout << "a victim coherent not sent trt index =" << r_xram_rsp_trt_index.read() << std::endl;
         if(r_xram_rsp_trt_buf.proc_read)         r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
         else if(r_xram_rsp_victim_inval.read())  r_xram_rsp_fsm = XRAM_RSP_INVAL;
@@ -4573,5 +4759,5 @@
     case XRAM_RSP_DIR_RSP:     // Request a response to TGT_RSP FSM
     {
-      if(!r_xram_rsp_to_tgt_rsp_req.read())
+      if( not r_xram_rsp_to_tgt_rsp_req.read())
       {
         r_xram_rsp_to_tgt_rsp_srcid = r_xram_rsp_trt_buf.srcid;
@@ -4627,19 +4813,17 @@
         xram_rsp_to_cc_send_fifo_srcid     = r_xram_rsp_victim_copy.read();
         xram_rsp_to_cc_send_fifo_inst      = r_xram_rsp_victim_copy_inst.read();
-#if L1_MULTI_CACHE
-        xram_rsp_to_cc_send_fifo_cache_id  = r_xram_rsp_victim_copy_cache.read();
-#endif
         xram_rsp_to_cc_send_fifo_put       = multi_req;
-        r_xram_rsp_next_ptr                 = r_xram_rsp_victim_ptr.read();
-
-        if(r_xram_rsp_victim_dirty)  r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
+        r_xram_rsp_next_ptr                = r_xram_rsp_victim_ptr.read();
+
+        if(r_xram_rsp_victim_dirty and r_xram_rsp_victim_coherent)  r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
         else if(not_last_multi_req)  r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ;
         else                         r_xram_rsp_fsm = XRAM_RSP_IDLE;
 
+// std::cout << "cleanup sent for trt index =" << r_xram_rsp_trt_index.read() << std::endl;
 #if DEBUG_MEMC_XRAM_RSP
 if(m_debug)
 std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL>"
           << " Send an inval request to CC_SEND FSM"
-          << " / victim line = " << r_xram_rsp_victim_nline.read() << std::endl;
+          << " / address = " << r_xram_rsp_victim_nline.read()*m_words*4 << std::endl;
 #endif
       }
@@ -4649,29 +4833,17 @@
     case XRAM_RSP_WRITE_DIRTY:  // send a write request to IXR_CMD FSM
     {
-      if(!r_xram_rsp_to_ixr_cmd_req.read() and !r_xram_rsp_to_ixr_cmd_inval_ncc_pending.read())
-      {
-        r_xram_rsp_to_ixr_cmd_req = true;
-        r_xram_rsp_to_ixr_cmd_nline = r_xram_rsp_victim_nline.read();
-        r_xram_rsp_to_ixr_cmd_trdid = r_xram_rsp_trt_index.read();
-        for(size_t i=0; i<m_words ; i++)
-        {
-            r_xram_rsp_to_ixr_cmd_data[i] = r_xram_rsp_victim_data[i];
-              std::cout << "data L2 = " << std::hex << r_xram_rsp_victim_data[i] << std::dec << std::endl;
-        }
-        m_cpt_write_dirty++;
+        if ( not r_xram_rsp_to_ixr_cmd_req.read() )
+        {
+            r_xram_rsp_to_ixr_cmd_req = true;
+            r_xram_rsp_to_ixr_cmd_index = r_xram_rsp_trt_index.read();
+ 
+            m_cpt_write_dirty++;
         
-        if ((!r_xram_rsp_victim_coherent.read()) and (r_xram_rsp_victim_count.read() == 1)) //if NCC, we save the data in case of not dirty L1
-        {
-          r_xram_rsp_to_ixr_cmd_req = false;
-          r_xram_rsp_to_ixr_cmd_inval_ncc_pending = true;
-          r_xram_rsp_fsm = XRAM_RSP_IDLE;
-          break;
-        }
-
-        bool multi_req = !r_xram_rsp_victim_is_cnt.read() and r_xram_rsp_victim_inval.read();
-        bool not_last_multi_req = multi_req and (r_xram_rsp_victim_count.read() != 1);
-
-        if(not_last_multi_req)   r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ;
-        else                     r_xram_rsp_fsm = XRAM_RSP_IDLE;
+            bool multi_req = not r_xram_rsp_victim_is_cnt.read() and 
+              r_xram_rsp_victim_inval.read();
+            bool not_last_multi_req = multi_req and (r_xram_rsp_victim_count.read() != 1);
+
+            if(not_last_multi_req)   r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ;
+            else                     r_xram_rsp_fsm = XRAM_RSP_IDLE;
 
 #if DEBUG_MEMC_XRAM_RSP
@@ -4681,6 +4853,6 @@
           << " / victim line = " << r_xram_rsp_victim_nline.read() << std::endl;
 #endif
-      }
-      break;
+         }
+        break;
     }
     /////////////////////////
@@ -4711,7 +4883,4 @@
 
         xram_rsp_to_cc_send_fifo_srcid    = entry.owner.srcid;
-#if L1_MULTI_CACHE
-        xram_rsp_to_cc_send_fifo_cache_id = entry.owner.cache_id;
-#endif
         xram_rsp_to_cc_send_fifo_inst  = entry.owner.inst;
         xram_rsp_to_cc_send_fifo_put   = true;
@@ -4757,7 +4926,4 @@
       HeapEntry last_entry;
       last_entry.owner.srcid    = 0;
-#if L1_MULTI_CACHE
-      last_entry.owner.cache_id = 0;
-#endif
       last_entry.owner.inst     = false;
       if(m_heap.is_full())
@@ -4783,5 +4949,5 @@
       break;
     }
-    // ///////////////////////
+    /////////////////////////
     case XRAM_RSP_ERROR_ERASE:  // erase TRT entry in case of error
     {
@@ -4873,13 +5039,6 @@
       r_cleanup_contains_data = false;
 
-      if(srcid >= m_initiators)
-      {
-        std::cout
-            << "VCI_MEM_CACHE ERROR " << name()
-            << " CLEANUP_IDLE state"  << std::endl
-            << "illegal srcid for cleanup request" << std::endl;
-
-        exit(0);
-      }
+      assert( (srcid < m_initiators) and
+      "MEMC ERROR in CLEANUP_IDLE state : illegal SRCID value");
 
       m_cpt_cleanup++;
@@ -5026,7 +5185,4 @@
       r_cleanup_copy         = entry.owner.srcid;
       r_cleanup_copy_inst    = entry.owner.inst;
-#if L1_MULTI_CACHE
-      r_cleanup_copy_cache   = entry.owner.cache_id;
-#endif
 
       //RWT
@@ -5034,6 +5190,4 @@
       m_cache_data.read_line(way, set, r_cleanup_old_data); 
       r_cleanup_coherent = entry.cache_coherent;
-
-
 
       if(entry.valid)      // hit : the copy must be cleared
@@ -5101,8 +5255,4 @@
       bool   match_srcid = (r_cleanup_copy.read() == r_cleanup_srcid.read());
 
-#if L1_MULTI_CACHE
-      match_srcid       &= (r_cleanup_copy_cache.read() == r_cleanup_pktid.read());
-#endif
-
       bool   match_inst  = (r_cleanup_copy_inst.read() == r_cleanup_inst.read());
       bool   match       = match_srcid and match_inst;
@@ -5149,7 +5299,4 @@
           entry.owner.srcid    = r_read_to_cleanup_srcid.read();
           entry.owner.inst     = 0;
-#if L1_MULTI_CACHE
-          entry.owner.cache_id = r_cleanup_copy_cache.read();
-#endif
         }
         else
@@ -5158,7 +5305,4 @@
           entry.owner.srcid    = r_cleanup_copy.read();
           entry.owner.inst     = r_cleanup_copy_inst.read();
-#if L1_MULTI_CACHE
-          entry.owner.cache_id = r_cleanup_copy_cache.read();
-#endif
         }
         if (r_read_to_cleanup_is_ll.read())
@@ -5172,9 +5316,5 @@
         entry.owner.srcid    = 0;
         entry.owner.inst     = 0;
-#if L1_MULTI_CACHE
-        entry.owner.cache_id = 0;
-#endif
-      }
-
+      }
 
       if (r_cleanup_contains_data.read())
@@ -5184,11 +5324,9 @@
           m_cache_data.write(way, set, word, r_cleanup_data[word].read(), 0xF);
         }
-        m_llsc_table.sw(r_cleanup_nline.read());
+        m_llsc_table.sw(r_cleanup_nline.read(), 0 , m_words - 1);
         //m_llsc_table.sw(r_cleanup_nline.read()*m_words*4);
       }
 
-
       m_cache_directory.write(set, way, entry);
-
 
       /*RWT*/
@@ -5346,13 +5484,6 @@
       // 1. the matching copy is directly in the directory
       // 2. the matching copy is the first copy in the heap
-      if(r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP)
-      {
-        std::cout
-            << "VCI_MEM_CACHE ERROR " << name()
-            << " CLEANUP_HEAP_LOCK state"
-            << " bad HEAP allocation" << std::endl;
-
-        exit(0);
-      }
+      assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and
+      "MEMC ERROR in CLEANUP_HEAP_LOCK state: bad HEAP allocation");
 
       size_t way            = r_cleanup_way.read();
@@ -5376,49 +5507,9 @@
       r_cleanup_prev_inst   = heap_entry.owner.inst;
 
-#if L1_MULTI_CACHE
-      match_dir  = match_dir  and(r_cleanup_copy_cache.read() == r_cleanup_pktid.read());
-      match_heap = match_heap and(heap_entry.owner.cache_id   == r_cleanup_pktid.read());
-      r_cleanup_prev_cache_id = heap_entry.owner.cache_id;
-#endif
-
-      if(not match_dir and not match_heap and last)
-      {
-        std::cout
-            << "VCI_MEM_CACHE ERROR " << name()
-            << " CLEANUP_HEAP_LOCK state"
-            << " hit but copy not found"
-            << std::endl;
-/**/
-        std::cout
-          << "r_cleanup_srcid = " << r_cleanup_srcid.read()
-          << " / r_cleanup_inst = " << r_cleanup_inst.read() << std::endl
-          << "r_cleanup_copy = " << r_cleanup_copy.read()
-          << " / r_cleanup_copy_inst = " << r_cleanup_copy_inst.read() << std::endl
-          << "heap_entry.owner.srcid = " << heap_entry.owner.srcid
-          << " / heap_entry.owner.inst = " << heap_entry.owner.inst << std::endl
-/**/
-          << "nline = " << r_cleanup_nline << std::endl;
-        exit(0);
-      }
-
-      if(match_dir and match_heap)
-      {
-        std::cout
-            << "VCI_MEM_CACHE ERROR " << name()
-            << " CLEANUP_HEAP_LOCK state"
-            << " two copies matching the cleanup owner id"
-            << std::endl;
-/**/
-        std::cout
-          << "r_cleanup_srcid = " << r_cleanup_srcid.read()
-          << " / r_cleanup_inst = " << r_cleanup_inst.read() << std::endl
-          << "r_cleanup_copy = " << r_cleanup_copy.read()
-          << " / r_cleanup_copy_inst = " << r_cleanup_copy_inst.read() << std::endl
-          << "heap_entry.owner.srcid = " << heap_entry.owner.srcid
-          << " / heap_entry.owner.inst = " << heap_entry.owner.inst << std::endl
-/**/
-          << "nline = " << r_cleanup_nline << std::endl;
-        exit(0);
-      }
+      assert( (not last or match_dir or match_heap) and
+      "MEMC ERROR in CLEANUP_HEAP_LOCK state: hit but no copy found");
+
+      assert( (not match_dir or not match_heap) and
+      "MEMC ERROR in CLEANUP_HEAP_LOCK state: two matching copies found");
 
       DirectoryEntry dir_entry;
@@ -5439,9 +5530,4 @@
         dir_entry.owner.srcid    = heap_entry.owner.srcid;
         dir_entry.owner.inst     = heap_entry.owner.inst;
-
-#if L1_MULTI_CACHE
-        dir_entry.owner.cache_id = heap_entry.owner.cache_id;
-#endif
-
         r_cleanup_next_ptr       = r_cleanup_ptr.read();
         r_cleanup_fsm            = CLEANUP_HEAP_FREE;
@@ -5456,9 +5542,4 @@
         dir_entry.owner.srcid    = r_cleanup_copy.read();
         dir_entry.owner.inst     = r_cleanup_copy_inst.read();
-
-#if L1_MULTI_CACHE
-        dir_entry.owner.cache_id = r_cleanup_copy_cache.read();
-#endif
-
         r_cleanup_next_ptr       = r_cleanup_ptr.read();
         r_cleanup_fsm            = CLEANUP_HEAP_FREE;
@@ -5472,9 +5553,4 @@
         dir_entry.owner.srcid    = r_cleanup_copy.read();
         dir_entry.owner.inst     = r_cleanup_copy_inst.read();
-
-#if L1_MULTI_CACHE
-        dir_entry.owner.cache_id = r_cleanup_copy_cache.read();
-#endif
-
         r_cleanup_next_ptr       = heap_entry.next;
         r_cleanup_fsm            = CLEANUP_HEAP_SEARCH;
@@ -5482,5 +5558,4 @@
 
       m_cache_directory.write(set,way,dir_entry);
-
 
 #if DEBUG_MEMC_CLEANUP
@@ -5508,13 +5583,6 @@
       // This state is handling the case where the copy
       // is in the heap, but is not the first in the linked list
-      if(r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP)
-      {
-        std::cout
-            << "VCI_MEM_CACHE ERROR " << name()
-            << " CLEANUP_HEAP_SEARCH state"
-            << " bad HEAP allocation" << std::endl;
-
-        exit(0);
-      }
+      assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and
+     "MEMC ERROR in CLEANUP_HEAP_LOCK state: bad HEAP allocation");
 
       HeapEntry heap_entry  = m_heap.read(r_cleanup_next_ptr.read());
@@ -5525,20 +5593,8 @@
       bool match_heap       = match_heap_srcid and match_heap_inst;
 
-#if L1_MULTI_CACHE
-      match_heap = match_heap and(heap_entry.owner.cache_id == r_cleanup_pktid.read());
-#endif
-
-      if(not match_heap and last)
-      {
-        std::cout
-            << "VCI_MEM_CACHE_ERROR " << name()
-            << " CLEANUP_HEAP_SEARCH state"
-            << " cleanup on valid line but copy not found"
-            << std::endl;
-
-        exit(0);
-      }
-
-      // the matching copy must be removed
+      assert( (not last or match_heap) and
+      "MEMC ERROR in CLEANUP_HEAP_SEARCH state: no copy found");
+
+       // the matching copy must be removed
       if(match_heap)
       {
@@ -5554,10 +5610,5 @@
         r_cleanup_prev_inst     = heap_entry.owner.inst;
         r_cleanup_next_ptr      = heap_entry.next;
-
         r_cleanup_fsm           = CLEANUP_HEAP_SEARCH;
-
-#if L1_MULTI_CACHE
-        r_cleanup_prev_cache_id = heap_entry.owner.cache_id;
-#endif
       }
 
@@ -5595,22 +5646,10 @@
     case CLEANUP_HEAP_CLEAN:    // remove a copy in the linked list
     {
-      if(r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP)
-      {
-        std::cout
-            << "VCI_MEM_CACHE ERROR " << name()
-            << " CLEANUP_HEAP_CLEAN state"
-            << "Bad HEAP allocation"  << std::endl;
-
-        exit(0);
-      }
+     assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and
+     "MEMC ERROR in CLEANUP_HEAP_LOCK state: bad HEAP allocation");
 
       HeapEntry heap_entry;
       heap_entry.owner.srcid    = r_cleanup_prev_srcid.read();
       heap_entry.owner.inst     = r_cleanup_prev_inst.read();
-
-#if L1_MULTI_CACHE
-      heap_entry.owner.cache_id = r_cleanup_prev_cache_id.read();
-#endif
-
       bool last = (r_cleanup_next_ptr.read() == r_cleanup_ptr.read());
 
@@ -5641,21 +5680,9 @@
                               // and becomes the head of the list of free entries
     {
-      if(r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP)
-      {
-        std::cout
-            << "VCI_MEM_CACHE ERROR " << name()
-            << " CLEANUP_HEAP_CLEAN state" << std::endl
-            << "Bad HEAP allocation" << std::endl;
-
-        exit(0);
-      }
-
+     assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and
+     "MEMC ERROR in CLEANUP_HEAP_LOCK state: bad HEAP allocation");
       HeapEntry heap_entry;
       heap_entry.owner.srcid    = 0;
       heap_entry.owner.inst     = false;
-
-#if L1_MULTI_CACHE
-      heap_entry.owner.cache_id = 0;
-#endif
 
       if(m_heap.is_full())
@@ -5706,17 +5733,15 @@
 #endif
         m_cpt_cleanup_fsm_n_upt_lock++;
-        break;
-      }
-
-      // pending inval
-      r_cleanup_write_srcid = m_ivt.srcid(index);
-      r_cleanup_write_trdid = m_ivt.trdid(index);
-      r_cleanup_write_pktid = m_ivt.pktid(index);
-      r_cleanup_need_rsp    = m_ivt.need_rsp(index);
-      r_cleanup_need_ack    = m_ivt.need_ack(index);
-      r_cleanup_index       = index;
-
-      r_cleanup_fsm         = CLEANUP_IVT_DECREMENT;
-
+      }
+      else
+      {
+        // pending inval
+        r_cleanup_write_srcid = m_ivt.srcid(index);
+        r_cleanup_write_trdid = m_ivt.trdid(index);
+        r_cleanup_write_pktid = m_ivt.pktid(index);
+        r_cleanup_need_rsp    = m_ivt.need_rsp(index);
+        r_cleanup_need_ack    = m_ivt.need_ack(index);
+        r_cleanup_index       = index;
+        r_cleanup_fsm         = CLEANUP_IVT_DECREMENT;
 #if DEBUG_MEMC_CLEANUP
 if(m_debug)
@@ -5727,4 +5752,5 @@
           << " / ivt_entry = " << index << std::endl;
 #endif
+      }
       break;
     }
@@ -5732,18 +5758,9 @@
     case CLEANUP_IVT_DECREMENT: // decrement response counter in IVT matching entry
     {
-      if(r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP)
-      {
-        std::cout
-            << "VCI_MEM_CACHE ERROR "         << name()
-            << " CLEANUP_IVT_DECREMENT state" << std::endl
-            << "Bad IVT allocation"
-            << std::endl;
-
-        exit(0);
-      }
+      assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_CLEANUP) and
+      "MEMC ERROR in CLEANUP_IVT_DECREMENT state: Bad IVT allocation");
 
       size_t count = 0;
       m_ivt.decrement(r_cleanup_index.read(), count);
-
 
       if(count == 0)   // multi inval transaction completed
@@ -5775,19 +5792,18 @@
     case CLEANUP_IVT_CLEAR:    // Clear IVT entry 
     {
-      if(r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP)
-      {
-        std::cout
-            << "VCI_MEM_CACHE ERROR "     << name()
-            << " CLEANUP_IVT_CLEAR state" << std::endl
-            << "Bad IVT allocation"
-            << std::endl;
-
-        exit(0);
-      }
+      assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_CLEANUP) and
+      "MEMC ERROR in CLEANUP_IVT_CLEAR state : bad IVT allocation");
 
       m_ivt.clear(r_cleanup_index.read());
 
+      if ( r_cleanup_need_ack.read() )
+      {
+          assert( (r_config_rsp_lines.read() > 0) and
+          "MEMC ERROR in CLEANUP_IVT_CLEAR state");
+
+          r_config_rsp_lines = r_config_rsp_lines.read() - 1;
+      }
+
       if      ( r_cleanup_need_rsp.read() ) r_cleanup_fsm = CLEANUP_WRITE_RSP;
-      else if ( r_cleanup_need_ack.read() ) r_cleanup_fsm = CLEANUP_CONFIG_ACK;
       else if ( r_cleanup_ncc.read()      ) r_cleanup_fsm = CLEANUP_IXR_REQ;
       else                                  r_cleanup_fsm = CLEANUP_SEND_CLACK;
@@ -5799,6 +5815,6 @@
           << " IVT_index = " << r_cleanup_index.read() << std::endl;
 #endif
-      break;
-    }
+          break;
+      }
     ///////////////////////
     case CLEANUP_WRITE_RSP:    // response to a previous write on the direct network
@@ -5812,5 +5828,5 @@
       r_cleanup_to_tgt_rsp_trdid   = r_cleanup_write_trdid.read();
       r_cleanup_to_tgt_rsp_pktid   = r_cleanup_write_pktid.read();
-      r_cleanup_to_tgt_rsp_type    = true;
+      r_cleanup_to_tgt_rsp_type    = true; 
 
       if (r_cleanup_ncc.read())
@@ -5833,29 +5849,11 @@
       break;
     }
-    ////////////////////////
-    case CLEANUP_CONFIG_ACK:   // signals inval completion to CONFIG FSM
-                               // wait if pending request
-    {
-      if ( r_cleanup_to_config_ack.read() ) break;
-
-      r_cleanup_to_config_ack      = true;
-      r_cleanup_fsm                = CLEANUP_SEND_CLACK;
-
-#if DEBUG_MEMC_CLEANUP
-if(m_debug)
-std::cout << "  <MEMC " << name() << " CLEANUP_CONFIG_ACK>"
-          << " Acknowledge broacast inval completion" << std::endl;
-#endif
-      break;
-    }
-
     /////////////////////////
     case CLEANUP_IXR_REQ:
     {
-    
       //Send a request to the ixr to write the data in the XRAM using the prereserved TRT entry
       if (r_alloc_trt_fsm.read() == ALLOC_TRT_CLEANUP)
       {
-        if(!r_cleanup_to_ixr_cmd_req.read())
+        if( not r_cleanup_to_ixr_cmd_req.read())
         {
           size_t index = 0;
@@ -5864,19 +5862,39 @@
           assert (hit and "CLEANUP_IXR_REQ found no matching entry in TRT");
 
-            r_cleanup_to_ixr_cmd_req     = true;
-
-            for(size_t i = 0; i < m_words; i++){
-              r_cleanup_to_ixr_cmd_data[i]   = r_cleanup_data[i];
+          r_cleanup_to_ixr_cmd_req     = true;
+
+          if (r_cleanup_contains_data.read())
+          {  
+            std::vector<data_t> data_vector;
+            data_vector.clear();
+
+            for(size_t i=0; i<m_words; i++)
+            {
+              data_vector.push_back(r_cleanup_data[i]);
             }
 
-            r_cleanup_to_ixr_cmd_srcid   = r_cleanup_srcid.read();
-            r_cleanup_to_ixr_cmd_trdid   = index;
-            r_cleanup_to_ixr_cmd_pktid   = r_cleanup_pktid.read();
-            r_cleanup_to_ixr_cmd_nline   = r_cleanup_nline.read();
-            r_cleanup_to_ixr_cmd_ncc_l1_dirty = r_cleanup_contains_data.read();
-            r_cleanup_fsm = CLEANUP_SEND_CLACK;
+            m_trt.set(index,
+                      false,       // write to XRAM
+                      r_cleanup_nline.read(),  // line index
+                      0,
+                      0,
+                      0,
+                      false,
+                      0,
+                      0,
+                      std::vector<be_t> (m_words,0),
+                      data_vector);
+          }
+//std::cout << "cleanup with a non coherent ligne in trt index = " << index << std::endl;
+          r_cleanup_to_ixr_cmd_srcid        = r_cleanup_srcid.read();
+          r_cleanup_to_ixr_cmd_index        = index;
+          r_cleanup_to_ixr_cmd_pktid        = r_cleanup_pktid.read();
+          r_cleanup_to_ixr_cmd_nline        = r_cleanup_nline.read();
+          //r_cleanup_to_ixr_cmd_l1_dirty_ncc = r_cleanup_contains_data.read();
+          r_cleanup_fsm = CLEANUP_SEND_CLACK;
 #if DEBUG_MEMC_CLEANUP
       if(m_debug)
       {
+        m_trt.print(0);
         std::cout
             << "  <MEMC " << name()
@@ -5993,12 +6011,8 @@
           r_cas_wdata = m_cmd_cas_wdata_fifo.read();
 
-        if(r_cas_cpt.read() >3)  // more than 4 flits...
-        {
-          std::cout << "VCI_MEM_CACHE ERROR in CAS_IDLE state : illegal CAS command"
-                    << std::endl;
-          exit(0);
-        }
-
-        if(r_cas_cpt.read() ==2)
+        assert( (r_cas_cpt.read() <= 3) and  // no more than 4 flits...
+        "MEMC ERROR in CAS_IDLE state: illegal CAS command");
+
+         if(r_cas_cpt.read() ==2)
           r_cas_wdata = m_cmd_cas_wdata_fifo.read();
 
@@ -6034,6 +6048,7 @@
     case CAS_DIR_LOCK:  // Read the directory
     {
-      if(r_alloc_dir_fsm.read() == ALLOC_DIR_CAS)
-      {
+        assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and
+        "MEMC ERROR in CAS_DIR_LOCK: Bad DIR allocation");
+
         size_t way = 0;
         DirectoryEntry entry(m_cache_directory.read(m_cmd_cas_addr_fifo.read(), way));
@@ -6045,7 +6060,4 @@
         r_cas_way        = way;
         r_cas_copy       = entry.owner.srcid;
-#if L1_MULTI_CACHE
-        r_cas_copy_cache = entry.owner.cache_id;
-#endif
         r_cas_copy_inst  = entry.owner.inst;
         r_cas_ptr        = entry.ptr;
@@ -6065,16 +6077,5 @@
         }
 #endif
-      }
-      else
-      {
-        std::cout
-            << "VCI_MEM_CACHE ERROR " << name()
-            << " CAS_DIR_LOCK state" << std::endl
-            << "Bad DIR allocation"   << std::endl;
-
-        exit(0);
-      }
-
-      break;
+        break;
     }
     /////////////////////
@@ -6094,7 +6095,4 @@
       entry.tag            = r_cas_tag.read();
       entry.owner.srcid    = r_cas_copy.read();
-#if L1_MULTI_CACHE
-      entry.owner.cache_id = r_cas_copy_cache.read();
-#endif
       entry.owner.inst     = r_cas_copy_inst.read();
       entry.count          = r_cas_count.read();
@@ -6156,11 +6154,9 @@
     {
       // The CAS is a success => sw access to the llsc_global_table
-      // BUG LLSC
-      addr_t      nline      = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())];
-      m_llsc_table.sw(nline);
       //m_llsc_table.sw(m_cmd_cas_addr_fifo.read());
           /**//*std::cout << "MEMCACHE : from proc " << m_cmd_cas_srcid_fifo.read()
                         << " | @ " << std::hex << m_cmd_cas_addr_fifo.read()
                         << " | WRITE (cas triggered)" << std::endl;*/
+      m_llsc_table.sw(m_nline[(addr_t)m_cmd_cas_addr_fifo.read()],m_x[(addr_t)(m_cmd_cas_addr_fifo.read())],m_x[(addr_t)(m_cmd_cas_addr_fifo.read())]);
 
       // test coherence request
@@ -6170,4 +6166,11 @@
         {
           r_cas_fsm = CAS_BC_TRT_LOCK;    // broadcast invalidate required
+#if DEBUG_MEMC_CAS
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CAS_DIR_HIT_WRITE>"
+          << " Broacast Inval required" 
+          << " / copies = " << r_cas_count.read() << std::endl;
+#endif
+
         }
         else if(!r_cas_to_cc_send_multi_req.read() and
@@ -6175,8 +6178,19 @@
         {
           r_cas_fsm = CAS_UPT_LOCK;       // multi update required
+#if DEBUG_MEMC_CAS
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CAS_DIR_HIT_WRITE>"
+          << " Multi Inval required" 
+          << " / copies = " << r_cas_count.read() << std::endl;
+#endif
         }
         else
         {
           r_cas_fsm = CAS_WAIT;
+#if DEBUG_MEMC_CAS
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CAS_DIR_HIT_WRITE>"
+          << " CC_SEND FSM busy: release all locks and retry" << std::endl;
+#endif
         }
       }
@@ -6193,14 +6207,4 @@
 
         r_cas_fsm = CAS_RSP_SUCCESS;
-
-        // monitor
-        if(m_monitor_ok)
-        {
-          addr_t address = m_cmd_cas_addr_fifo.read();
-          check_monitor( address, r_cas_wdata.read(), false);
-
-          if(r_cas_cpt.read() == 4)
-            check_monitor( address+4, m_cmd_cas_wdata_fifo.read(), false);
-        }
 
 #if DEBUG_MEMC_CAS
@@ -6256,13 +6260,4 @@
           r_cas_fsm = CAS_UPT_HEAP_LOCK;
 
-          // monitor
-          if(m_monitor_ok)
-          {
-            addr_t address = m_cmd_cas_addr_fifo.read();
-            check_monitor( address, r_cas_wdata.read(), false);
-
-            if(r_cas_cpt.read() ==4)
-              check_monitor( address+4, m_cmd_cas_wdata_fifo.read(), false);
-          }
         }
         else       //  releases the locks protecting UPT and DIR UPT full
@@ -6350,7 +6345,4 @@
         cas_to_cc_send_fifo_inst    = r_cas_copy_inst.read();
         cas_to_cc_send_fifo_srcid   = r_cas_copy.read();
-#if L1_MULTI_CACHE
-        cas_to_cc_send_fifo_cache_id= r_cas_copy_cache.read();
-#endif
         if(r_cas_count.read() == 1)  // one single copy
         {
@@ -6387,7 +6379,4 @@
       HeapEntry entry = m_heap.read(r_cas_ptr.read());
       cas_to_cc_send_fifo_srcid    = entry.owner.srcid;
-#if L1_MULTI_CACHE
-      cas_to_cc_send_fifo_cache_id = entry.owner.cache_id;
-#endif
       cas_to_cc_send_fifo_inst     = entry.owner.inst;
       cas_to_cc_send_fifo_put = true;
@@ -6421,44 +6410,28 @@
     case CAS_BC_TRT_LOCK:      // check the TRT to register a PUT transaction
     {
-      if(r_alloc_trt_fsm.read() == ALLOC_TRT_CAS)
-      {
-        if(!r_cas_to_ixr_cmd_req)    // we can transfer the request to IXR_CMD FSM
-        {
-          // fill the data buffer
-          size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())];
-          for(size_t i = 0; i<m_words; i++)
-          {
-            if(i == word)
+        assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and
+        "MEMC ERROR in CAS_BC_TRT_LOCK state: Bas DIR allocation");
+
+        if(r_alloc_trt_fsm.read() == ALLOC_TRT_CAS)
+        {
+            size_t wok_index = 0;
+            bool   wok       = !m_trt.full(wok_index);
+            if( wok )
             {
-              r_cas_to_ixr_cmd_data[i] = r_cas_wdata.read();
-            }
-            else if((i == word+1) and (r_cas_cpt.read() == 4))   // 64 bit CAS
-            {
-              r_cas_to_ixr_cmd_data[i] = m_cmd_cas_wdata_fifo.read();
+                r_cas_trt_index = wok_index;
+                r_cas_fsm       = CAS_BC_IVT_LOCK;
             }
             else
             {
-              r_cas_to_ixr_cmd_data[i] = r_cas_data[i].read();
+                r_cas_fsm       = CAS_WAIT;
+                m_cpt_cas_fsm_n_trt_lock++;
             }
-          }
-          size_t wok_index = 0;
-          bool   wok       = !m_trt.full(wok_index);
-          if(wok)
-          {
-            r_cas_trt_index = wok_index;
-            r_cas_fsm       = CAS_BC_IVT_LOCK;
-          }
-          else
-          {
-            r_cas_fsm       = CAS_WAIT;
-          }
-        }
-        else
-        {
-          r_cas_fsm = CAS_WAIT;
-        }
-        m_cpt_cas_fsm_n_trt_lock++;
-      }
-
+
+#if DEBUG_MEMC_CAS
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CAS_BC_TRT_LOCK> Check TRT"
+          << " : wok = " << wok << " / index = " << wok_index << std::endl;
+#endif
+        }
       m_cpt_cas_fsm_trt_lock++;
 
@@ -6502,13 +6475,4 @@
             m_cache_data.write(way, set, word+1, m_cmd_cas_wdata_fifo.read());
 
-          // monitor
-          if(m_monitor_ok)
-          {
-            addr_t address = m_cmd_cas_addr_fifo.read();
-            check_monitor( address, r_cas_wdata.read(), false);
-
-            if(r_cas_cpt.read() ==4)
-              check_monitor( address+4, m_cmd_cas_wdata_fifo.read(), false);
-          }
           r_cas_upt_index = index;
           r_cas_fsm = CAS_BC_DIR_INVAL;
@@ -6537,20 +6501,36 @@
     case CAS_BC_DIR_INVAL:  // Register the PUT transaction in TRT, and inval the DIR entry
     {
-      if((r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and
-         (r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS) and
-         (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS))
-      {
-        // set TRT
-        m_trt.set(r_cas_trt_index.read(),
-                              false,    // PUT request to XRAM
-                              m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())],
-                              0,
-                              0,
-                              0,
-                              false,    // not a processor read
-                              0,
-                              0,
-                              std::vector<be_t> (m_words,0),
-                              std::vector<data_t> (m_words,0));
+        assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and
+        "MEMC ERROR in CAS_BC_DIR_INVAL state: Bad DIR allocation");
+
+        assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and
+        "MEMC ERROR in CAS_BC_DIR_INVAL state: Bad TRT allocation");
+
+        assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS) and
+        "MEMC ERROR in CAS_BC_DIR_INVAL state: Bad IVT allocation");
+
+        std::vector<data_t> data_vector;
+        data_vector.clear();
+        size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())];
+        for(size_t i=0; i<m_words; i++)
+        {
+            if(i == word)                                        // first modified word
+                data_vector.push_back( r_cas_wdata.read() );     
+            else if((i == word+1) and (r_cas_cpt.read() == 4))   // second modified word
+                data_vector.push_back( m_cmd_cas_wdata_fifo.read() );
+            else                                                 // unmodified words
+                data_vector.push_back( r_cas_data[i].read() );
+        }
+        m_trt.set( r_cas_trt_index.read(),
+                   false,    // PUT request 
+                   m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())],
+                   0,
+                   0,
+                   0,
+                   false,    // not a processor read
+                   0,
+                   0,
+                   std::vector<be_t> (m_words,0),
+                   data_vector );
 
         // invalidate directory entry
@@ -6558,12 +6538,9 @@
         entry.valid         = false;
         entry.dirty         = false;
-        entry.tag         = 0;
+        entry.tag           = 0;
         entry.is_cnt        = false;
         entry.lock          = false;
         entry.count         = 0;
         entry.owner.srcid   = 0;
-#if L1_MULTI_CACHE
-        entry.owner.cache_id= 0;
-#endif
         entry.owner.inst    = false;
         entry.ptr           = 0;
@@ -6576,14 +6553,8 @@
 #if DEBUG_MEMC_CAS
 if(m_debug)
-std::cout << "  <MEMC " << name()
-          << " CAS_BC_DIR_INVAL> Register the PUT in TRT and invalidate DIR entry"
-          << " / nline = " << std::hex << m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]
-          << " / set = " << std::dec << set << " / way = " << way << std::endl;
-#endif
-      }
-      else
-      {
-        assert(false and "LOCK ERROR in CAS_FSM, STATE = CAS_BC_DIR_INVAL");
-      }
+        m_trt.print(0);
+std::cout << "  <MEMC " << name() << " CAS_BC_DIR_INVAL> Inval DIR & register in TRT:"
+          << " address = " << m_cmd_cas_addr_fifo.read() << std::endl;
+#endif
       break;
     }
@@ -6591,6 +6562,6 @@
     case CAS_BC_CC_SEND:  // Request the broadcast inval to CC_SEND FSM
     {
-      if(!r_cas_to_cc_send_multi_req.read() and
-          !r_cas_to_cc_send_brdcast_req.read())
+      if( not r_cas_to_cc_send_multi_req.read() and
+          not r_cas_to_cc_send_brdcast_req.read())
       {
         r_cas_to_cc_send_multi_req    = false;
@@ -6608,10 +6579,9 @@
     case CAS_BC_XRAM_REQ: // request the IXR FSM to start a put transaction
     {
-      if(!r_cas_to_ixr_cmd_req)
+      if( not r_cas_to_ixr_cmd_req.read() )
       {
         r_cas_to_ixr_cmd_req     = true;
-        r_cas_to_ixr_cmd_write   = true;
-        r_cas_to_ixr_cmd_nline   = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())];
-        r_cas_to_ixr_cmd_trdid   = r_cas_trt_index.read();
+        r_cas_to_ixr_cmd_put     = true;
+        r_cas_to_ixr_cmd_index   = r_cas_trt_index.read();
         r_cas_fsm                = CAS_IDLE;
         cmd_cas_fifo_get         = true;
@@ -6622,13 +6592,9 @@
 std::cout << "  <MEMC " << name()
           << " CAS_BC_XRAM_REQ> Request a PUT transaction to IXR_CMD FSM" << std::hex
-          << " / nline = " << m_nline[(addr_t) m_cmd_cas_addr_fifo.read()]
+          << " / address = " << (addr_t) m_cmd_cas_addr_fifo.read()
           << " / trt_index = " << r_cas_trt_index.read() << std::endl;
 #endif
       }
-      else
-      {
-        std::cout << "ERROR in MEM_CACHE / CAS_BC_XRAM_REQ state"
-                  << " : request should not have been previously set" << std::endl;
-      }
+      
       break;
     }
@@ -6636,9 +6602,9 @@
     case CAS_RSP_FAIL:  // request TGT_RSP FSM to send a failure response
     {
-      if(!r_cas_to_tgt_rsp_req)
-      {
-        cmd_cas_fifo_get     = true;
+      if( not r_cas_to_tgt_rsp_req.read() )
+      {
+        cmd_cas_fifo_get       = true;
         r_cas_cpt              = 0;
-        r_cas_to_tgt_rsp_req = true;
+        r_cas_to_tgt_rsp_req   = true;
         r_cas_to_tgt_rsp_data  = 1;
         r_cas_to_tgt_rsp_srcid = m_cmd_cas_srcid_fifo.read();
@@ -6658,5 +6624,5 @@
     case CAS_RSP_SUCCESS:  // request TGT_RSP FSM to send a success response
     {
-      if(!r_cas_to_tgt_rsp_req)
+      if( not r_cas_to_tgt_rsp_req.read() )
       {
         cmd_cas_fifo_get       = true;
@@ -6687,5 +6653,5 @@
         bool hit_write = m_trt.hit_write(
                            m_nline[(addr_t) m_cmd_cas_addr_fifo.read()]);
-        bool wok = !m_trt.full(index);
+        bool wok = not m_trt.full(index);
 
 #if DEBUG_MEMC_CAS
@@ -6719,6 +6685,7 @@
     case CAS_MISS_TRT_SET: // register the GET transaction in TRT
     {
-      if(r_alloc_trt_fsm.read() == ALLOC_TRT_CAS)
-      {
+        assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and
+        "MEMC ERROR in CAS_MISS_TRT_SET state: Bad TRT allocation");
+
         std::vector<be_t> be_vector;
         std::vector<data_t> data_vector;
@@ -6732,14 +6699,14 @@
 
         m_trt.set(r_cas_trt_index.read(),
-                              true,   // read request
-                              m_nline[(addr_t) m_cmd_cas_addr_fifo.read()],
-                              m_cmd_cas_srcid_fifo.read(),
-                              m_cmd_cas_trdid_fifo.read(),
-                              m_cmd_cas_pktid_fifo.read(),
-                              false,    // write request from processor
-                              0,
-                              0,
-                              be_vector,
-                              data_vector);
+                  true,   // read request
+                  m_nline[(addr_t) m_cmd_cas_addr_fifo.read()],
+                  m_cmd_cas_srcid_fifo.read(),
+                  m_cmd_cas_trdid_fifo.read(),
+                  m_cmd_cas_pktid_fifo.read(),
+                  false,    // write request from processor
+                  0,
+                  0,
+                  be_vector,
+                  data_vector);
         r_cas_fsm = CAS_MISS_XRAM_REQ;
 
@@ -6747,4 +6714,5 @@
         if(m_debug)
         {
+          m_trt.print(0);
           std::cout << "  <MEMC " << name() << " CAS_MISS_TRT_SET> Register a GET transaction in TRT" << std::hex
                     << " / nline = " << m_nline[(addr_t) m_cmd_cas_addr_fifo.read()]
@@ -6752,5 +6720,4 @@
         }
 #endif
-      }
       break;
     }
@@ -6758,19 +6725,16 @@
     case CAS_MISS_XRAM_REQ:  // request the IXR_CMD FSM to fetch the missing line
     {
-      if(!r_cas_to_ixr_cmd_req)
+      if( not r_cas_to_ixr_cmd_req.read() )
       {
         r_cas_to_ixr_cmd_req        = true;
-        r_cas_to_ixr_cmd_write      = false;
-        r_cas_to_ixr_cmd_trdid      = r_cas_trt_index.read();
-        r_cas_to_ixr_cmd_nline      = m_nline[(addr_t) m_cmd_cas_addr_fifo.read()];
+        r_cas_to_ixr_cmd_put        = false;
+        r_cas_to_ixr_cmd_index      = r_cas_trt_index.read();
         r_cas_fsm                   = CAS_WAIT;
 
 #if DEBUG_MEMC_CAS
-        if(m_debug)
-        {
-          std::cout << "  <MEMC " << name() << " CAS_MISS_XRAM_REQ> Request a GET transaction to IXR_CMD FSM" << std::hex
-                    << " / nline = " << m_nline[(addr_t) m_cmd_cas_addr_fifo.read()]
-                    << " / trt_index = " << r_cas_trt_index.read() << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CAS_MISS_XRAM_REQ> Request a GET transaction"
+          << " / address = " << std::hex << (addr_t) m_cmd_cas_addr_fifo.read()
+          << " / trt_index = " << std::dec << r_cas_trt_index.read() << std::endl;
 #endif
       }
@@ -7643,5 +7607,4 @@
         r_tgt_rsp_cpt = r_cleanup_to_tgt_rsp_first_word.read();
       }
-
       else if(r_config_to_tgt_rsp_req)    r_tgt_rsp_fsm = TGT_RSP_CONFIG;
       else if(r_tgt_cmd_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
@@ -7780,5 +7743,5 @@
     }
     /////////////////////
-    case TGT_RSP_TGT_CMD: // send the response for a segmentation violation
+    case TGT_RSP_TGT_CMD: // send the response for a configuration access
     {
       if ( p_vci_tgt.rspack )
@@ -7792,8 +7755,9 @@
   std::cout
     << "  <MEMC " << name()
-    << " TGT_RSP_TGT_CMD> Segmentation violation response"
+    << " TGT_RSP_TGT_CMD> Send response for a configuration access"
     << " / rsrcid = " << std::hex << r_tgt_cmd_to_tgt_rsp_srcid.read()
     << " / rtrdid = " << r_tgt_cmd_to_tgt_rsp_trdid.read()
     << " / rpktid = " << r_tgt_cmd_to_tgt_rsp_pktid.read()
+    << " / error = " << r_tgt_cmd_to_tgt_rsp_error.read()
     << std::endl;
 }
@@ -7916,5 +7880,4 @@
 #endif
 
-
         uint32_t last_word_idx = r_cleanup_to_tgt_rsp_first_word.read() + r_cleanup_to_tgt_rsp_length.read() - 1;
         bool is_ll = ((r_cleanup_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL);
@@ -7972,5 +7935,4 @@
           }
         }
-
       }
       break;
@@ -8114,5 +8076,4 @@
               else if (r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK)
                   r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK;
-            
               else
                   m_cpt_upt_unused++;
@@ -8145,5 +8106,4 @@
               else if (r_cas_fsm.read() == CAS_UPT_LOCK)
                   r_alloc_upt_fsm = ALLOC_UPT_CAS;
-            
               else
                   m_cpt_upt_unused++;
@@ -8178,5 +8138,5 @@
               r_alloc_ivt_fsm = ALLOC_IVT_READ;
             
-            else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)
+            else if (r_xram_rsp_fsm.read() == XRAM_RSP_IVT_LOCK)
               r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP;
 
@@ -8188,5 +8148,5 @@
                   r_alloc_ivt_fsm = ALLOC_IVT_CAS;
         
-            else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK)
+            else if (r_config_fsm.read() == CONFIG_IVT_LOCK)
               r_alloc_ivt_fsm = ALLOC_IVT_CONFIG;
 
@@ -8200,5 +8160,5 @@
           if (r_read_fsm.read() != READ_IVT_LOCK) 
           {
-            if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)
+            if (r_xram_rsp_fsm.read() == XRAM_RSP_IVT_LOCK)
               r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP;
 
@@ -8210,5 +8170,5 @@
                   r_alloc_ivt_fsm = ALLOC_IVT_CAS;
         
-            else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK)
+            else if (r_config_fsm.read() == CONFIG_IVT_LOCK)
               r_alloc_ivt_fsm = ALLOC_IVT_CONFIG;
           
@@ -8217,5 +8177,4 @@
                 (r_write_fsm.read() == WRITE_MISS_IVT_LOCK))
               r_alloc_ivt_fsm = ALLOC_IVT_WRITE;
-
             else
               m_cpt_ivt_unused++;
@@ -8225,5 +8184,5 @@
       //////////////////////////
       case ALLOC_IVT_XRAM_RSP:         // allocated to XRAM_RSP FSM
-          if(r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK)
+          if(r_xram_rsp_fsm.read() != XRAM_RSP_IVT_LOCK)
           {
             if ((r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) or
@@ -8234,5 +8193,5 @@
               r_alloc_ivt_fsm = ALLOC_IVT_CAS;
 
-            else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK)
+            else if (r_config_fsm.read() == CONFIG_IVT_LOCK)
               r_alloc_ivt_fsm = ALLOC_IVT_CONFIG;
 
@@ -8259,5 +8218,5 @@
               r_alloc_ivt_fsm = ALLOC_IVT_CAS;
 
-            else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK)
+            else if (r_config_fsm.read() == CONFIG_IVT_LOCK)
               r_alloc_ivt_fsm = ALLOC_IVT_CONFIG;
 
@@ -8270,5 +8229,5 @@
               r_alloc_ivt_fsm = ALLOC_IVT_READ;
 
-            else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)
+            else if (r_xram_rsp_fsm.read() == XRAM_RSP_IVT_LOCK)
               r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP;
 
@@ -8282,5 +8241,5 @@
           if (r_cas_fsm.read() != CAS_BC_IVT_LOCK)
           {
-            if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK)
+            if (r_config_fsm.read() == CONFIG_IVT_LOCK)
               r_alloc_ivt_fsm = ALLOC_IVT_CONFIG;
 
@@ -8293,5 +8252,5 @@
               r_alloc_ivt_fsm = ALLOC_IVT_READ;
 
-            else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)
+            else if (r_xram_rsp_fsm.read() == XRAM_RSP_IVT_LOCK)
               r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP;
 
@@ -8307,5 +8266,5 @@
       //////////////////////////
       case ALLOC_IVT_CONFIG:           // allocated to CONFIG FSM
-          if (r_config_fsm.read() != CONFIG_DIR_IVT_LOCK)
+          if (r_config_fsm.read() != CONFIG_IVT_LOCK)
           {
             if ((r_write_fsm.read() == WRITE_BC_IVT_LOCK) or
@@ -8317,5 +8276,5 @@
               r_alloc_ivt_fsm = ALLOC_IVT_READ;
 
-            else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)
+            else if (r_xram_rsp_fsm.read() == XRAM_RSP_IVT_LOCK)
               r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP;
 
@@ -8326,5 +8285,4 @@
             else if(r_cas_fsm.read() == CAS_BC_IVT_LOCK)
               r_alloc_ivt_fsm = ALLOC_IVT_CAS;
-
             else
               m_cpt_ivt_unused++;
@@ -8361,5 +8319,7 @@
     if ( (r_config_fsm.read()    != CONFIG_DIR_REQ) and
          (r_config_fsm.read()    != CONFIG_DIR_ACCESS) and
-         (r_config_fsm.read()    != CONFIG_DIR_IVT_LOCK) )
+         (r_config_fsm.read()    != CONFIG_TRT_LOCK) and
+         (r_config_fsm.read()    != CONFIG_TRT_SET) and
+         (r_config_fsm.read()    != CONFIG_IVT_LOCK) )
     {
         if(r_read_fsm.read() == READ_DIR_REQ)
@@ -8417,5 +8377,5 @@
       if(((r_write_fsm.read()       != WRITE_DIR_REQ)  and
           (r_write_fsm.read()       != WRITE_DIR_LOCK)  and
-          (r_write_fsm.read()       != WRITE_DIR_READ)  and
+          (r_write_fsm.read()       != WRITE_BC_DIR_READ)  and
           (r_write_fsm.read()       != WRITE_DIR_HIT)  and
           (r_write_fsm.read()       != WRITE_BC_TRT_LOCK)  and
@@ -8530,5 +8490,5 @@
       if( (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) and
         (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) and
-        (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK))
+        (r_xram_rsp_fsm.read() != XRAM_RSP_IVT_LOCK))
       {
         if(r_config_fsm.read() == CONFIG_DIR_REQ)
@@ -8579,4 +8539,12 @@
           r_alloc_trt_fsm = ALLOC_TRT_CAS;
 
+        else if((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or
+                (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or
+                (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or
+                (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or
+                (r_ixr_cmd_fsm.read() == IXR_CMD_CLEANUP_TRT) or
+                (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT) )
+          r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD;
+ 
         else if((r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK) and
                 (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP))
@@ -8587,4 +8555,7 @@
           r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
 
+        else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 
+          r_alloc_trt_fsm = ALLOC_TRT_CONFIG;
+ 
         else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ)
           r_alloc_trt_fsm = ALLOC_TRT_CLEANUP;
@@ -8607,4 +8578,12 @@
           r_alloc_trt_fsm = ALLOC_TRT_CAS;
 
+        else if((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or
+               (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or
+               (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or
+               (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or
+               (r_ixr_cmd_fsm.read() == IXR_CMD_CLEANUP_TRT) or
+               (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT) )
+          r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD;
+ 
         else if((r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK) and
                 (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP))
@@ -8618,4 +8597,7 @@
           r_alloc_trt_fsm = ALLOC_TRT_CLEANUP;
 
+        else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 
+          r_alloc_trt_fsm = ALLOC_TRT_CONFIG;
+
         else if(r_read_fsm.read() == READ_TRT_LOCK)
           r_alloc_trt_fsm = ALLOC_TRT_READ;
@@ -8634,6 +8616,14 @@
           (r_cas_fsm.read() != CAS_BC_IVT_LOCK))
       {
-        if((r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK) and
-            (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP))
+       if((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or
+          (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or
+          (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or
+          (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or
+          (r_ixr_cmd_fsm.read() == IXR_CMD_CLEANUP_TRT) or
+          (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT) )
+           r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD;
+ 
+        else if((r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK) and
+               (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP))
           r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
 
@@ -8645,4 +8635,7 @@
           r_alloc_trt_fsm = ALLOC_TRT_CLEANUP;
 
+        else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 
+          r_alloc_trt_fsm = ALLOC_TRT_CONFIG;
+ 
         else if(r_read_fsm.read() == READ_TRT_LOCK)
           r_alloc_trt_fsm = ALLOC_TRT_READ;
@@ -8658,4 +8651,40 @@
         m_cpt_cas_fsm_trt_used++;
       break;
+      ///////////////////////
+      case ALLOC_TRT_IXR_CMD:
+          if((r_ixr_cmd_fsm.read() != IXR_CMD_READ_TRT) and
+             (r_ixr_cmd_fsm.read() != IXR_CMD_WRITE_TRT) and
+             (r_ixr_cmd_fsm.read() != IXR_CMD_CAS_TRT) and
+             (r_ixr_cmd_fsm.read() != IXR_CMD_XRAM_TRT) and
+             (r_ixr_cmd_fsm.read() != IXR_CMD_CLEANUP_TRT) and
+             (r_ixr_cmd_fsm.read() != IXR_CMD_CONFIG_TRT))
+          {
+              if((r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK) and
+                 (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP))
+                  r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+
+              else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or
+                      (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))
+                  r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+
+              else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ)
+                  r_alloc_trt_fsm = ALLOC_TRT_CLEANUP;
+
+
+              else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 
+                  r_alloc_trt_fsm = ALLOC_TRT_CONFIG;
+
+              else if(r_read_fsm.read() == READ_TRT_LOCK)
+                  r_alloc_trt_fsm = ALLOC_TRT_READ;
+
+              else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or
+                      (r_write_fsm.read() == WRITE_BC_TRT_LOCK))
+                  r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+
+              else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or
+                      (r_cas_fsm.read() == CAS_BC_TRT_LOCK))
+                  r_alloc_trt_fsm = ALLOC_TRT_CAS;
+          }
+          break;
 
     ////////////////////////
@@ -8665,5 +8694,5 @@
           (r_xram_rsp_fsm.read()  != XRAM_RSP_TRT_COPY)  and
           (r_xram_rsp_fsm.read()  != XRAM_RSP_DIR_UPDT)  and
-          (r_xram_rsp_fsm.read()  != XRAM_RSP_INVAL_LOCK))
+          (r_xram_rsp_fsm.read()  != XRAM_RSP_IVT_LOCK))
       {
         if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or
@@ -8685,4 +8714,15 @@
           r_alloc_trt_fsm = ALLOC_TRT_CAS;
 
+        else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 
+          r_alloc_trt_fsm = ALLOC_TRT_CONFIG;
+ 
+        else if((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or
+               (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or
+               (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or
+               (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or
+               (r_ixr_cmd_fsm.read() == IXR_CMD_CLEANUP_TRT) or
+               (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT) )
+          r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD;
+
         else
           m_cpt_trt_unused++;
@@ -8697,6 +8737,8 @@
           (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ))
       {
+        if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 
+          r_alloc_trt_fsm = ALLOC_TRT_CONFIG;
         
-        if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ)
+        else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ)
           r_alloc_trt_fsm = ALLOC_TRT_CLEANUP;
 
@@ -8711,4 +8753,12 @@
                 (r_cas_fsm.read() == CAS_BC_TRT_LOCK))
           r_alloc_trt_fsm = ALLOC_TRT_CAS;
+
+        else if((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or
+                (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or
+                (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or
+                (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or
+                (r_ixr_cmd_fsm.read() == IXR_CMD_CLEANUP_TRT) or
+                (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT) )
+          r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD;
 
         else if((r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK) &&
@@ -8746,6 +8796,54 @@
             (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))
           r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
-      }
-      break;
+
+        else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 
+          r_alloc_trt_fsm = ALLOC_TRT_CONFIG;
+
+        else if((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or
+                (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or
+                (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or
+                (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or
+                (r_ixr_cmd_fsm.read() == IXR_CMD_CLEANUP_TRT) or
+                (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT) )
+          r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD;
+      }
+      break;
+      //////////////////////
+      case ALLOC_TRT_CONFIG:
+          if((r_config_fsm.read() != CONFIG_TRT_LOCK) and
+             (r_config_fsm.read() != CONFIG_TRT_SET))
+          {
+              if(r_read_fsm.read() == READ_TRT_LOCK)
+                  r_alloc_trt_fsm = ALLOC_TRT_READ;
+
+              else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or
+                      (r_write_fsm.read() == WRITE_BC_TRT_LOCK))
+                  r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+
+              else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or
+                      (r_cas_fsm.read() == CAS_BC_TRT_LOCK))
+                  r_alloc_trt_fsm = ALLOC_TRT_CAS;
+
+              else if((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or
+                      (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or
+                      (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or
+                      (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or
+                      (r_ixr_cmd_fsm.read() == IXR_CMD_CLEANUP_TRT) or
+                      (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT) )
+                  r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD;
+
+              else if((r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK) and
+                      (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP))
+                  r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+
+              else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ)
+                  r_alloc_trt_fsm = ALLOC_TRT_CLEANUP;
+
+              else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or
+                      (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))
+                  r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+          }
+          break;
+
 
   } // end switch alloc_trt_fsm
@@ -9034,8 +9132,4 @@
   m_write_to_cc_send_srcid_fifo.update( write_to_cc_send_fifo_get, write_to_cc_send_fifo_put,
                                         write_to_cc_send_fifo_srcid );
-#if L1_MULTI_CACHE
-  m_write_to_cc_send_cache_id_fifo.update( write_to_cc_send_fifo_get, write_to_cc_send_fifo_put,
-                                           write_to_cc_send_fifo_cache_id );
-#endif
 
   ////////////////////////////////////////////////////////////////////////////////////
@@ -9047,8 +9141,4 @@
   m_config_to_cc_send_srcid_fifo.update( config_to_cc_send_fifo_get, config_to_cc_send_fifo_put,
                                          config_to_cc_send_fifo_srcid );
-#if L1_MULTI_CACHE
-  m_config_to_cc_send_cache_id_fifo.update( config_to_cc_send_fifo_get, config_to_cc_send_fifo_put,
-                                            config_to_cc_send_fifo_cache_id );
-#endif
 
   ////////////////////////////////////////////////////////////////////////////////////
@@ -9060,8 +9150,4 @@
   m_xram_rsp_to_cc_send_srcid_fifo.update( xram_rsp_to_cc_send_fifo_get, xram_rsp_to_cc_send_fifo_put,
                                            xram_rsp_to_cc_send_fifo_srcid );
-#if L1_MULTI_CACHE
-  m_xram_rsp_to_cc_send_cache_id_fifo.update( xram_rsp_to_cc_send_fifo_get, xram_rsp_to_cc_send_fifo_put,
-                                              xram_rsp_to_cc_send_fifo_cache_id );
-#endif
 
   ////////////////////////////////////////////////////////////////////////////////////
@@ -9073,9 +9159,4 @@
   m_cas_to_cc_send_srcid_fifo.update( cas_to_cc_send_fifo_get, cas_to_cc_send_fifo_put,
                                       cas_to_cc_send_fifo_srcid );
-#if L1_MULTI_CACHE
-  m_cas_to_cc_send_cache_id_fifo.update( cas_to_cc_send_fifo_get, cas_to_cc_send_fifo_put,
-                                         cas_to_cc_send_fifo_cache_id );
-#endif
-
   m_cpt_cycles++;
 
@@ -9089,8 +9170,20 @@
   // Command signals on the p_vci_ixr port
   ////////////////////////////////////////////////////////////
-
-  p_vci_ixr.be      = 0xFF;   // nor transmited to external ram
+  // DATA width is 8 bytes
+  // The following values are not transmitted to XRAM
+  //   p_vci_ixr.be 
+  //   p_vci_ixr.pktid  
+  //   p_vci_ixr.cons 
+  //   p_vci_ixr.wrap 
+  //   p_vci_ixr.contig 
+  //   p_vci_ixr.clen 
+  //   p_vci_ixr.cfixed 
+
+  p_vci_ixr.plen    = 64;
+  p_vci_ixr.srcid   = m_srcid_x;
+  p_vci_ixr.trdid   = r_ixr_cmd_trdid.read();
+  p_vci_ixr.address = (addr_t)r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2);
+  p_vci_ixr.be      = 0xFF; 
   p_vci_ixr.pktid   = 0;
-  p_vci_ixr.srcid   = m_srcid_x;
   p_vci_ixr.cons    = false;
   p_vci_ixr.wrap    = false;
@@ -9098,102 +9191,44 @@
   p_vci_ixr.clen    = 0;
   p_vci_ixr.cfixed  = false;
-  p_vci_ixr.plen    = 64;
-
-  if(r_ixr_cmd_fsm.read() == IXR_CMD_READ)
-  {
-    p_vci_ixr.cmd       = vci_param_ext::CMD_READ;
-    p_vci_ixr.cmdval    = true;
-    p_vci_ixr.address   = (addr_t)(r_read_to_ixr_cmd_nline.read() * m_words * 4);
-    p_vci_ixr.wdata     = 0;
-    p_vci_ixr.trdid     = r_read_to_ixr_cmd_trdid.read();
-    p_vci_ixr.eop       = true;
+
+  if ( (r_ixr_cmd_fsm.read() == IXR_CMD_READ_SEND) or
+       (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_SEND) or
+       (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_SEND) or
+       (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_SEND) or
+       (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_SEND) )
+   {
+      p_vci_ixr.cmdval    = true;
+    
+      if ( r_ixr_cmd_get.read() )  // GET
+      {
+          p_vci_ixr.cmd     = vci_param_ext::CMD_READ;
+          p_vci_ixr.wdata   = 0;
+          p_vci_ixr.eop     = true;
+      }
+      else                         // PUT
+      {
+          size_t word       = r_ixr_cmd_word.read();
+          p_vci_ixr.cmd     = vci_param_ext::CMD_WRITE;
+          p_vci_ixr.wdata   = ((wide_data_t)(r_ixr_cmd_wdata[word].read()))  |
+                              ((wide_data_t)(r_ixr_cmd_wdata[word+1].read()) << 32);
+          p_vci_ixr.eop     = (word == (m_words-2));
+      }
   }
-  else if(r_ixr_cmd_fsm.read() == IXR_CMD_CAS)
-  {
-    if(r_cas_to_ixr_cmd_write.read())
-    {
-      size_t word       = r_ixr_cmd_cpt.read();
-      p_vci_ixr.cmd     = vci_param_ext::CMD_WRITE;
-      p_vci_ixr.cmdval  = true;
-      p_vci_ixr.address = (addr_t)( (r_cas_to_ixr_cmd_nline.read() * m_words + word) * 4 );
-      p_vci_ixr.wdata   = ((wide_data_t)(r_cas_to_ixr_cmd_data[word].read()))  |
-                          ((wide_data_t)(r_cas_to_ixr_cmd_data[word+1].read()) << 32);
-      p_vci_ixr.trdid   = r_cas_to_ixr_cmd_trdid.read();
-      p_vci_ixr.eop     = (r_ixr_cmd_cpt == (m_words-2));
-    }
-    else
-    {
-      p_vci_ixr.cmd     = vci_param_ext::CMD_READ;
-      p_vci_ixr.cmdval  = true;
-      p_vci_ixr.address = (addr_t)(r_cas_to_ixr_cmd_nline.read() *m_words*4);
-      p_vci_ixr.wdata   = 0;
-      p_vci_ixr.trdid   = r_cas_to_ixr_cmd_trdid.read();
-      p_vci_ixr.eop     = true;
-    }
-  }
-  else if(r_ixr_cmd_fsm.read() == IXR_CMD_WRITE)
-  {
-    if(r_write_to_ixr_cmd_write.read())
-    {
-      p_vci_ixr.cmd     = vci_param_ext::CMD_WRITE;
-      p_vci_ixr.cmdval  = true;
-      p_vci_ixr.address = (addr_t)( (r_write_to_ixr_cmd_nline.read() * m_words +
-                                     r_ixr_cmd_cpt.read()) * 4 );
-      p_vci_ixr.wdata   = ((wide_data_t)(r_write_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read()) |
-                          ((wide_data_t)(r_write_to_ixr_cmd_data[r_ixr_cmd_cpt.read()+1].read()) << 32));
-      p_vci_ixr.trdid   = r_write_to_ixr_cmd_trdid.read();
-      p_vci_ixr.eop     = (r_ixr_cmd_cpt == (m_words-2));
-    }
-    else
-    {
-      p_vci_ixr.cmd     = vci_param_ext::CMD_READ;
-      p_vci_ixr.cmdval  = true;
-      p_vci_ixr.address = (addr_t)(r_write_to_ixr_cmd_nline.read() *m_words*4);
-      p_vci_ixr.wdata   = 0;
-      p_vci_ixr.trdid   = r_write_to_ixr_cmd_trdid.read();
-      p_vci_ixr.eop     = true;
-    }
-  }
-  else if(r_ixr_cmd_fsm.read() == IXR_CMD_XRAM)
-  {
-    p_vci_ixr.cmd       = vci_param_ext::CMD_WRITE;
-    p_vci_ixr.cmdval    = true;
-    p_vci_ixr.address   = (addr_t)( (r_xram_rsp_to_ixr_cmd_nline.read() * m_words +
-                                   r_ixr_cmd_cpt.read()) * 4 );
-    p_vci_ixr.wdata     = ((wide_data_t)(r_xram_rsp_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read()) |
-                          ((wide_data_t)(r_xram_rsp_to_ixr_cmd_data[r_ixr_cmd_cpt.read()+1].read()) << 32));
-    p_vci_ixr.trdid     = r_xram_rsp_to_ixr_cmd_trdid.read();
-    p_vci_ixr.eop       = (r_ixr_cmd_cpt == (m_words-2));
-  } 
-  else if (r_ixr_cmd_fsm.read() == IXR_CMD_CLEANUP_DATA)
+  else if (r_ixr_cmd_fsm.read() == IXR_CMD_CLEANUP_DATA_SEND)
   {
     p_vci_ixr.cmd     = vci_param_ext::CMD_WRITE;
     p_vci_ixr.cmdval  = true;
-    p_vci_ixr.address = (addr_t)((r_cleanup_to_ixr_cmd_nline.read() * m_words + r_ixr_cmd_cpt.read()) * 4);
-    if (r_cleanup_to_ixr_cmd_ncc_l1_dirty.read()) //if L1 was dirty, the correct data is in the cleanup
-    {
-      p_vci_ixr.wdata   = ((wide_data_t)(r_cleanup_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read()) | 
-          ((wide_data_t)(r_cleanup_to_ixr_cmd_data[r_ixr_cmd_cpt.read()+1].read()) << 32));
-      if(r_cleanup_to_ixr_cmd_nline.read() == 0x12bb)
-        std::cout << "IXR data dirty = " << std::hex << p_vci_ixr.wdata << std::dec << std::endl;
-    }
-    else //if L1 was not dirty, the data is in the L2
-    {
-      p_vci_ixr.wdata   = ((wide_data_t)(r_xram_rsp_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read()) | 
-          ((wide_data_t)(r_xram_rsp_to_ixr_cmd_data[r_ixr_cmd_cpt.read()+1].read()) << 32));
-      if(r_cleanup_to_ixr_cmd_nline.read() == 0x12bb)
-        std::cout << "IXR data not dirty = " << std::hex << p_vci_ixr.wdata << std::dec << std::endl;
-    }
-    p_vci_ixr.trdid   = r_cleanup_to_ixr_cmd_trdid.read();
-    p_vci_ixr.eop     = (r_ixr_cmd_cpt == (m_words - 2));
+    /*p_vci_ixr.address = (addr_t)((r_cleanup_to_ixr_cmd_nline.read() * m_words + 
+                                    r_ixr_cmd_word.read()) * 4);*/
+    p_vci_ixr.address = (addr_t)r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2);
+    p_vci_ixr.wdata   = ((wide_data_t)(r_ixr_cmd_wdata[r_ixr_cmd_word.read()].read()) | 
+          ((wide_data_t)(r_ixr_cmd_wdata[r_ixr_cmd_word.read() + 1].read()) << 32));
+    p_vci_ixr.trdid   = r_cleanup_to_ixr_cmd_index.read();
+    p_vci_ixr.eop     = (r_ixr_cmd_word == (m_words - 2));
   }
+
   else
   {
-    p_vci_ixr.cmdval    = false;
-    p_vci_ixr.cmd       = vci_param_ext::CMD_READ;
-    p_vci_ixr.address   = 0;
-    p_vci_ixr.wdata     = 0;
-    p_vci_ixr.trdid     = 0;
-    p_vci_ixr.eop       = false;
+     p_vci_ixr.cmdval    = false;
   }
 
@@ -9202,12 +9237,17 @@
   ////////////////////////////////////////////////////
 
-  if(((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) and
-      (r_ixr_rsp_fsm.read()   == IXR_RSP_TRT_READ)) or
-      (r_ixr_rsp_fsm.read()   == IXR_RSP_ACK))
-
-    p_vci_ixr.rspack = true;
-
-  else
-    p_vci_ixr.rspack = false;
+  if( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ) or
+      (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) )
+  { 
+      p_vci_ixr.rspack = (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP);
+  }
+  else if (r_ixr_rsp_fsm.read() == IXR_RSP_ACK)
+  {
+      p_vci_ixr.rspack = true;
+  }
+  else // r_ixr_rsp_fsm == IXR_RSP_IDLE
+  {
+      p_vci_ixr.rspack = false;
+  }
 
   ////////////////////////////////////////////////////
@@ -9279,5 +9319,5 @@
     {
       p_vci_tgt.rspval  = true;
-      p_vci_tgt.rdata   = 0;
+      p_vci_tgt.rdata   = r_tgt_cmd_to_tgt_rsp_rdata.read();
       p_vci_tgt.rsrcid  = r_tgt_cmd_to_tgt_rsp_srcid.read();
       p_vci_tgt.rtrdid  = r_tgt_cmd_to_tgt_rsp_trdid.read();
@@ -9904,42 +9944,18 @@
   ////////////////////////////////////////////////////////////////////
 
-  switch(r_cleanup_fsm.read())
+  if ( r_cleanup_fsm.read() == CLEANUP_SEND_CLACK )
   {
-    case CLEANUP_IDLE:
-    case CLEANUP_GET_NLINE:
-    case CLEANUP_DIR_REQ:
-    case CLEANUP_DIR_LOCK:
-    case CLEANUP_DIR_WRITE:
-    case CLEANUP_HEAP_REQ:
-    case CLEANUP_HEAP_LOCK:
-    case CLEANUP_HEAP_SEARCH:
-    case CLEANUP_HEAP_CLEAN:
-    case CLEANUP_HEAP_FREE:
-    case CLEANUP_IVT_LOCK:
-    case CLEANUP_IVT_DECREMENT:
-    case CLEANUP_IVT_CLEAR:
-    case CLEANUP_WRITE_RSP:
-    case CLEANUP_CONFIG_ACK:
-      p_dspin_clack.write = false;
-      p_dspin_clack.eop   = false;
-      p_dspin_clack.data  = 0;
-
-      break;
-
-    case CLEANUP_SEND_CLACK: 
-      {
-        uint8_t cleanup_ack_type;
-        if(r_cleanup_inst.read())
-        {
+      uint8_t cleanup_ack_type;
+      if(r_cleanup_inst.read())
+      {
           cleanup_ack_type = DspinDhccpParam::TYPE_CLACK_INST;
-        }
-        else
-        {
+      }
+      else
+      {
           cleanup_ack_type = DspinDhccpParam::TYPE_CLACK_DATA;
-        }
-
-        uint64_t flit = 0;
-        uint64_t dest =
-          r_cleanup_srcid.read() <<
+      }
+
+      uint64_t flit = 0;
+      uint64_t dest = r_cleanup_srcid.read() <<
           (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S);
 
@@ -9964,11 +9980,14 @@
             DspinDhccpParam::CLACK_TYPE);
 
-        p_dspin_clack.eop   = true;
-        p_dspin_clack.write = true;
-        p_dspin_clack.data  = flit;
-      }
-      break;
+      p_dspin_clack.eop   = true;
+      p_dspin_clack.write = true;
+      p_dspin_clack.data  = flit;
   }
-
+  else
+  {
+      p_dspin_clack.write = false;
+      p_dspin_clack.eop   = false;
+      p_dspin_clack.data  = 0;
+  }
   ///////////////////////////////////////////////////////////////////
   //  p_dspin_p2m port (CC_RECEIVE FSM)
