Ignore:
Timestamp:
Sep 9, 2013, 11:18:05 AM (11 years ago)
Author:
cfuguet
Message:

Bugfix in vci_cc_vcache_wrapper:

  • The DCACHE FSM must be interruptible by clack and CC request in the XTN_SWITCH state. This is to avoid a deadlock situation between the DCACHE and the ICACHE.

This bug was found in simulation with the next situation:

DCACHE_FSM -> XTN_SWITH state
DCACHE_FSM -> Wait r_dcache_xtn_req to be reset

ICACHE_FSM -> MISS_DIR_UPDT state
ICACHE_FSM -> Wait r_icache_miss_clack to be reset

The ICACHE_FSM only treats the xtn requests in the IDLE state.

The clack to the ICACHE is blocked on the DSPIN port by another
clack to the DCACHE but the DCACHE cannnot treat it as it is
blocked in the XTN_SWITCH state.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp

    r506 r521  
    36453645                                // Caution : the itlb miss requests must be taken
    36463646                                // to avoid dead-lock in case of simultaneous ITLB miss
    3647     {
     3647                                // Caution : the clack and cc requests must be taken
     3648                                // to avoid dead-lock
     3649    {
     3650        // coherence clack request (from DSPIN CLACK)
     3651        if ( r_dcache_clack_req.read() )
     3652        {
     3653            r_dcache_fsm = DCACHE_CC_CHECK;
     3654            r_dcache_fsm_cc_save = r_dcache_fsm.read();
     3655            break;
     3656        }
     3657
     3658        // coherence request (from CC_RECEIVE FSM)
     3659        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
     3660        {
     3661            r_dcache_fsm = DCACHE_CC_CHECK;
     3662            r_dcache_fsm_cc_save = r_dcache_fsm.read();
     3663            break;
     3664        }
     3665
    36483666        // itlb miss request
    36493667        if ( r_icache_tlb_miss_req.read() )
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