Changeset 550 for trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h

Timestamp:

Oct 17, 2013, 8:55:19 PM (11 years ago)

Author:

alain

Message:

Compliance with the mapping_table defined in release 2462.
Modifying the L2 to L3 network, to use the dspin_router_tsar component,
in order to simplify the architecture (no more local crossbar in RAM network.

File:

• trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h (modified) (5 diffs)

trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h

@@ -25 +25 @@
 #include "vci_dspin_initiator_wrapper.h"
 #include "vci_dspin_target_wrapper.h"
-#include "dspin_router.h"
+#include "dspin_router_tsar.h"
 #include "virtual_dspin_router.h"
 #include "vci_multi_dma.h"
@@ -52 +52 @@
     sc_in<bool>                                            p_resetn;
 
-    soclib::caba::VciInitiator<vci_param_ext>*         p_vci_iox_ini;
-    soclib::caba::VciTarget<vci_param_ext>*            p_vci_iox_tgt;
-
-    sc_in<bool>*                                       p_irq[32];  // not always used
-
+    // Thes two ports are used to connect IOB to IOX nework in top cell
+    soclib::caba::VciInitiator<vci_param_ext>*         p_vci_iob_iox_ini;
+    soclib::caba::VciTarget<vci_param_ext>*            p_vci_iob_iox_tgt; 
+
+    // These ports are used to connect IOB to RAM network in top cell
+    soclib::caba::DspinOutput<dspin_ram_cmd_width>*    p_dspin_iob_cmd_out;  
+    soclib::caba::DspinInput<dspin_ram_rsp_width>*     p_dspin_iob_rsp_in;  
+
+    // These ports are used to connect hard IRQ from external peripherals to IOB0
+    sc_in<bool>*                                       p_irq[32];
+
+    // These arrays of ports are used to connect the INT & RAM networks in top cell
         soclib::caba::DspinOutput<dspin_int_cmd_width>**   p_dspin_int_cmd_out;
         soclib::caba::DspinInput<dspin_int_cmd_width>**    p_dspin_int_cmd_in;
@@ -124 +131 @@
         VciSignals<vci_param_ext>             signal_ram_vci_tgt_xram;
 
-    // RAM network DSPIN signals between VCI/DSPIN wrappers and crossbars or routers 
+    // RAM network DSPIN signals between VCI/DSPIN wrappers and routers 
         DspinSignals<dspin_ram_cmd_width>     signal_ram_dspin_cmd_xram_t;
         DspinSignals<dspin_ram_rsp_width>     signal_ram_dspin_rsp_xram_t;
         DspinSignals<dspin_ram_cmd_width>     signal_ram_dspin_cmd_memc_i;
         DspinSignals<dspin_ram_rsp_width>     signal_ram_dspin_rsp_memc_i;
-        DspinSignals<dspin_ram_cmd_width>     signal_ram_dspin_cmd_iobx_i;
-        DspinSignals<dspin_ram_rsp_width>     signal_ram_dspin_rsp_iobx_i;
   
-    // RAM network DSPIN signals between DSPIN routers and DSPIN local crossbars 
-        DspinSignals<dspin_ram_cmd_width>     signal_ram_dspin_cmd_l2g; 
-        DspinSignals<dspin_ram_cmd_width>     signal_ram_dspin_cmd_g2l; 
-        DspinSignals<dspin_ram_rsp_width>     signal_ram_dspin_rsp_l2g; 
-        DspinSignals<dspin_ram_rsp_width>     signal_ram_dspin_rsp_g2l; 
-        
     //////////////////////////////////////
     // Hardwate Components (pointers)
@@ -194 +193 @@
                           dspin_ram_rsp_width>*       xram_ram_wt;
         
-    DspinRouter<dspin_ram_cmd_width>*                 ram_router_cmd;
-    DspinRouter<dspin_ram_rsp_width>*                 ram_router_rsp;
+    DspinRouterTsar<dspin_ram_cmd_width>*                 ram_router_cmd;
+    DspinRouterTsar<dspin_ram_rsp_width>*             ram_router_rsp;
 
         // IO Network Components (not instanciated in all clusters)
@@ -214 +213 @@
                              dspin_ram_rsp_width>*    iob_ram_wi;
         
-    DspinLocalCrossbar<dspin_ram_cmd_width>*          ram_xbar_cmd; 
-    DspinLocalCrossbar<dspin_ram_rsp_width>*          ram_xbar_rsp; 
-
     // cluster constructor
         TsarIobCluster( sc_module_name                     insname,