Changeset 567 for trunk/softs/tsar_boot/include/mips32_registers.h

Timestamp:

Oct 30, 2013, 11:03:43 AM (10 years ago)

Author:

alain

Message:

Introducing CP2 registers mnemonics in mips32_registers.h
Supporting 40 bits physical addresses, multi-clusters TSAR
architectures: XICUs are accessed using the physical address
extension mechanism.

File:

• trunk/softs/tsar_boot/include/mips32_registers.h (modified) (1 diff)

trunk/softs/tsar_boot/include/mips32_registers.h

@@ -54 +54 @@
 #define CP0_EBASE       $15,1
 
+/* CP2 registers */
+
+#define CP2_PTPR             $0 
+#define CP2_MODE             $1
+#define CP2_ICACHE_FLUSH     $2
+#define CP2_DCACHE_FLUSH     $3
+#define CP2_ITLB_INVAL       $4 
+#define CP2_DTLB_INVAL       $5 
+#define CP2_ICACHE_INVAL     $6 
+#define CP2_DCACHE_INVAL     $7
+#define CP2_ICACHE_PREFETCH  $8 
+#define CP2_DCACHE_PREFETCH  $9 
+#define CP2_SYNC             $10 
+#define CP2_IETR             $11 
+#define CP2_DETR             $12 
+#define CP2_IBVAR            $13
+#define CP2_DBVAR            $14
+#define CP2_PARAMS           $15 
+#define CP2_RELEASE          $16 
+#define CP2_DATA_LO          $17     
+#define CP2_DATA_HI          $18         
+#define CP2_ICACHE_INVAL_PA  $19         
+#define CP2_DCACHE_INVAL_PA  $20 
+#define CP2_PADDR_EXT        $24
+
 #endif