Changeset 568


Ignore:
Timestamp:
Oct 30, 2013, 11:19:23 AM (10 years ago)
Author:
cfuguet
Message:

Adding support for TSAR platforms using the vci_io_bridge component.

In this case (USE_IOB=1), when a block is read from the disk controller,
the buffer containing the read data must be invalidated in the Memory
Cache as the transfer is done between the disk controller and the RAM.

Location:
trunk/softs/tsar_boot
Files:
1 added
6 edited

Legend:

Unmodified
Added
Removed
  • trunk/softs/tsar_boot/README.txt

    r554 r568  
    1515             This file is mandatory. This file defines the
    1616             NB_PROCS per cluster, the NB_CLUSTERS and the base address of
    17              the TTY, IOC and XICU devices.
     17             the TTY, IOC, XICU and MEMC (config) devices.
    1818             It defines also:
     19
     20              -> USE_IOB
     21                 This constant is used by the boot_ioc_read function to know
     22                 if the buffer used to store the blocks from the
     23                 block_device must be invalidated in the memory cache after
     24                 the transfert has finished.
    1925
    2026              -> CACHE_COHERENCE
     
    2531
    2632              -> CACHE_LINE_SIZE
    27                  This constant is mandatory if CACHE_COHERENCE=0
     33                 This constant is mandatory if CACHE_COHERENCE=0 or USE_IOB=1
    2834                 This constant defines the size in bytes of a cache line.
    2935
     
    5561                seg_stack_base: Base address of the stack used by processor 0
    5662                during the boot process. read-write data and bss will also
    57                 be there.
     63                be there.
    5864
    5965                seg_boot_base: Base address of the code and read-only data
    60                 defined for this loader
     66                defined for this loader
    6167           
    6268Makefile    Makefile for compile the boot loader.
  • trunk/softs/tsar_boot/conf/platform_fpga_de2-115/defs_platform.h

    r425 r568  
    44#define IRQ_PER_PROC    1
    55
     6#define USE_IOB         0
    67#define CACHE_COHERENCE 1
    78#define CACHE_LINE_SIZE 64//bytes
     
    1314#define TTY_BASE        0xFC000000
    1415#define ICU_BASE        0xFD000000
     16#define MCC_BASE        0xFFFFFFFF // not used
    1517
    1618/* Mandatory argument only for FPGA platforms */
  • trunk/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/defs_platform.h

    r416 r568  
    44#define IRQ_PER_PROC    1
    55
     6#define USE_IOB         0
    67#define CACHE_COHERENCE 1
    78#define CACHE_LINE_SIZE 64 // bytes (ie 16 x 32-bit word)
     
    1314#define ICU_BASE        0x30000000
    1415#define IOC_BASE        0x40000000
     16#define MCC_BASE        0xFFFFFFFF // not used
  • trunk/softs/tsar_boot/conf/platform_vgsb_xicu_mmu/defs_platform.h

    r425 r568  
    44#define IRQ_PER_PROC    1
    55
     6#define USE_IOB         0
    67#define CACHE_COHERENCE 0
    78#define CACHE_LINE_SIZE 16//bytes
     
    1314#define IOC_BASE        0x00F10000
    1415#define TTY_BASE        0x00F20000
     16#define MCC_BASE        0xFFFFFFFF //not used
  • trunk/softs/tsar_boot/include/boot_ioc.h

    r412 r568  
    77#else
    88#include <block_device.h>
     9#include <mcc.h>
    910#endif
    1011
  • trunk/softs/tsar_boot/src/boot_ioc.c

    r554 r568  
    145145// SOCLIB version of the boot_ioc_read function
    146146
     147void boot_buf_invalidate (
     148        const void * buffer,
     149        unsigned int line_size,
     150        unsigned int size);
     151
     152void boot_mcc_invalidate (
     153        const void * buffer,
     154        unsigned int size);
     155
    147156int boot_ioc_read(unsigned int lba, void* buffer, unsigned int count)
    148157{
     
    179188    _boot_ioc_completed();
    180189
    181 #if (CACHE_COHERENCE == 0)
    182     boot_dbuf_invalidate(buffer, CACHE_LINE_SIZE, count * 512);
     190#if (CACHE_COHERENCE == 0) || (USE_IOB == 1)
     191    boot_buf_invalidate(buffer, CACHE_LINE_SIZE, count * 512);
     192#endif
     193
     194#if (USE_IOB == 1)
     195    boot_mcc_invalidate(buffer, count * 512);
    183196#endif
    184197
     
    252265 * buffer (identified by an address and a size).
    253266 */
    254 #if (CACHE_COHERENCE == 0)
    255 void boot_dbuf_invalidate (
     267#if (CACHE_COHERENCE == 0) || (USE_IOB == 1)
     268void boot_buf_invalidate (
    256269        const void * buffer,
    257270        unsigned int line_size,
     
    271284#endif
    272285
     286/**
     287 * boot_mcc_inval()
     288 *
     289 * Invalidate all data cache lines corresponding to a memory
     290 * buffer (identified by an address and a size).
     291 */
     292#if (USE_IOB == 1)
     293void boot_mcc_invalidate (
     294        const void * buffer,
     295        unsigned int size)
     296{
     297    unsigned int * mcc_address = (unsigned int *)MCC_BASE;
     298
     299    // get the hard lock assuring exclusive access to MEMC
     300    while (ioread32(&mcc_address[MCC_LOCK]));
     301
     302    // write invalidate paremeters on the memory cache
     303    // this preloader use only the cluster 0 and then the HI bits are not used
     304   
     305    iowrite32(&mcc_address[MCC_ADDR_LO], (unsigned int) buffer);
     306    iowrite32(&mcc_address[MCC_ADDR_HI], (unsigned int) 0);
     307    iowrite32(&mcc_address[MCC_LENGTH] , (unsigned int) size);
     308    iowrite32(&mcc_address[MCC_CMD]    , (unsigned int) MCC_CMD_INVAL);
     309
     310    // release the lock protecting MEMC
     311    iowrite32(&mcc_address[MCC_LOCK], (unsigned int) 0);
     312}
     313#endif
     314
    273315/*
    274316 * vim: tabstop=4 : shiftwidth=4 : expandtab
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