Index: trunk/modules/vci_io_bridge/caba/source/include/vci_io_bridge.h
===================================================================
--- trunk/modules/vci_io_bridge/caba/source/include/vci_io_bridge.h	(revision 434)
+++ trunk/modules/vci_io_bridge/caba/source/include/vci_io_bridge.h	(revision 585)
@@ -28,6 +28,6 @@
 // This TSAR component is a bridge to access external peripherals
 // connected to an external I/O bus (such as Hypertransport or PCIe).
-// AT the moment, the external I/O bus is modeled by a VCI VGMN component.
 // It connects three VCI networks:
+//
 // - INT network : to receive both configuration requests from processors
 //                 or software driven data access to peripherals.
@@ -40,5 +40,5 @@
 // an - optional - IOMMU service : the 32 bits virtual address is translated
 // to a (up to) 40 bits physical address by a standard SoCLib generic TLB.
-// In case of TLB MISS, the DMA is stalled until the TLB is updated.
+// In case of TLB MISS, the DMA transaction is stalled until the TLB is updated.
 // In case of page fault (illegal access), a VCI error is returned to the
 // faulty peripheral.
@@ -46,13 +46,14 @@
 //   General Constraints:
 //
-// - All VCI fields have the same widths on the EXT and IOX networks.
-// - Only the VCI DATA field can differ between INT and EXT networks,
-//   and the width must be 32 or 64 bits.
+// - All VCI fields have the same widths on the RAM and IOX networks,
+//   and the VCI DATA field is 64 bits.
+// - Only the VCI DATA field differ between INT and IOX/RAM networks,
+//   as the VCI DATA field is 32 bits.
 // - The common VCI ADDRESS width cannot be larger than 64 bits.
 // - All VCI transactions must be included in a single cache line.
 // - Page Tables must have the format required by the SoCLib generic_tlb.
 // - IO's segments must be the same in INT and IOX networks
-// - Write operations on IOMMU configuration registers (PTPR, ACTIVE) can only
-//   be done when DMA_TLB FSM is IDLE. It should, preferably, be done before
+// - Write operations on IOMMU configuration registers (PTPR, ACTIVE) are
+//   delayed until DMA_TLB FSM is IDLE. It should, preferably, be done before
 //   starting any transfers. Pseudo register INVAL may be modified any time.
 ////////////////////////////////////////////////////////////////////////////////
@@ -93,12 +94,13 @@
     : public soclib::caba::BaseModule
 {
-    // Data field can have different widths on INT and EXT networks
-    typedef typename vci_param_ext::fast_data_t     ext_data_t;
-    typedef typename vci_param_int::fast_data_t     int_data_t;
+    // Data and be fields have different widths on INT and EXT networks
+    typedef typename vci_param_ext::data_t          ext_data_t;
+    typedef typename vci_param_int::data_t          int_data_t;
+    typedef typename vci_param_ext::be_t            ext_be_t;
+    typedef typename vci_param_int::be_t            ext_in_t;
 
     // Other fields must be equal   
     typedef typename vci_param_int::fast_addr_t     vci_addr_t; 
     typedef typename vci_param_int::srcid_t         vci_srcid_t;  
-    typedef typename vci_param_int::be_t            vci_be_t;
     typedef typename vci_param_int::trdid_t         vci_trdid_t;
     typedef typename vci_param_int::pktid_t         vci_pktid_t;
@@ -161,6 +163,7 @@
     {  
         CONFIG_CMD_IDLE,
-        CONFIG_CMD_FIFO_PUT_CMD,
-        CONFIG_CMD_FIFO_PUT_RSP,
+        CONFIG_CMD_NEXT,
+        CONFIG_CMD_PUT,
+        CONFIG_CMD_RSP,
 	};
     
@@ -169,5 +172,7 @@
     {  
         CONFIG_RSP_IDLE,
-        CONFIG_RSP_FIFO_PUT,
+        CONFIG_RSP_PUT_LO,
+        CONFIG_RSP_PUT_HI,
+        CONFIG_RSP_PUT_UNC,
     };
     
@@ -241,5 +246,5 @@
     sc_signal<uint32_t>         r_iommu_etr;            // iommu error type
     sc_signal<uint32_t>         r_iommu_bad_id;         // SRCID of faulty peripheral 
-    sc_signal<uint32_t>         r_iommu_wti_enable;     // enable WTI transactions when true 
+    sc_signal<uint32_t>         r_iommu_wti_enable;     // enable WTI transactions  
     sc_signal<vci_addr_t>       r_iommu_wti_paddr;      // address of IOMMU WTI 
     sc_signal<vci_addr_t>*      r_iommu_peri_wti;       // array[32] WTI for peripherals 
@@ -264,5 +269,20 @@
     sc_signal<bool>             r_config_cmd_error;
     sc_signal<uint32_t>         r_config_cmd_inval_vaddr;
-    
+
+    sc_signal<ext_data_t>       r_config_cmd_wdata;
+    sc_signal<ext_be_t>         r_config_cmd_be;
+    sc_signal<vci_plen_t>       r_config_cmd_cmd;
+    sc_signal<vci_addr_t>       r_config_cmd_address;
+    sc_signal<vci_srcid_t>      r_config_cmd_srcid;
+    sc_signal<vci_pktid_t>      r_config_cmd_pktid;
+    sc_signal<vci_trdid_t>      r_config_cmd_trdid;
+    sc_signal<vci_plen_t>       r_config_cmd_plen;
+    sc_signal<vci_clen_t>       r_config_cmd_clen;
+    sc_signal<vci_cons_t>       r_config_cmd_cons;
+    sc_signal<vci_contig_t>     r_config_cmd_contig;
+    sc_signal<vci_cfixed_t>     r_config_cmd_cfixed;
+    sc_signal<vci_wrap_t>       r_config_cmd_wrap;
+    sc_signal<vci_eop_t>        r_config_cmd_eop;
+
     ///////////////////////////////////
     // CONFIG_RSP FSM REGISTERS
@@ -342,5 +362,5 @@
     GenericFifo<vci_trdid_t>    m_dma_cmd_trdid_fifo;
     GenericFifo<vci_pktid_t>    m_dma_cmd_pktid_fifo;
-    GenericFifo<vci_be_t>       m_dma_cmd_be_fifo;
+    GenericFifo<ext_be_t>       m_dma_cmd_be_fifo;
     GenericFifo<vci_cmd_t>      m_dma_cmd_cmd_fifo;
     GenericFifo<vci_contig_t>   m_dma_cmd_contig_fifo;
@@ -366,5 +386,5 @@
     GenericFifo<vci_trdid_t>    m_config_cmd_trdid_fifo;
     GenericFifo<vci_pktid_t>    m_config_cmd_pktid_fifo;
-    GenericFifo<vci_be_t>       m_config_cmd_be_fifo;
+    GenericFifo<ext_be_t>       m_config_cmd_be_fifo;
     GenericFifo<vci_cmd_t>      m_config_cmd_cmd_fifo;
     GenericFifo<vci_contig_t>   m_config_cmd_contig_fifo;
