- Timestamp:
- Dec 4, 2013, 7:51:10 PM (10 years ago)
- File:
-
- 1 edited
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trunk/modules/vci_io_bridge/caba/source/src/vci_io_bridge.cpp
r549 r585 83 83 { 84 84 "CONFIG_CMD_IDLE", 85 "CONFIG_CMD_FIFO_PUT_CMD", 86 "CONFIG_CMD_FIFO_PUT_RSP", 85 "CONFIG_CMD_NEXT", 86 "CONFIG_CMD_PUT", 87 "CONFIG_CMD_RSP", 87 88 }; 88 89 … … 90 91 { 91 92 "CONFIG_RSP_IDLE", 92 "CONFIG_RSP_FIFO_PUT", 93 "CONFIG_RSP_PUT_LO", 94 "CONFIG_RSP_PUT_HI", 95 "CONFIG_RSP_PUT_UNC", 93 96 }; 94 97 … … 170 173 r_config_cmd_error("r_config_cmd_error"), 171 174 r_config_cmd_inval_vaddr("r_config_cmd_inval_vaddr"), 175 r_config_cmd_wdata("r_config_cmd_wdata"), 176 r_config_cmd_be("r_config_cmd_be"), 177 r_config_cmd_cmd("r_config_cmd_wdata"), 178 r_config_cmd_address("r_config_cmd_address"), 179 r_config_cmd_srcid("r_config_cmd_srcid"), 180 r_config_cmd_pktid("r_config_cmd_pktid"), 181 r_config_cmd_trdid("r_config_cmd_trdid"), 182 r_config_cmd_plen("r_config_cmd_plen"), 183 r_config_cmd_clen("r_config_cmd_clen"), 184 r_config_cmd_cons("r_config_cmd_cons"), 185 r_config_cmd_contig("r_config_cmd_contig"), 186 r_config_cmd_cfixed("r_config_cmd_cfixed"), 187 r_config_cmd_wrap("r_config_cmd_wrap"), 188 r_config_cmd_eop("r_config_cmd_eop"), 172 189 173 190 // CONFIG_RSP FSM registers … … 294 311 "VCI_IO_BRIDGE ERROR: VCI ADDRESS width cannot be bigger than 64 bits"); 295 312 296 assert( ( (vci_param_int::B == 4) or (vci_param_int::B == 8)) and297 "VCI_IO_BRIDGE ERROR: VCI DATA width must be 32 or 64bits on internal network");298 299 assert( ( (vci_param_ext::B == 4) or (vci_param_ext::B == 8)) and300 "VCI_IO_BRIDGE ERROR: VCI DATA width must be 32 or64 bits on external network");313 assert( (vci_param_int::B == 4) and 314 "VCI_IO_BRIDGE ERROR: VCI DATA width must be 32 bits on internal network"); 315 316 assert( (vci_param_ext::B == 8) and 317 "VCI_IO_BRIDGE ERROR: VCI DATA width must be 64 bits on external network"); 301 318 302 319 assert( (vci_param_int::S == vci_param_ext::S) and … … 525 542 #if DEBUG_DMA_CMD 526 543 if( m_debug_activated ) 527 std::cout << " <IOB DMA_CMD_IDLE> IOMMU not activated" << std::endl; 544 std::cout << " <IOB DMA_CMD_IDLE> @@@ dma command" << std::endl 545 << " address = " << std::hex << p_vci_tgt_iox.address.read() 546 << " / srcid = " << p_vci_tgt_iox.srcid.read() 547 << " / trdid = " << p_vci_tgt_iox.trdid.read() 548 << " / wdata = " << std::hex << p_vci_tgt_iox.wdata.read() 549 << " / be = " << p_vci_tgt_iox.be.read() 550 << " / plen = " << std::dec << p_vci_tgt_iox.plen.read() 551 << " / eop = " << p_vci_tgt_iox.eop.read() << std::endl; 552 528 553 #endif 529 554 // put DMA transaction into DMA_CMD fifo … … 1214 1239 //////////////////////////////////////////////////////////////////////////////// 1215 1240 // The CONFIG_CMD_FSM handles the VCI commands from the INT network. 1216 // This FSM is mainly intended to handle single flit config transactions, 1217 // but it can also handle software driven, multi-flits data transactions. 1241 // This FSM can handle single flit config transactions, but it can also handle 1242 // software driven, multi-flits data transactions to ROM (read) or FBF (write). 1243 // The write burst transactions must be serialised from 32 to 64 bits width. 1218 1244 // The configuration requests can be local (IO_BRIDGE config registers) 1219 1245 // or remote (config registers of peripherals on IOX network). … … 1222 1248 // - In case of local config request, or in case of segmentation violation, 1223 1249 // the FSM put a VCI response request in CONFIG_RSP fifo. 1224 // - In case of remote transaction, it put the VCI command in CONFIG_CMD fifo. 1250 // - In case of remote transaction, it put the VCI command in CONFIG_CMD fifo, 1251 // and this require two cycles per IOX flit in case of write burst. 1225 1252 /////////////////////////////////////////////////////////////////////////////// 1226 1253 … … 1228 1255 { 1229 1256 ///////////////////// 1230 case CONFIG_CMD_IDLE: // waiting VCI command1257 case CONFIG_CMD_IDLE: // A VCI INT command is always consumed in this state 1231 1258 { 1232 1259 if ( p_vci_tgt_int.cmdval.read() ) … … 1235 1262 #if DEBUG_CONFIG_CMD 1236 1263 if( m_debug_activated ) 1237 std::cout << " <IOB CONFIG_CMD_IDLE> Command received"1238 << " /address = " << std::hex << p_vci_tgt_int.address.read()1239 << " / srcid = " << std::dec <<p_vci_tgt_int.srcid.read()1264 std::cout << " <IOB CONFIG_CMD_IDLE> ### Config Command received" << std::endl 1265 << " address = " << std::hex << p_vci_tgt_int.address.read() 1266 << " / srcid = " << p_vci_tgt_int.srcid.read() 1240 1267 << " / trdid = " << p_vci_tgt_int.trdid.read() 1241 1268 << " / wdata = " << std::hex << p_vci_tgt_int.wdata.read() … … 1247 1274 bool read = (p_vci_tgt_int.cmd.read() == vci_param_int::CMD_READ); 1248 1275 uint32_t cell = (uint32_t)((paddr & 0x1FF)>>2); 1249 1276 bool eop = p_vci_tgt_int.eop.read(); 1277 bool high = (paddr & 0x4); 1278 1250 1279 // chek segments 1251 1280 std::list<soclib::common::Segment>::iterator seg; … … 1264 1293 if ( found and special ) // IO_BRIDGE itself 1265 1294 { 1266 uint32_t rdata = 0; 1267 bool rerror = false; 1295 bool rerror = false; 1296 1297 assert( (p_vci_tgt_int.be.read() == 0xF) and 1298 "ERROR in vci_io_bridge : BE != 0xF for a config access"); 1299 1300 assert( ( eop ) and 1301 "ERROR in vci_io_bridge : local config access must be one flit"); 1268 1302 1269 1303 if ( not read && (cell == IOB_IOMMU_PTPR) ) // WRITE PTPR … … 1273 1307 else if ( read && (cell == IOB_IOMMU_PTPR) ) // READ PTPR 1274 1308 { 1275 r data = r_iommu_ptpr.read();1309 r_config_cmd_rdata = r_iommu_ptpr.read(); 1276 1310 } 1277 1311 else if( not read && (cell == IOB_WTI_ENABLE)) // WRITE WTI_ENABLE … … 1281 1315 else if( read && (cell == IOB_WTI_ENABLE)) // READ WTI ENABLE 1282 1316 { 1283 r data = r_iommu_wti_enable.read();1317 r_config_cmd_rdata = r_iommu_wti_enable.read(); 1284 1318 } 1285 1319 else if( read && (cell == IOB_IOMMU_BVAR)) // READ BVAR 1286 1320 { 1287 r data = r_iommu_bvar.read();1321 r_config_cmd_rdata = r_iommu_bvar.read(); 1288 1322 } 1289 1323 else if( read && (cell == IOB_IOMMU_ETR)) // READ ETR 1290 1324 { 1291 r data = r_iommu_etr.read();1325 r_config_cmd_rdata = r_iommu_etr.read(); 1292 1326 } 1293 1327 else if( read && (cell == IOB_IOMMU_BAD_ID)) // READ BAD_ID 1294 1328 { 1295 r data = r_iommu_bad_id.read();1329 r_config_cmd_rdata = r_iommu_bad_id.read(); 1296 1330 } 1297 1331 else if( not read && (cell == IOB_INVAL_PTE)) // WRITE INVAL_PTE … … 1306 1340 else if( read && (cell == IOB_WTI_ADDR_LO)) // READ WTI_PADDR_LO 1307 1341 { 1308 r data = (uint32_t)r_iommu_wti_paddr.read();1342 r_config_cmd_rdata = (uint32_t)r_iommu_wti_paddr.read(); 1309 1343 } 1310 1344 else if( not read && (cell == IOB_WTI_ADDR_HI)) // WRITE WTI_PADDR_HI … … 1315 1349 else if( read && (cell == IOB_WTI_ADDR_HI)) // READ WTI_PADDR_HI 1316 1350 { 1317 r data = (uint32_t)(r_iommu_wti_paddr.read()>>32);1351 r_config_cmd_rdata = (uint32_t)(r_iommu_wti_paddr.read()>>32); 1318 1352 } 1319 1353 else if( not read && ((cell >= IOB_PERI_WTI_BEGIN) // WRITE PERI WTI … … 1333 1367 size_t index = (cell - IOB_PERI_WTI_BEGIN)/2; 1334 1368 bool high = (cell - IOB_PERI_WTI_BEGIN)%2; 1335 if ( high ) rdata = (uint32_t)(r_iommu_peri_wti[index].read()>>32); 1336 else rdata = (uint32_t)(r_iommu_peri_wti[index].read()); 1369 if ( high ) r_config_cmd_rdata = 1370 (uint32_t)(r_iommu_peri_wti[index].read()>>32); 1371 else r_config_cmd_rdata = 1372 (uint32_t)(r_iommu_peri_wti[index].read()); 1337 1373 } 1338 1374 else // Error: Wrong address, or invalid operation. … … 1340 1376 rerror = true; 1341 1377 } 1342 r_config_cmd_rdata = rdata;1343 1378 r_config_cmd_error = rerror; 1344 r_config_cmd_fsm = CONFIG_CMD_ FIFO_PUT_RSP;1379 r_config_cmd_fsm = CONFIG_CMD_RSP; 1345 1380 } 1346 1381 else if ( found ) // remote peripheral 1347 1382 { 1348 r_config_cmd_fsm = CONFIG_CMD_FIFO_PUT_CMD; 1349 } 1350 else // out of segment 1351 { 1352 r_config_cmd_rdata = 0; 1383 r_config_cmd_address = p_vci_tgt_int.address.read(); 1384 r_config_cmd_srcid = p_vci_tgt_int.srcid.read(); 1385 r_config_cmd_trdid = p_vci_tgt_int.trdid.read(); 1386 r_config_cmd_pktid = p_vci_tgt_int.pktid.read(); 1387 r_config_cmd_pktid = p_vci_tgt_int.pktid.read(); 1388 r_config_cmd_plen = p_vci_tgt_int.plen.read(); 1389 r_config_cmd_cmd = p_vci_tgt_int.cmd.read(); 1390 r_config_cmd_cons = p_vci_tgt_int.cons.read(); 1391 r_config_cmd_clen = p_vci_tgt_int.clen.read(); 1392 r_config_cmd_wrap = p_vci_tgt_int.wrap.read(); 1393 r_config_cmd_contig = p_vci_tgt_int.contig.read(); 1394 r_config_cmd_cfixed = p_vci_tgt_int.cfixed.read(); 1395 1396 if( eop ) // single flit command 1397 { 1398 if ( high ) // HI word 1399 { 1400 r_config_cmd_wdata = ((ext_data_t)p_vci_tgt_int.wdata.read())<<32; 1401 r_config_cmd_be = ((ext_be_t)p_vci_tgt_int.be.read())<<4; 1402 r_config_cmd_eop = true; 1403 r_config_cmd_fsm = CONFIG_CMD_PUT; 1404 } 1405 else // LO word 1406 { 1407 r_config_cmd_wdata = ((ext_data_t)p_vci_tgt_int.wdata.read()); 1408 r_config_cmd_be = ((ext_be_t)p_vci_tgt_int.be.read()); 1409 r_config_cmd_eop = true; 1410 r_config_cmd_fsm = CONFIG_CMD_PUT; 1411 } 1412 } 1413 else // multi-flits write 1414 { 1415 if ( high ) // MSB word 1416 { 1417 r_config_cmd_wdata = ((ext_data_t)p_vci_tgt_int.wdata.read())<<32; 1418 r_config_cmd_be = ((ext_be_t)p_vci_tgt_int.be.read())<<4; 1419 r_config_cmd_eop = false; 1420 r_config_cmd_fsm = CONFIG_CMD_PUT; 1421 } 1422 else // LSB word 1423 { 1424 r_config_cmd_wdata = ((ext_data_t)p_vci_tgt_int.wdata.read()); 1425 r_config_cmd_be = ((ext_be_t)p_vci_tgt_int.be.read()); 1426 r_config_cmd_eop = false; 1427 r_config_cmd_fsm = CONFIG_CMD_NEXT; 1428 } 1429 } 1430 } 1431 else // out of segment address 1432 { 1433 r_config_cmd_rdata = 0; 1353 1434 r_config_cmd_error = true; 1354 r_config_cmd_fsm = CONFIG_CMD_FIFO_PUT_RSP;1435 if( eop ) r_config_cmd_fsm = CONFIG_CMD_RSP; 1355 1436 } 1356 1437 } // end if cmdval 1357 1438 break; 1358 1439 } 1359 ///////////////////////////// 1360 case CONFIG_CMD_FIFO_PUT_CMD: // transmit VCI command from the INT network 1361 // to the CONFIG_CMD fifo to IOX network 1440 ///////////////////// 1441 case CONFIG_CMD_NEXT: // Consume the second flit for a multi-flits write 1442 { 1443 if ( p_vci_tgt_int.cmdval.read() ) 1444 { 1445 vci_addr_t paddr = p_vci_tgt_int.address.read(); 1446 bool high = (paddr & 0x4 == 0x4); 1447 bool eop = p_vci_tgt_int.eop.read(); 1448 1449 assert( (paddr == r_config_cmd_address.read() + 4) and high and 1450 "ERROR in vci_io_bridge : addresses must be contiguous in write burst" ); 1451 1452 r_config_cmd_wdata = r_config_cmd_wdata.read() | 1453 ((ext_data_t)p_vci_tgt_int.wdata.read()<<32); 1454 r_config_cmd_be = r_config_cmd_be.read() | 1455 ((ext_be_t)p_vci_tgt_int.be.read()<<4); 1456 r_config_cmd_eop = eop; 1457 r_config_cmd_fsm = CONFIG_CMD_PUT; 1458 } 1459 break; 1460 } 1461 //////////////////// 1462 case CONFIG_CMD_PUT: // try to post a command to CONFIG_CMD fifo (to IOX network) 1362 1463 { 1363 1464 config_cmd_fifo_put = true; 1364 1465 1365 if ( p_vci_tgt_int.cmdval.read() andm_config_cmd_addr_fifo.wok() )1466 if ( m_config_cmd_addr_fifo.wok() ) 1366 1467 { 1367 1468 1368 1469 #if DEBUG_CONFIG_CMD 1369 1470 if( m_debug_activated ) 1370 std::cout << " <IOB CONFIG_CMD_FIFO_PUT_CMD> Transmit VCI command to IOX network" 1371 << " : address = " << std::hex << p_vci_tgt_int.address.read() 1372 << " / srcid = " << p_vci_tgt_int.srcid.read() 1471 std::cout << " <IOB CONFIG_CMD_PUT> Transmit VCI command to IOX network" 1472 << " : address = " << std::hex << r_config_cmd_address.read() 1473 << " / srcid = " << r_config_cmd_srcid.read() 1474 << " / eop = " << r_config_cmd_eop.read() 1373 1475 << std::endl; 1374 1476 #endif 1375 if( p_vci_tgt_int.eop.read() )r_config_cmd_fsm = CONFIG_CMD_IDLE;1376 } 1377 break; 1378 } 1379 //////////////////// /////////1380 case CONFIG_CMD_ FIFO_PUT_RSP: // Try to put a response in CONFIG_RSP fifo,1381 // for a local configuration transaction.1382 1383 1384 { 1385 if ( p_vci_tgt_int.cmdval.read() andr_alloc_fifo_config_rsp_local.read() )1477 r_config_cmd_fsm = CONFIG_CMD_IDLE; 1478 } 1479 break; 1480 } 1481 //////////////////// 1482 case CONFIG_CMD_RSP: // Try to put a response in CONFIG_RSP fifo, for 1483 // a local configuration transaction or a segment error. 1484 // The FIFO is shared with CONFIG_RSP FSM 1485 // and must we wait for allocation... 1486 { 1487 if ( r_alloc_fifo_config_rsp_local.read() ) 1386 1488 { 1387 1489 config_rsp_fifo_put = true; … … 1392 1494 #if DEBUG_CONFIG_CMD 1393 1495 if( m_debug_activated ) 1394 std::cout << " <IOB CONFIG_CMD_ FIFO_PUT_RSP> Response to a local configuration request"1496 std::cout << " <IOB CONFIG_CMD_RSP> Response to a local configuration request" 1395 1497 << std::endl; 1396 1498 #endif 1397 if( p_vci_tgt_int.eop.read() )r_config_cmd_fsm = CONFIG_CMD_IDLE;1499 r_config_cmd_fsm = CONFIG_CMD_IDLE; 1398 1500 } 1399 1501 } … … 1403 1505 1404 1506 ////////////////////////////////////////////////////////////////////////////// 1405 // The CONFIG_RSP_FSM handles the VCI responses from the periherals1507 // The CONFIG_RSP_FSM handles the 64 bits VCI responses from the periherals 1406 1508 // on the IOX network and writes the responses in the CONFIG_RSP fifo. 1407 // The VCI response flit is only consumed in the FIFO_PUT state. 1408 // This FSM is mainly intended to handle single flit config transactions, 1409 // but it can also handle software driven, multi-flits data transactions. 1509 // This FSM handle both single flit config responses, and multi-flits 1510 // read responses (ROM), where data must be serialised (64 bits -> 32 bits). 1511 // Note: We use the VCI RPKTID field to distinguish between read cached 1512 // (multi-flits response) and others (single flit response). 1513 // The VCI response flit is only consumed in the PUT_UNC or PUT_HI states. 1410 1514 ////////////////////////////////////////////////////////////////////////////// 1411 1515 … … 1414 1518 ///////////////////// 1415 1519 case CONFIG_RSP_IDLE: // waiting a VCI response from IOX network 1520 // flit on IOX network is not consumed 1416 1521 { 1417 1522 if ( p_vci_ini_iox.rspval.read() ) 1418 1523 { 1419 r_config_rsp_fsm = CONFIG_RSP_FIFO_PUT; 1524 if ( (p_vci_ini_iox.rpktid.read() & 0x5) == 0x1 ) // multi-flits response 1525 { 1526 r_config_rsp_fsm = CONFIG_RSP_PUT_LO; 1527 } 1528 else // single flit response 1529 { 1530 r_config_rsp_fsm = CONFIG_RSP_PUT_UNC; 1531 1532 assert( p_vci_ini_iox.reop.read() and 1533 "ERROR in vci_io_bridge : a remote config response should be one flit"); 1534 } 1420 1535 } 1421 1536 break; 1422 1537 } 1423 ///////////////////////// 1424 case CONFIG_RSP_FIFO_PUT: // try to write into CONFIG_RSP fifo 1425 // as soon as it is allocated 1426 { 1427 if ( p_vci_ini_iox.rspval.read() and not r_alloc_fifo_config_rsp_local.read() ) 1428 { 1429 config_rsp_fifo_put = true; 1430 1431 if ( m_config_rsp_data_fifo.wok() ) 1432 { 1433 if ( p_vci_ini_iox.reop.read() ) r_config_rsp_fsm = CONFIG_RSP_IDLE; 1538 /////////////////////// 1539 case CONFIG_RSP_PUT_LO: // try to write 32 low bits into CONFIG_RSP fifo 1540 // flit on IOX network is not consumed 1541 { 1542 if ( not r_alloc_fifo_config_rsp_local.read() and m_config_rsp_data_fifo.wok() ) 1543 { 1544 r_config_rsp_fsm = CONFIG_RSP_PUT_HI; 1434 1545 1435 1546 #if DEBUG_CONFIG_RSP 1436 1547 if( m_debug_activated ) 1437 std::cout << " <IOB CONFIG_RSP_ FIFO_PUT> Pushresponse into CONFIG_RSP fifo:"1548 std::cout << " <IOB CONFIG_RSP_PUT_LO> Push multi-flit response into CONFIG_RSP fifo:" 1438 1549 << " / rsrcid = " << std::hex << p_vci_ini_iox.rsrcid.read() 1439 1550 << " / rtrdid = " << p_vci_ini_iox.rtrdid.read() 1440 << " / rdata = " << p_vci_ini_iox.rdata.read() 1551 << " / rpktid = " << p_vci_ini_iox.rpktid.read() 1552 << " / rdata = " << (uint32_t)p_vci_ini_iox.rdata.read() 1553 << " / reop = " << false 1554 << " / rerror = " << p_vci_ini_iox.rerror.read() << std::endl; 1555 #endif 1556 } 1557 break; 1558 } 1559 /////////////////////// 1560 case CONFIG_RSP_PUT_HI: // try to write 32 high bits into CONFIG_RSP fifo 1561 // flit on IOX network is consumed if success 1562 { 1563 if ( not r_alloc_fifo_config_rsp_local.read() and m_config_rsp_data_fifo.wok() ) 1564 { 1565 if( p_vci_ini_iox.reop.read() ) r_config_rsp_fsm = CONFIG_RSP_IDLE; 1566 else r_config_rsp_fsm = CONFIG_RSP_PUT_LO; 1567 1568 #if DEBUG_CONFIG_RSP 1569 if( m_debug_activated ) 1570 std::cout << " <IOB CONFIG_RSP_PUT_HI> Push multi-flit response into CONFIG_RSP fifo:" 1571 << " / rsrcid = " << std::hex << p_vci_ini_iox.rsrcid.read() 1572 << " / rtrdid = " << p_vci_ini_iox.rtrdid.read() 1573 << " / rpktid = " << p_vci_ini_iox.rpktid.read() 1574 << " / rdata = " << (uint32_t)(p_vci_ini_iox.rdata.read()>>32) 1441 1575 << " / reop = " << p_vci_ini_iox.reop.read() 1442 1576 << " / rerror = " << p_vci_ini_iox.rerror.read() << std::endl; 1443 1577 #endif 1444 } 1445 1578 } 1579 break; 1580 } 1581 //////////////////////// 1582 case CONFIG_RSP_PUT_UNC: // try to write single flit into CONFIG_RSP fifo 1583 // flit on IOX network is consumed if success 1584 { 1585 if ( not r_alloc_fifo_config_rsp_local.read() and m_config_rsp_data_fifo.wok() ) 1586 { 1587 r_config_rsp_fsm = CONFIG_RSP_IDLE; 1588 1589 #if DEBUG_CONFIG_RSP 1590 if( m_debug_activated ) 1591 std::cout << " <IOB CONFIG_RSP_PUT_UNC> Push single flit response into CONFIG_RSP fifo:" 1592 << " / rsrcid = " << std::hex << p_vci_ini_iox.rsrcid.read() 1593 << " / rtrdid = " << p_vci_ini_iox.rtrdid.read() 1594 << " / rpktid = " << p_vci_ini_iox.rpktid.read() 1595 << " / rdata = " << (uint32_t)p_vci_ini_iox.rdata.read() 1596 << " / reop = " << true 1597 << " / rerror = " << p_vci_ini_iox.rerror.read() << std::endl; 1598 #endif 1446 1599 } 1447 1600 break; … … 1575 1728 assert( ( (p_vci_ini_int.rerror.read()&0x1) == 0 ) and 1576 1729 "VCI_IO_BRIDGE ERROR: IRQ Write response error !!!" ); 1577 // TODO traiter errorusing the IOMMU IRQ1730 // TODO handling error when using the IOMMU IRQ 1578 1731 1579 1732 #if DEBUG_MISS_WTI … … 1641 1794 if ( r_alloc_fifo_config_rsp_local.read() ) 1642 1795 { 1643 if ( (r_config_rsp_fsm.read() == CONFIG_RSP_FIFO_PUT) and1644 (r_config_cmd_fsm.read() != CONFIG_CMD_ FIFO_PUT_RSP) )1796 if ( (r_config_rsp_fsm.read() != CONFIG_RSP_IDLE) and // config_rsp_fsm requiring 1797 (r_config_cmd_fsm.read() != CONFIG_CMD_RSP) ) // config_cmd_fsm not requiring 1645 1798 r_alloc_fifo_config_rsp_local = false; 1646 1799 } 1647 1800 else 1648 1801 { 1649 if ( (r_config_cmd_fsm.read() == CONFIG_CMD_ FIFO_PUT_RSP) and1650 (r_config_rsp_fsm.read() != CONFIG_RSP_FIFO_PUT) )1802 if ( (r_config_cmd_fsm.read() == CONFIG_CMD_RSP) and // config_cmd_fsm requiring 1803 (r_config_rsp_fsm.read() == CONFIG_RSP_IDLE) ) // config_rsp_fsm not requiring 1651 1804 r_alloc_fifo_config_rsp_local = true; 1652 1805 } … … 1786 1939 m_config_cmd_addr_fifo.update( config_cmd_fifo_get, 1787 1940 config_cmd_fifo_put, 1788 p_vci_tgt_int.address.read() );1941 r_config_cmd_address.read() ); 1789 1942 m_config_cmd_cmd_fifo.update( config_cmd_fifo_get, 1790 1943 config_cmd_fifo_put, 1791 p_vci_tgt_int.cmd.read() );1944 r_config_cmd_cmd.read() ); 1792 1945 m_config_cmd_contig_fifo.update( config_cmd_fifo_get, 1793 1946 config_cmd_fifo_put, 1794 p_vci_tgt_int.contig.read() );1947 r_config_cmd_contig.read() ); 1795 1948 m_config_cmd_cons_fifo.update( config_cmd_fifo_get, 1796 1949 config_cmd_fifo_put, 1797 p_vci_tgt_int.cons.read() );1950 r_config_cmd_cons.read() ); 1798 1951 m_config_cmd_plen_fifo.update( config_cmd_fifo_get, 1799 1952 config_cmd_fifo_put, 1800 p_vci_tgt_int.plen.read() );1953 r_config_cmd_plen.read() ); 1801 1954 m_config_cmd_wrap_fifo.update( config_cmd_fifo_get, 1802 1955 config_cmd_fifo_put, 1803 p_vci_tgt_int.wrap.read() );1956 r_config_cmd_wrap.read() ); 1804 1957 m_config_cmd_cfixed_fifo.update( config_cmd_fifo_get, 1805 1958 config_cmd_fifo_put, 1806 p_vci_tgt_int.cfixed.read() );1959 r_config_cmd_cfixed.read() ); 1807 1960 m_config_cmd_clen_fifo.update( config_cmd_fifo_get, 1808 1961 config_cmd_fifo_put, 1809 p_vci_tgt_int.clen.read() );1962 r_config_cmd_clen.read() ); 1810 1963 m_config_cmd_srcid_fifo.update( config_cmd_fifo_get, 1811 1964 config_cmd_fifo_put, 1812 p_vci_tgt_int.srcid.read() );1965 r_config_cmd_srcid.read() ); 1813 1966 m_config_cmd_trdid_fifo.update( config_cmd_fifo_get, 1814 1967 config_cmd_fifo_put, 1815 p_vci_tgt_int.trdid.read() );1968 r_config_cmd_trdid.read() ); 1816 1969 m_config_cmd_pktid_fifo.update( config_cmd_fifo_get, 1817 1970 config_cmd_fifo_put, 1818 p_vci_tgt_int.pktid.read() );1971 r_config_cmd_pktid.read() ); 1819 1972 m_config_cmd_data_fifo.update( config_cmd_fifo_get, 1820 1973 config_cmd_fifo_put, 1821 (ext_data_t)p_vci_tgt_int.wdata.read() );1974 r_config_cmd_wdata.read() ); 1822 1975 m_config_cmd_be_fifo.update( config_cmd_fifo_get, 1823 1976 config_cmd_fifo_put, 1824 p_vci_tgt_int.be.read() );1977 r_config_cmd_be.read() ); 1825 1978 m_config_cmd_eop_fifo.update( config_cmd_fifo_get, 1826 1979 config_cmd_fifo_put, 1827 p_vci_tgt_int.eop.read() );1980 r_config_cmd_eop.read() ); 1828 1981 1829 1982 ////////////////////////////////////////////////////////////////////////// … … 1837 1990 m_config_rsp_data_fifo.update( config_rsp_fifo_get, 1838 1991 config_rsp_fifo_put, 1839 (int_data_t)r_config_cmd_rdata.read() );1992 r_config_cmd_rdata.read() ); 1840 1993 m_config_rsp_rsrcid_fifo.update( config_rsp_fifo_get, 1841 1994 config_rsp_fifo_put, … … 1857 2010 // response for a remote transaction 1858 2011 { 2012 // PUT depends on CONFIG_RSP FSM state 2013 uint32_t rdata; 2014 bool reop; 2015 if ( r_config_rsp_fsm.read() == CONFIG_RSP_PUT_HI ) 2016 { 2017 config_rsp_fifo_put = true; 2018 rdata = (uint32_t)(p_vci_ini_iox.rdata.read()>>32); 2019 reop = p_vci_ini_iox.reop.read(); 2020 } 2021 else if ( r_config_rsp_fsm.read() == CONFIG_RSP_PUT_LO ) 2022 { 2023 config_rsp_fifo_put = true; 2024 rdata = (uint32_t)(p_vci_ini_iox.rdata.read()); 2025 reop = false; 2026 } 2027 else if ( r_config_rsp_fsm.read() == CONFIG_RSP_PUT_UNC ) 2028 { 2029 config_rsp_fifo_put = true; 2030 rdata = (uint32_t)(p_vci_ini_iox.rdata.read()); 2031 reop = true; 2032 } 2033 else 2034 { 2035 config_rsp_fifo_put = false; 2036 rdata = 0; 2037 reop = false;; 2038 } 2039 1859 2040 m_config_rsp_data_fifo.update( config_rsp_fifo_get, 1860 2041 config_rsp_fifo_put, 1861 (int_data_t)p_vci_ini_iox.rdata.read());2042 rdata ); 1862 2043 m_config_rsp_rsrcid_fifo.update( config_rsp_fifo_get, 1863 2044 config_rsp_fifo_put, … … 1871 2052 m_config_rsp_reop_fifo.update( config_rsp_fifo_get, 1872 2053 config_rsp_fifo_put, 1873 p_vci_ini_iox.reop.read());2054 reop ); 1874 2055 m_config_rsp_rerror_fifo.update( config_rsp_fifo_get, 1875 2056 config_rsp_fifo_put, … … 1920 2101 p_vci_tgt_iox.cmdack = m_dma_rsp_data_fifo.wok(); 1921 2102 break; 1922 } // end switch r_dma_cmd_fsm2103 } 1923 2104 1924 2105 // VCI target response on IOX network … … 1948 2129 p_vci_ini_iox.cmd = m_config_cmd_cmd_fifo.read(); 1949 2130 p_vci_ini_iox.contig = m_config_cmd_contig_fifo.read(); 1950 p_vci_ini_iox.wdata = (ext_data_t)m_config_cmd_data_fifo.read();2131 p_vci_ini_iox.wdata = m_config_cmd_data_fifo.read(); 1951 2132 p_vci_ini_iox.eop = m_config_cmd_eop_fifo.read(); 1952 2133 p_vci_ini_iox.cons = m_config_cmd_cons_fifo.read(); … … 1965 2146 { 1966 2147 case CONFIG_CMD_IDLE: 2148 p_vci_tgt_int.cmdack = true; 2149 break; 2150 case CONFIG_CMD_NEXT: 2151 p_vci_tgt_int.cmdack = true; 2152 break; 2153 case CONFIG_CMD_PUT: 1967 2154 p_vci_tgt_int.cmdack = false; 1968 2155 break; 1969 case CONFIG_CMD_FIFO_PUT_CMD: 1970 p_vci_tgt_int.cmdack = m_config_cmd_addr_fifo.wok(); 1971 break; 1972 case CONFIG_CMD_FIFO_PUT_RSP: 1973 p_vci_tgt_int.cmdack = m_config_rsp_data_fifo.wok() and 1974 r_alloc_fifo_config_rsp_local.read(); 1975 break; 1976 }// end switch r_config_cmd_fsm 2156 case CONFIG_CMD_RSP: 2157 p_vci_tgt_int.cmdack = false; 2158 break; 2159 } 1977 2160 1978 2161 // VCI target response on INT network … … 1991 2174 1992 2175 p_vci_ini_iox.rspack = m_config_rsp_data_fifo.wok() and 1993 (r_config_rsp_fsm.read() == CONFIG_RSP_FIFO_PUT) and 1994 not r_alloc_fifo_config_rsp_local.read(); 2176 not r_alloc_fifo_config_rsp_local.read() and 2177 ( (r_config_rsp_fsm.read() == CONFIG_RSP_PUT_UNC) or 2178 (r_config_rsp_fsm.read() == CONFIG_RSP_PUT_HI) ); 1995 2179 1996 2180 // VCI initiator command on INT network
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