- Timestamp:
- Dec 11, 2013, 12:13:44 PM (10 years ago)
- File:
-
- 1 edited
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trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r582 r596 33 33 34 34 #include "../include/vci_mem_cache.h" 35 #include "mem_cache.h" 35 36 36 37 ////// debug services ///////////////////////////////////////////////////////////// … … 392 393 m_broadcast_boundaries(0x7C1F), 393 394 395 // CONFIG interface 396 m_config_addr_mask((1<<12)-1), 397 398 m_config_regr_width(7), 399 m_config_func_width(3), 400 m_config_regr_idx_mask((1<<m_config_regr_width)-1), 401 m_config_func_idx_mask((1<<m_config_func_width)-1), 394 402 395 403 // FIFOs … … 652 660 } 653 661 662 ///////////////////////////////////////////////////// 663 tmpl(int)::read_instrumentation(uint32_t regr, uint32_t & rdata) 664 ///////////////////////////////////////////////////// 665 { 666 int error = 0; 667 668 switch(regr) 669 { 670 /////////////////////////////////////////////////////// 671 // DIRECT instrumentation registers // 672 // Registers of 32 bits and therefore only LO is // 673 // implemented. // 674 // // 675 // The HI may be used in future implementations // 676 /////////////////////////////////////////////////////// 677 678 // LOCAL 679 680 case MEMC_LOCAL_READ_LO : rdata = m_cpt_read_local ; break; 681 case MEMC_LOCAL_WRITE_LO : rdata = m_cpt_write_flits_local ; break; 682 case MEMC_LOCAL_LL_LO : rdata = m_cpt_ll_local ; break; 683 case MEMC_LOCAL_SC_LO : rdata = m_cpt_sc_local ; break; 684 case MEMC_LOCAL_CAS_LO : rdata = m_cpt_cas_local ; break; 685 case MEMC_LOCAL_READ_HI : 686 case MEMC_LOCAL_WRITE_HI : 687 case MEMC_LOCAL_LL_HI : 688 case MEMC_LOCAL_SC_HI : 689 case MEMC_LOCAL_CAS_HI : rdata = 0; break; 690 691 // REMOTE 692 693 case MEMC_REMOTE_READ_LO : rdata = m_cpt_read_remote ; break; 694 case MEMC_REMOTE_WRITE_LO : rdata = m_cpt_write_flits_remote ; break; 695 case MEMC_REMOTE_LL_LO : rdata = m_cpt_ll_remote ; break; 696 case MEMC_REMOTE_SC_LO : rdata = m_cpt_sc_remote ; break; 697 case MEMC_REMOTE_CAS_LO : rdata = m_cpt_cas_remote ; break; 698 case MEMC_REMOTE_READ_HI : 699 case MEMC_REMOTE_WRITE_HI : 700 case MEMC_REMOTE_LL_HI : 701 case MEMC_REMOTE_SC_HI : 702 case MEMC_REMOTE_CAS_HI : rdata = 0; break; 703 704 // COST 705 706 case MEMC_COST_READ_LO : rdata = m_cpt_read_cost ; break; 707 case MEMC_COST_WRITE_LO : rdata = m_cpt_write_cost; break; 708 case MEMC_COST_LL_LO : rdata = m_cpt_ll_cost ; break; 709 case MEMC_COST_SC_LO : rdata = m_cpt_sc_cost ; break; 710 case MEMC_COST_CAS_LO : rdata = m_cpt_cas_cost ; break; 711 case MEMC_COST_READ_HI : 712 case MEMC_COST_WRITE_HI : 713 case MEMC_COST_LL_HI : 714 case MEMC_COST_SC_HI : 715 case MEMC_COST_CAS_HI : rdata = 0; break; 716 717 /////////////////////////////////////////////////////// 718 // COHERENCE instrumentation registers // 719 // Registers of 32 bits and therefore only LO is // 720 // implemented. // 721 // // 722 // The HI may be used in future implementations // 723 /////////////////////////////////////////////////////// 724 725 // LOCAL 726 727 case MEMC_LOCAL_MUPDATE_LO : rdata = m_cpt_update_local ; break; 728 case MEMC_LOCAL_MINVAL_LO : rdata = m_cpt_minval_local ; break; 729 case MEMC_LOCAL_CLEANUP_LO : rdata = m_cpt_cleanup_local; break; 730 case MEMC_LOCAL_MUPDATE_HI : 731 case MEMC_LOCAL_MINVAL_HI : 732 case MEMC_LOCAL_CLEANUP_HI : rdata = 0; break; 733 734 // REMOTE 735 736 case MEMC_REMOTE_MUPDATE_LO : rdata = m_cpt_update_remote ; break; 737 case MEMC_REMOTE_MINVAL_LO : rdata = m_cpt_minval_remote ; break; 738 case MEMC_REMOTE_CLEANUP_LO : rdata = m_cpt_cleanup_remote; break; 739 case MEMC_REMOTE_MUPDATE_HI : 740 case MEMC_REMOTE_MINVAL_HI : 741 case MEMC_REMOTE_CLEANUP_HI : rdata = 0; break; 742 743 // COST 744 745 case MEMC_COST_MUPDATE_LO : rdata = m_cpt_update_cost ; break; 746 case MEMC_COST_MINVAL_LO : rdata = m_cpt_minval_cost ; break; 747 case MEMC_COST_CLEANUP_LO : rdata = m_cpt_cleanup_cost ; break; 748 case MEMC_COST_MUPDATE_HI : 749 case MEMC_COST_MINVAL_HI : 750 case MEMC_COST_CLEANUP_HI : rdata = 0; break; 751 752 // TOTAL 753 754 case MEMC_TOTAL_MUPDATE_LO : rdata = m_cpt_update ; break; 755 case MEMC_TOTAL_MINVAL_LO : rdata = m_cpt_minval ; break; 756 case MEMC_TOTAL_BINVAL_LO : rdata = m_cpt_binval ; break; 757 case MEMC_TOTAL_MUPDATE_HI : 758 case MEMC_TOTAL_MINVAL_HI : 759 case MEMC_TOTAL_BINVAL_HI : rdata = 0; break; 760 761 // unknown register 762 763 default : error = 1; 764 } 765 766 return error; 767 } 654 768 655 769 ////////////////////////////////////////////////// … … 722 836 << "[022] UPDT COST (FLITS * DIST) = " << m_cpt_update_cost << std::endl 723 837 << std::endl 724 << "[023] REQUESTS TRIG. M_INV = " << m_cpt_m _inval << std::endl725 << "[024] LOCAL M_INV = " << m_cpt_m _inval_local << std::endl726 << "[025] REMOTE M_INV = " << m_cpt_m _inval_remote << std::endl727 << "[026] M_INV COST (FLITS * DIST) = " << m_cpt_m _inval_cost << std::endl838 << "[023] REQUESTS TRIG. M_INV = " << m_cpt_minval << std::endl 839 << "[024] LOCAL M_INV = " << m_cpt_minval_local << std::endl 840 << "[025] REMOTE M_INV = " << m_cpt_minval_remote << std::endl 841 << "[026] M_INV COST (FLITS * DIST) = " << m_cpt_minval_cost << std::endl 728 842 << std::endl 729 << "[027] BROADCAT INVAL = " << m_cpt_b r_inval << std::endl843 << "[027] BROADCAT INVAL = " << m_cpt_binval << std::endl 730 844 << std::endl 731 845 << "[028] LOCAL CLEANUP = " << m_cpt_cleanup_local << std::endl … … 771 885 << "[117] AV. REMOTE UPDT PER UP REQ = " << (double) m_cpt_update_remote / m_cpt_update << std::endl 772 886 << std::endl 773 << "[118] INVAL MULTICAST RATE = " << (double) m_cpt_m _inval / m_cpt_cycles << std::endl774 << "[119] AVE. INVAL PER M_INV = " << (double) (m_cpt_m _inval_local + m_cpt_m_inval_remote) / m_cpt_m_inval << std::endl775 << "[120] AV. LOC INV PER M_INV = " << (double) m_cpt_m _inval_local / m_cpt_m_inval << std::endl776 << "[121] AV. REM INV PER M_INV = " << (double) m_cpt_m _inval_remote / m_cpt_m_inval << std::endl887 << "[118] INVAL MULTICAST RATE = " << (double) m_cpt_minval / m_cpt_cycles << std::endl 888 << "[119] AVE. INVAL PER M_INV = " << (double) (m_cpt_minval_local + m_cpt_minval_remote) / m_cpt_minval << std::endl 889 << "[120] AV. LOC INV PER M_INV = " << (double) m_cpt_minval_local / m_cpt_minval << std::endl 890 << "[121] AV. REM INV PER M_INV = " << (double) m_cpt_minval_remote / m_cpt_minval << std::endl 777 891 << std::endl 778 << "[122] INVAL BROADCAST RATE = " << (double) m_cpt_b r_inval / m_cpt_cycles << std::endl892 << "[122] INVAL BROADCAST RATE = " << (double) m_cpt_binval / m_cpt_cycles << std::endl 779 893 << "[123] WRITE DIRTY RATE = " << (double) m_cpt_write_dirty / m_cpt_cycles << std::endl 780 894 << std::endl … … 968 1082 m_cpt_update_remote = 0; 969 1083 m_cpt_update_cost = 0; 970 m_cpt_m _inval= 0;971 m_cpt_m _inval_local= 0;972 m_cpt_m _inval_remote= 0;973 m_cpt_m _inval_cost= 0;974 m_cpt_b r_inval= 0;1084 m_cpt_minval = 0; 1085 m_cpt_minval_local = 0; 1086 m_cpt_minval_remote = 0; 1087 m_cpt_minval_cost = 0; 1088 m_cpt_binval = 0; 975 1089 m_cpt_cleanup_local = 0; 976 1090 m_cpt_cleanup_remote = 0; … … 1206 1320 case TGT_CMD_CONFIG: // execute config request and return response 1207 1321 { 1208 addr_t seg_base = m_seg[m_seg_config]->baseAddress(); 1209 addr_t address = p_vci_tgt.address.read(); 1210 size_t cell = (address - seg_base) / vci_param_int::B; 1322 /////////////////////////////////////////////////////////// 1323 // Decoding CONFIG interface commands // 1324 // // 1325 // VCI ADDRESS // 1326 // ================================================ // 1327 // GLOBAL | LOCAL | ... | FUNC_IDX | REGS_IDX | 00 // 1328 // IDX | IDX | | (3 bits) | (7 bits) | // 1329 // ================================================ // 1330 // // 1331 // For instrumentation : FUNC_IDX = 0b001 // 1332 // // 1333 // REGS_IDX // 1334 // ============================================ // 1335 // Z | Y | X | W // 1336 // (1 bit) | (2 bits) | (3 bits) | (1 bit) // 1337 // ============================================ // 1338 // // 1339 // Z : DIRECT / COHERENCE // 1340 // Y : SUBTYPE ( LOCAL, REMOTE, OTHER ) // 1341 // X : REGISTER INDEX // 1342 // W : HI / LO // 1343 // // 1344 // For configuration: FUNC_IDX = 0b000 // 1345 // // 1346 // REGS_IDX // 1347 // ============================================ // 1348 // RESERVED | X | // 1349 // (4 bits) | (3 bits) | // 1350 // ============================================ // 1351 // // 1352 // X : REGISTER INDEX // 1353 // // 1354 /////////////////////////////////////////////////////////// 1355 1356 addr_t addr_lsb = p_vci_tgt.address.read() & 1357 m_config_addr_mask; 1358 1359 addr_t cell = (addr_lsb / vci_param_int::B); 1360 1361 size_t regr = cell & 1362 m_config_regr_idx_mask; 1363 1364 size_t func = (cell >> m_config_regr_width) & 1365 m_config_func_idx_mask; 1211 1366 1212 1367 bool need_rsp; 1213 size_terror;1368 int error; 1214 1369 uint32_t rdata = 0; // default value 1215 1370 uint32_t wdata = p_vci_tgt.wdata.read(); 1216 1371 1217 if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) // get lock 1218 and (cell == MEMC_LOCK)) 1219 { 1220 rdata = (uint32_t) r_config_lock.read(); 1221 need_rsp = true; 1222 error = 0; 1223 r_config_lock = true; 1224 } 1225 else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // release lock 1226 and (cell == MEMC_LOCK)) 1227 { 1228 need_rsp = true; 1229 error = 0; 1230 r_config_lock = false; 1231 } 1232 else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set addr_lo 1233 and (cell == MEMC_ADDR_LO)) 1234 { 1235 assert( ((wdata % (m_words * vci_param_int::B)) == 0) and 1236 "VCI_MEM_CACHE CONFIG ERROR: The buffer must be aligned on a cache line"); 1237 1238 need_rsp = true; 1239 error = 0; 1240 r_config_address = (r_config_address.read() & 0xFFFFFFFF00000000LL) | 1241 ((addr_t)wdata); 1242 } 1243 else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set addr_hi 1244 and (cell == MEMC_ADDR_HI)) 1245 1246 { 1247 need_rsp = true; 1248 error = 0; 1249 r_config_address = (r_config_address.read() & 0x00000000FFFFFFFFLL) | 1250 (((addr_t) wdata) << 32); 1251 } 1252 else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set buf_lines 1253 and (cell == MEMC_BUF_LENGTH)) 1254 { 1255 need_rsp = true; 1256 error = 0; 1257 size_t lines = wdata / (m_words << 2); 1258 if (wdata % (m_words << 2)) lines++; 1259 r_config_cmd_lines = lines; 1260 r_config_rsp_lines = 0; 1261 } 1262 else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set cmd type 1263 and (cell == MEMC_CMD_TYPE)) 1264 { 1265 need_rsp = false; 1266 error = 0; 1267 r_config_cmd = wdata; 1268 1269 // prepare delayed response from CONFIG FSM 1270 r_config_srcid = p_vci_tgt.srcid.read(); 1271 r_config_trdid = p_vci_tgt.trdid.read(); 1272 r_config_pktid = p_vci_tgt.pktid.read(); 1273 } 1274 else 1275 { 1276 need_rsp = true; 1277 error = 1; 1372 switch(func) 1373 { 1374 // memory operation 1375 case MEMC_CONFIG: 1376 { 1377 if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) // get lock 1378 and (regr == MEMC_LOCK)) 1379 { 1380 rdata = (uint32_t) r_config_lock.read(); 1381 need_rsp = true; 1382 error = 0; 1383 r_config_lock = true; 1384 } 1385 else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // release lock 1386 and (regr == MEMC_LOCK)) 1387 { 1388 need_rsp = true; 1389 error = 0; 1390 r_config_lock = false; 1391 } 1392 else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set addr_lo 1393 and (regr == MEMC_ADDR_LO)) 1394 { 1395 assert( ((wdata % (m_words * vci_param_int::B)) == 0) and 1396 "VCI_MEM_CACHE CONFIG ERROR: The buffer must be aligned on a cache line"); 1397 1398 need_rsp = true; 1399 error = 0; 1400 r_config_address = (r_config_address.read() & 0xFFFFFFFF00000000LL) | 1401 ((addr_t)wdata); 1402 } 1403 else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set addr_hi 1404 and (regr == MEMC_ADDR_HI)) 1405 1406 { 1407 need_rsp = true; 1408 error = 0; 1409 r_config_address = (r_config_address.read() & 0x00000000FFFFFFFFLL) | 1410 (((addr_t) wdata) << 32); 1411 } 1412 else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set buf_lines 1413 and (regr == MEMC_BUF_LENGTH)) 1414 { 1415 need_rsp = true; 1416 error = 0; 1417 size_t lines = wdata / (m_words << 2); 1418 if (wdata % (m_words << 2)) lines++; 1419 r_config_cmd_lines = lines; 1420 r_config_rsp_lines = 0; 1421 } 1422 else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set cmd type 1423 and (regr == MEMC_CMD_TYPE)) 1424 { 1425 need_rsp = false; 1426 error = 0; 1427 r_config_cmd = wdata; 1428 1429 // prepare delayed response from CONFIG FSM 1430 r_config_srcid = p_vci_tgt.srcid.read(); 1431 r_config_trdid = p_vci_tgt.trdid.read(); 1432 r_config_pktid = p_vci_tgt.pktid.read(); 1433 } 1434 else 1435 { 1436 need_rsp = true; 1437 error = 1; 1438 } 1439 1440 break; 1441 } 1442 1443 // instrumentation registers 1444 case MEMC_INSTRM: 1445 { 1446 need_rsp = true; 1447 1448 if (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) 1449 { 1450 error = read_instrumentation(regr, rdata); 1451 } 1452 else 1453 { 1454 error = 1; 1455 } 1456 1457 break; 1458 } 1459 1460 //unknown function 1461 default: 1462 { 1463 need_rsp = true; 1464 error = 1; 1465 1466 break; 1467 } 1278 1468 } 1279 1469 … … 1289 1479 r_tgt_cmd_to_tgt_rsp_error = error; 1290 1480 r_tgt_cmd_to_tgt_rsp_rdata = rdata; 1291 r_tgt_cmd_fsm = TGT_CMD_IDLE; 1292 } 1293 else 1294 { 1295 r_tgt_cmd_fsm = TGT_CMD_IDLE; 1296 } 1481 } 1482 1483 r_tgt_cmd_fsm = TGT_CMD_IDLE; 1297 1484 1298 1485 #if DEBUG_MEMC_TGT_CMD … … 1300 1487 std::cout << " <MEMC " << name() << " TGT_CMD_CONFIG> Configuration request:" 1301 1488 << " address = " << std::hex << p_vci_tgt.address.read() 1489 << " / func = " << func 1490 << " / regr = " << regr 1491 << " / rdata = " << rdata 1302 1492 << " / wdata = " << p_vci_tgt.wdata.read() 1303 1493 << " / need_rsp = " << need_rsp … … 1355 1545 if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_read_local++; 1356 1546 else m_cpt_read_remote++; 1357 m_cpt_read_cost += m_words *req_distance(p_vci_tgt.srcid.read());1547 m_cpt_read_cost += req_distance(p_vci_tgt.srcid.read()); 1358 1548 } 1359 1549 // </Activity counters> … … 1677 1867 #if DEBUG_MEMC_CONFIG 1678 1868 if (m_debug) 1679 std::cout << " <MEMC " << name() << " CONFIG_IDLE> Config Request received"1680 << " / address = " << std::hex << r_config_address.read()1681 << " / lines = " << std::dec << r_config_cmd_lines.read()1682 << " / type = " << r_config_cmd.read() << std::endl;1869 std::cout << " <MEMC " << name() << " CONFIG_IDLE> Config Request received" 1870 << " / address = " << std::hex << r_config_address.read() 1871 << " / lines = " << std::dec << r_config_cmd_lines.read() 1872 << " / type = " << r_config_cmd.read() << std::endl; 1683 1873 #endif 1684 1874 } … … 4699 4889 "MEMC ERROR in CLEANUP_IDLE state : illegal SRCID value"); 4700 4890 4701 // <Activity Counters>4702 if (is_local_req(srcid)) {4703 m_cpt_cleanup_local++;4704 }4705 else {4706 m_cpt_cleanup_remote++;4707 m_cpt_cleanup_cost += req_distance(srcid);4708 }4709 // </Activity Counters>4710 4891 cc_receive_to_cleanup_fifo_get = true; 4711 4892 r_cleanup_fsm = CLEANUP_GET_NLINE; … … 6207 6388 if (is_local_req(m_config_to_cc_send_srcid_fifo.read())) 6208 6389 { 6209 m_cpt_m _inval_local++;6390 m_cpt_minval_local++; 6210 6391 } 6211 6392 else 6212 6393 { 6213 m_cpt_m _inval_remote++;6214 m_cpt_m _inval_cost += req_distance(m_config_to_cc_send_srcid_fifo.read());6394 m_cpt_minval_remote++; 6395 m_cpt_minval_cost += req_distance(m_config_to_cc_send_srcid_fifo.read()); 6215 6396 } 6216 6397 // </Activity Counters> … … 6220 6401 if (r_config_to_cc_send_multi_req.read()) r_config_to_cc_send_multi_req = false; 6221 6402 // <Activity Counters> 6222 m_cpt_m _inval++;6403 m_cpt_minval++; 6223 6404 // </Activity Counters> 6224 6405 r_cc_send_fsm = CC_SEND_CONFIG_IDLE; … … 6252 6433 if (not p_dspin_m2p.read) break; 6253 6434 // <Activity Counters> 6254 m_cpt_b r_inval++;6435 m_cpt_binval++; 6255 6436 // </Activity Counters> 6256 6437 r_config_to_cc_send_brdcast_req = false; … … 6274 6455 if (is_local_req(m_xram_rsp_to_cc_send_srcid_fifo.read())) 6275 6456 { 6276 m_cpt_m _inval_local++;6457 m_cpt_minval_local++; 6277 6458 } 6278 6459 else 6279 6460 { 6280 m_cpt_m _inval_remote++;6281 m_cpt_m _inval_cost += req_distance(m_xram_rsp_to_cc_send_srcid_fifo.read());6461 m_cpt_minval_remote++; 6462 m_cpt_minval_cost += req_distance(m_xram_rsp_to_cc_send_srcid_fifo.read()); 6282 6463 } 6283 6464 // </Activity Counters> … … 6287 6468 if (r_xram_rsp_to_cc_send_multi_req.read()) r_xram_rsp_to_cc_send_multi_req = false; 6288 6469 // <Activity Counters> 6289 m_cpt_m _inval++;6470 m_cpt_minval++; 6290 6471 // </Activity Counters> 6291 6472 r_cc_send_fsm = CC_SEND_XRAM_RSP_IDLE; … … 6319 6500 if (not p_dspin_m2p.read) break; 6320 6501 // <Activity Counters> 6321 m_cpt_b r_inval++;6502 m_cpt_binval++; 6322 6503 // </Activity Counters> 6323 6504 r_xram_rsp_to_cc_send_brdcast_req = false; … … 6345 6526 6346 6527 // <Activity Counters> 6347 m_cpt_b r_inval++;6528 m_cpt_binval++; 6348 6529 // </Activity Counters> 6349 6530 … … 6434 6615 if (not p_dspin_m2p.read) break; 6435 6616 // <Activity Counters> 6436 m_cpt_b r_inval++;6617 m_cpt_binval++; 6437 6618 // </Activity Counters> 6438 6619 … … 6576 6757 cc_receive_to_cleanup_fifo_put = true; 6577 6758 r_cc_receive_fsm = CC_RECEIVE_CLEANUP_EOP; 6759 6760 // <Activity Counters> 6761 uint32_t srcid = DspinDhccpParam::dspin_get( 6762 p_dspin_p2m.data.read(), 6763 DspinDhccpParam::CLEANUP_SRCID); 6764 6765 if (is_local_req(srcid)) { 6766 m_cpt_cleanup_local++; 6767 } 6768 else { 6769 m_cpt_cleanup_remote++; 6770 m_cpt_cleanup_cost += req_distance(srcid); 6771 } 6772 // </Activity Counters> 6578 6773 6579 6774 break; … … 8029 8224 8030 8225 case TGT_CMD_CONFIG: 8226 { 8227 addr_t addr_lsb = p_vci_tgt.address.read() & 8228 m_config_addr_mask; 8229 8230 addr_t cell = (addr_lsb / vci_param_int::B); 8231 8232 size_t regr = cell & 8233 m_config_regr_idx_mask; 8234 8235 size_t func = (cell >> m_config_regr_width) & 8236 m_config_func_idx_mask; 8237 8238 switch(func) 8239 { 8240 case MEMC_CONFIG: 8241 if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) 8242 and (regr == MEMC_CMD_TYPE)) 8243 { 8244 p_vci_tgt.cmdack = true; 8245 } 8246 else 8247 { 8248 p_vci_tgt.cmdack = not r_tgt_cmd_to_tgt_rsp_req.read(); 8249 } 8250 break; 8251 8252 default: 8253 p_vci_tgt.cmdack = not r_tgt_cmd_to_tgt_rsp_req.read(); 8254 break; 8255 } 8256 8257 break; 8258 } 8031 8259 case TGT_CMD_ERROR: 8032 8260 p_vci_tgt.cmdack = not r_tgt_cmd_to_tgt_rsp_req.read();
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