Changeset 601 for trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h

Timestamp:

Dec 17, 2013, 11:11:20 AM (10 years ago)

Author:

cfuguet

Message:

Modifications in vci_mem_cache:

• The out of segment read or write does not activate any more an assert on the memory cache. Instead, the request is sent to the XRAM and the error from the XRAM will be propagated to the processor doing the access.

The propagation of the error is done in two different ways:

• When is a READ MISS: The error is propagated through the VCI rerror to the processor doing the read.

• When is a WRITE MISS: The error is propagated through an IRQ which normally is connected to the local XICU.

File:

• trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h (modified) (2 diffs)

trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h

@@ -466 +466 @@
       sc_in<bool>                                 p_clk;
       sc_in<bool>                                 p_resetn;
+      sc_out<bool>                                p_irq;
       soclib::caba::VciTarget<vci_param_int>      p_vci_tgt;
       soclib::caba::VciInitiator<vci_param_ext>   p_vci_ixr;
@@ -904 +905 @@
       sc_signal<size_t>   r_xram_rsp_ivt_index;         // IVT entry index
       sc_signal<size_t>   r_xram_rsp_next_ptr;          // Next pointer to the heap
+      sc_signal<bool>     r_xram_rsp_rerror_irq;        // WRITE MISS rerror irq
+      sc_signal<bool>     r_xram_rsp_rerror_irq_enable; // WRITE MISS rerror irq enable
+      sc_signal<addr_t>   r_xram_rsp_rerror_address;    // WRITE MISS rerror address
+      sc_signal<size_t>   r_xram_rsp_rerror_rsrcid;     // WRITE MISS rerror srcid
 
       // Buffer between XRAM_RSP fsm and TGT_RSP fsm  (response to L1 cache)