Ignore:
Timestamp:
Dec 17, 2013, 3:21:07 PM (9 years ago)
Author:
devigne
Message:

Merge with the latest trunk (concurrent access to a register CONFIG_FSM)
Modification processing software invalidations to memcache level.

When a software memcache invalidation, it does not write the dirty data in the
XRAM (and therefore does not reserve space in the TRT). This poses a problem
when processing CLEANUP_DATA on a line NCC because CLEANUP_FSM expects to find
a placeholder in the TRT.

To overcome this problem, the flit DSPIN a multi-inval now contains a bit to
indicate that the invalidation from a control configuration (software
invalidation level memcache).

At the reception of this message invalidation in the L1 cache, it retrieves the
value of the field DSPIN IS_CONFIG. When processing invalidation (
DCACHE_CC_INVAL ), the value of this field is checked. Two scenarios are
possible:

  • 1st case : The INVAL concerns a line NCC but not from a software invalidation (IS_CONFIG = 0), the CLEANUP sent then follows the classical treatment of invalidation of a line NCC (sends a CLEANUP_NCC with or without data).
  • 2nd case : The INVAL provides a line NCC from a software invalidation (IS_CONFIG = 1) : same treatment as was CLEANUP line CC.

Thus in the case of interest (software invalidation on a line NCC), the CLEANUP
received by the memcache will be treated as one line CC.

Location:
branches/RWT/modules/vci_cc_vcache_wrapper/caba/source
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h

    r577 r604  
    604604
    605605    // communication between CC_RECEIVE FSM and DCACHE FSM
    606     sc_signal<bool>         r_cc_receive_dcache_req;        // cc_receive to dcache request
    607     sc_signal<int>          r_cc_receive_dcache_type;       // cc_receive type of request
    608     sc_signal<size_t>       r_cc_receive_dcache_way;        // cc_receive to dcache way
    609     sc_signal<size_t>       r_cc_receive_dcache_set;        // cc_receive to dcache set
    610     sc_signal<size_t>       r_cc_receive_dcache_updt_tab_idx;  // cc_receive update table index
    611     sc_signal<paddr_t>      r_cc_receive_dcache_nline;      // cache line physical address
     606    sc_signal<bool>         r_cc_receive_dcache_req;              // cc_receive to dcache request
     607    sc_signal<int>          r_cc_receive_dcache_type;             // cc_receive type of request
     608    sc_signal<size_t>       r_cc_receive_dcache_way;              // cc_receive to dcache way
     609    sc_signal<size_t>       r_cc_receive_dcache_set;              // cc_receive to dcache set
     610    sc_signal<size_t>       r_cc_receive_dcache_updt_tab_idx;     // cc_receive update table index
     611    sc_signal<paddr_t>      r_cc_receive_dcache_nline;            // cache line physical address
     612    sc_signal<bool>         r_cc_receive_dcache_inval_is_config;  // inval from memcache is config
    612613
    613614    ///////////////////////////////////
  • branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp

    r577 r604  
    22972297        {
    22982298
     2299
    22992300            if ( r_mmu_mode.read() & DATA_TLB_MASK )  // DTLB activated
    23002301            {
     
    53665367#endif
    53675368                }
    5368 
    5369                 if (cache_state == CACHE_SLOT_STATE_VALID_CC)
     5369                // If the line is coherente we send a classic CLEANUP
     5370                // If the type of inval request from Memcache is configuration
     5371                // (software), we send a classic CLEANUP
     5372                if (cache_state == CACHE_SLOT_STATE_VALID_CC or r_cc_receive_dcache_inval_is_config.read())
    53705373                {
    53715374                    r_dcache.write_dir( way,
     
    53885391                r_dcache_cc_send_type = CC_TYPE_CLEANUP;
    53895392                // MODIFIER POUR DIRTY BIT //
    5390                 if (cache_state == CACHE_SLOT_STATE_VALID_NCC)
     5393                if (cache_state == CACHE_SLOT_STATE_VALID_NCC and not r_cc_receive_dcache_inval_is_config.read())
    53915394                {
    53925395                    r_dcache_cc_cleanup_line_ncc = true;
    53935396                    if ((r_dcache_content_state[way*m_dcache_sets+set] != LINE_CACHE_DATA_NOT_DIRTY) or r_dcache_dirty_save.read() or dirty_save) //must send data
    5394                     //if (true) //must send data
    53955397                    {
    53965398                        r_dcache_cc_cleanup_updt_data = true;
     
    63096311        case CC_RECEIVE_DATA_INVAL_HEADER:
    63106312        {
     6313            // initialize dspin received data
     6314            uint64_t receive_data = p_dspin_m2p.data.read();
    63116315            // sample updt tab index in the HEADER, then skip to second flit
    63126316            r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_NLINE;
     6317            r_cc_receive_dcache_inval_is_config = DspinDhccpParam::dspin_get(receive_data,
     6318                                                  DspinDhccpParam::MULTI_INVAL_IS_CONFIG);
    63136319            break;
    63146320        }
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