Ignore:
Timestamp:
Dec 17, 2013, 3:21:07 PM (9 years ago)
Author:
devigne
Message:

Merge with the latest trunk (concurrent access to a register CONFIG_FSM)
Modification processing software invalidations to memcache level.

When a software memcache invalidation, it does not write the dirty data in the
XRAM (and therefore does not reserve space in the TRT). This poses a problem
when processing CLEANUP_DATA on a line NCC because CLEANUP_FSM expects to find
a placeholder in the TRT.

To overcome this problem, the flit DSPIN a multi-inval now contains a bit to
indicate that the invalidation from a control configuration (software
invalidation level memcache).

At the reception of this message invalidation in the L1 cache, it retrieves the
value of the field DSPIN IS_CONFIG. When processing invalidation (
DCACHE_CC_INVAL ), the value of this field is checked. Two scenarios are
possible:

  • 1st case : The INVAL concerns a line NCC but not from a software invalidation (IS_CONFIG = 0), the CLEANUP sent then follows the classical treatment of invalidation of a line NCC (sends a CLEANUP_NCC with or without data).
  • 2nd case : The INVAL provides a line NCC from a software invalidation (IS_CONFIG = 1) : same treatment as was CLEANUP line CC.

Thus in the case of interest (software invalidation on a line NCC), the CLEANUP
received by the memcache will be treated as one line CC.

File:
1 edited

Legend:

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  • branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h

    r577 r604  
    604604
    605605    // communication between CC_RECEIVE FSM and DCACHE FSM
    606     sc_signal<bool>         r_cc_receive_dcache_req;        // cc_receive to dcache request
    607     sc_signal<int>          r_cc_receive_dcache_type;       // cc_receive type of request
    608     sc_signal<size_t>       r_cc_receive_dcache_way;        // cc_receive to dcache way
    609     sc_signal<size_t>       r_cc_receive_dcache_set;        // cc_receive to dcache set
    610     sc_signal<size_t>       r_cc_receive_dcache_updt_tab_idx;  // cc_receive update table index
    611     sc_signal<paddr_t>      r_cc_receive_dcache_nline;      // cache line physical address
     606    sc_signal<bool>         r_cc_receive_dcache_req;              // cc_receive to dcache request
     607    sc_signal<int>          r_cc_receive_dcache_type;             // cc_receive type of request
     608    sc_signal<size_t>       r_cc_receive_dcache_way;              // cc_receive to dcache way
     609    sc_signal<size_t>       r_cc_receive_dcache_set;              // cc_receive to dcache set
     610    sc_signal<size_t>       r_cc_receive_dcache_updt_tab_idx;     // cc_receive update table index
     611    sc_signal<paddr_t>      r_cc_receive_dcache_nline;            // cache line physical address
     612    sc_signal<bool>         r_cc_receive_dcache_inval_is_config;  // inval from memcache is config
    612613
    613614    ///////////////////////////////////
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