Index: branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
===================================================================
--- branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h	(revision 545)
+++ branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h	(revision 604)
@@ -633,5 +633,5 @@
 
       void print_stats(bool activity_counters, bool stats);
-      void print_trace();
+      void print_trace( size_t detailled = 0 );
       void cache_monitor(addr_t addr);
       void start_monitor(addr_t addr, addr_t length);
Index: branches/RWT/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
===================================================================
--- branches/RWT/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp	(revision 545)
+++ branches/RWT/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp	(revision 604)
@@ -134,5 +134,5 @@
         "CONFIG_IDLE",
         "CONFIG_LOOP",
-        "CONFIG_WAIT"
+        "CONFIG_WAIT",
         "CONFIG_RSP",
         "CONFIG_DIR_REQ",
@@ -140,5 +140,5 @@
         "CONFIG_IVT_LOCK",
         "CONFIG_BC_SEND",
-        "CONFIG_INVAL_SEND"
+        "CONFIG_INVAL_SEND",
         "CONFIG_HEAP_REQ",
         "CONFIG_HEAP_SCAN",
@@ -412,6 +412,4 @@
         m_broadcast_boundaries(0x7C1F),
 
-        r_tgt_cmd_fsm("r_tgt_cmd_fsm"),
-
         //  FIFOs
         m_cmd_read_addr_fifo("m_cmd_read_addr_fifo", 4),
@@ -438,4 +436,6 @@
         m_cc_receive_to_cleanup_fifo("m_cc_receive_to_cleanup_fifo", 4),
         m_cc_receive_to_multi_ack_fifo("m_cc_receive_to_multi_ack_fifo", 4),
+
+        r_tgt_cmd_fsm("r_tgt_cmd_fsm"),
 
         r_config_fsm( "r_config_fsm" ),
@@ -574,5 +574,5 @@
             r_ixr_cmd_wdata            = new sc_signal<data_t>[nwords];
 
-            // Allocation for ODCCP
+            // Allocation for RWT
             r_cleanup_data             = new sc_signal<data_t>[nwords];
             r_cleanup_to_ixr_cmd_data  = new sc_signal<data_t>[nwords];
@@ -679,6 +679,6 @@
 
     //////////////////////////////////////////////////
-    tmpl(void) ::print_trace()
-        //////////////////////////////////////////////////
+    tmpl(void)::print_trace( size_t detailed )
+    //////////////////////////////////////////////////
     {
         std::cout << "MEMC " << name() << std::endl;
@@ -701,4 +701,6 @@
             << " | " << alloc_ivt_fsm_str[r_alloc_ivt_fsm.read()]
             << " | " << alloc_heap_fsm_str[r_alloc_heap_fsm.read()] << std::endl;
+
+        if ( detailed ) m_trt.print(0);
     }
 
@@ -764,4 +766,9 @@
                 << "[037] GET (UNIMPLEMENTED)       = " << m_cpt_get << std::endl
                 << "[038] WRITE BROADCAST           = " << m_cpt_write_broadcast << std::endl
+                << std::endl
+                << "[039] CLEANUP DATA (FLITS)      = " << m_cpt_cleanup_data * 16 << std::endl
+                << "[040] NCC TO CC (READ)          = " << m_cpt_ncc_to_cc_read << std::endl
+                << "[041] NCC TO CC (WRITE)         = " << m_cpt_ncc_to_cc_write << std::endl
+                << "[042] NCC TO CC (TOTAL)         = " << m_cpt_ncc_to_cc << std::endl
                 << std::endl;
         }
@@ -976,5 +983,5 @@
             r_tgt_rsp_key_sent  = false;
 
-            // ODCCP
+            // RWT
             r_cleanup_data_index       = 0;
             r_cleanup_trdid            = 0;
@@ -1110,4 +1117,8 @@
         size_t  xram_rsp_to_cc_send_fifo_srcid = 0;
 
+        bool   config_rsp_lines_incr          = false;
+        bool   config_rsp_lines_cleanup_decr  = false;
+        bool   config_rsp_lines_ixr_rsp_decr  = false;
+
         bool    config_to_cc_send_fifo_put   = false;
         bool    config_to_cc_send_fifo_get   = false;
@@ -1348,5 +1359,5 @@
                         if (wdata % (m_words << 2)) lines++;
                         r_config_cmd_lines  = lines;
-                        r_config_rsp_lines  = lines;
+                        r_config_rsp_lines  = 0;
                     }
                     else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set cmd type
@@ -1614,5 +1625,4 @@
                     bool valid   = m_upt.decrement(r_multi_ack_upt_index.read(), count);
 
-                    /*ODCCP*/ //m_upt.print();
 
                     if(not valid)
@@ -1718,4 +1728,10 @@
         // the command for line (n+1). It decrements the r_config_cmd_lines counter until 
         // the last request has been registered in TRT (for a SYNC), or in IVT (for an INVAL).
+        // The r_config_rsp_lines counter contains the number of expected responses from
+        // CLEANUP FSM (inval) or from IXR_RSP FSM (sync). This register is incremented by
+        // the CONFIG FSM (each time a transaction is requested), and decremented by the
+        // CLEANUP or IXR_RSP FSMs(each time a response is received. As this register can
+        // be concurently accessed by those three FSMs, it is implemented as an [incr/decr]
+        // counter.
         // 
         // - INVAL request:
@@ -1879,5 +1895,4 @@
                     {
                         r_config_cmd_lines = r_config_cmd_lines.read() - 1;
-                        r_config_rsp_lines = r_config_rsp_lines.read() - 1;
                         r_config_address   = r_config_address.read() + (m_words<<2);
                         r_config_fsm       = CONFIG_LOOP;
@@ -1981,4 +1996,5 @@
                             0,                                   // ll_key:          unused
                             true );                              // requested by config FSM
+                    config_rsp_lines_incr = true;
                     r_config_fsm = CONFIG_PUT_REQ;
 
@@ -2031,5 +2047,4 @@
                             m_cache_directory.inval( way, set );
                             r_config_cmd_lines  = r_config_cmd_lines.read() - 1;
-                            r_config_rsp_lines  = r_config_rsp_lines.read() - 1;
                             r_config_address    = r_config_address.read() + (m_words<<2);
                             r_config_fsm        = CONFIG_LOOP;
@@ -2067,4 +2082,5 @@
                                 m_cache_directory.inval( way, set );
                                 r_config_ivt_index = index;
+                                config_rsp_lines_incr = true;
                                 if ( broadcast )  r_config_fsm = CONFIG_BC_SEND;
                                 else              r_config_fsm = CONFIG_INVAL_SEND;
@@ -3885,5 +3901,4 @@
                                 nb_copies,
                                 index);
-                        /*ODCCP*/ //m_upt.print();
 #if DEBUG_MEMC_WRITE
                         if( m_debug and wok )
@@ -4071,5 +4086,4 @@
                 ////////////////////////
             case IXR_CMD_CLEANUP_IDLE:
-                /*ODCCP*///std::cout << "IXR_CMD_CLEANUP_IDLE" << std::endl;
                 if     (r_read_to_ixr_cmd_req.read())       r_ixr_cmd_fsm = IXR_CMD_READ_TRT;
                 else if(r_write_to_ixr_cmd_req.read())      r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;
@@ -4352,8 +4366,6 @@
                     if(p_vci_ixr.cmdack.read())
                     {
-                        /*ODCCP*/ //std::cout << "IXR_CMD_CLEANUP_DATA_SEND STATE at cycle : " << std::dec << m_cpt_cycles << std::endl;
                         if(r_ixr_cmd_word.read() == (m_words - 2))
                         {
-                            /*ODCCP*/ //std::cout << "IXR_CMD_CLEANUP_DATA_SEND GO TO IXR_CMD_CLEANUP_IDLE" << std::endl;
                             r_ixr_cmd_fsm = IXR_CMD_CLEANUP_IDLE;
                             r_cleanup_to_ixr_cmd_req = false;
@@ -4467,9 +4479,16 @@
                     {
                         size_t  index = r_ixr_rsp_trt_index.read(); 
-                        if (m_trt.is_config(index) ) r_config_rsp_lines = r_config_rsp_lines.read() - 1;
-                        m_trt.erase(index);
-                        r_ixr_rsp_fsm = IXR_RSP_IDLE;
-
-                        //            std::cout << "remove a valid slot in trt index = " << r_ixr_rsp_trt_index.read()<< std::endl;
+                        if (m_trt.is_config(index))     // it's a config transaction
+                        {
+                            config_rsp_lines_ixr_rsp_decr = true;
+                            m_trt.erase(index);
+                            r_ixr_rsp_fsm = IXR_RSP_IDLE;
+                        }
+                        else                            // not a config transaction
+                        {
+                            m_trt.erase(index);
+                            r_ixr_rsp_fsm = IXR_RSP_IDLE;
+                        }
+
 #if DEBUG_MEMC_IXR_RSP
                         if(m_debug)
@@ -5355,5 +5374,4 @@
             case CLEANUP_DIR_WRITE:
                 {
-                    /*ODCCP*///std::cout << "CLEANUP_DIR_WRITE" << std::endl;
                     // Update the directory entry without heap access
                     if(r_alloc_dir_fsm.read() != ALLOC_DIR_CLEANUP)
@@ -5919,9 +5937,9 @@
                                 "MEMC ERROR in CLEANUP_IVT_CLEAR state");
 
-                        r_config_rsp_lines = r_config_rsp_lines.read() - 1;
+                        config_rsp_lines_cleanup_decr = true;
                     }
 
                     if      ( r_cleanup_need_rsp.read() ) r_cleanup_fsm = CLEANUP_WRITE_RSP;
-                    else if ( r_cleanup_ncc.read()      ) r_cleanup_fsm = CLEANUP_IXR_REQ;
+                    else if ( r_cleanup_ncc.read() ) r_cleanup_fsm = CLEANUP_IXR_REQ;
                     else                                  r_cleanup_fsm = CLEANUP_SEND_CLACK;
 
@@ -5947,5 +5965,5 @@
                     r_cleanup_to_tgt_rsp_type    = true; 
 
-                    if (r_cleanup_ncc.read())
+                    if (r_cleanup_ncc.read() )
                     {
                         r_cleanup_fsm = CLEANUP_IXR_REQ;//need to put data to the XRAM
@@ -8945,5 +8963,4 @@
                 ////////////////////////
             case ALLOC_TRT_CLEANUP:
-                /*ODCCP*///std::cout << "TRT ALLOCATED TO CLEANUP" << std::endl;
                 if(r_cleanup_fsm.read() != CLEANUP_IXR_REQ)
                 {
@@ -9294,4 +9311,19 @@
                 cas_to_cc_send_fifo_srcid );
         m_cpt_cycles++;
+
+        ////////////////////////////////////////////////////////////////////////////////////
+        //            Update r_config_rsp_lines counter.
+        // The three sources of (increment / decrement) are CONFIG / CLEANUP / IXR_RSP FSMs
+        ////////////////////////////////////////////////////////////////////////////////////
+        if ( config_rsp_lines_incr and not 
+             (config_rsp_lines_cleanup_decr or config_rsp_lines_ixr_rsp_decr) )
+        {
+            r_config_rsp_lines = r_config_rsp_lines.read() + 1;
+        }
+        if ( not config_rsp_lines_incr and  
+             (config_rsp_lines_cleanup_decr or config_rsp_lines_ixr_rsp_decr) )
+        {
+            r_config_rsp_lines = r_config_rsp_lines.read() - 1;
+        }
 
     } // end transition()
@@ -9645,4 +9677,9 @@
                             DspinDhccpParam::MULTI_INVAL_SRCID);
 
+                    // MODIFIED FOR CONFIG INVAL (solution 1 bit in flit multi_inval)
+                    DspinDhccpParam::dspin_set( flit,
+                            1,
+                            DspinDhccpParam::MULTI_INVAL_IS_CONFIG);
+
                     DspinDhccpParam::dspin_set( flit,
                             r_config_to_cc_send_trdid.read(),
@@ -9723,4 +9760,27 @@
                 /////////////////////////////////////
             case CC_SEND_CONFIG_BRDCAST_HEADER:
+                {
+                    uint64_t flit = 0;
+
+                    DspinDhccpParam::dspin_set( flit,
+                            m_broadcast_boundaries,
+                            DspinDhccpParam::BROADCAST_BOX);
+                    // MODIFIED FOR CONFIG INVAL (solution 1 bit in flit multi_inval)
+                    DspinDhccpParam::dspin_set( flit,
+                            1,
+                            DspinDhccpParam::MULTI_INVAL_IS_CONFIG);
+
+                    DspinDhccpParam::dspin_set( flit,
+                            m_cc_global_id,
+                            DspinDhccpParam::BROADCAST_SRCID);
+
+                    DspinDhccpParam::dspin_set( flit,
+                            1ULL,
+                            DspinDhccpParam::M2P_BC);
+                    p_dspin_m2p.write = true;
+                    p_dspin_m2p.data  = flit;
+                    break;
+                }
+                /////////////////////////////////////
             case CC_SEND_XRAM_RSP_BRDCAST_HEADER:
             case CC_SEND_WRITE_BRDCAST_HEADER:
