Changeset 616 for trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h

Timestamp:

Jan 7, 2014, 4:26:39 PM (10 years ago)

Author:

haoliu

Message:

Modification in vci_cc_vcache_wrapper:
a) Non cacheable write request will not any more be sent by multi_write_buffer.

A write non cacheable access is retreated with a synchronous way, like the
read non cacheable access. When Cache L1 receives a write non cacheable request,
it will block the processor until the response of this request arrives.
The advantage of this method is that the cache L1 can supply the virtual address
to OS when it receives a bus error response.

b) In VCI_CMD_STATE, the unc_read request will not check the multi_write_buffer for

an matching address. But the CAS and SC request must be check this point
before sent to the target.

File:

• trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (modified) (6 diffs)

trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h

@@ -148 +148 @@
         CMD_INS_UNC,
         CMD_DATA_MISS,
-        CMD_DATA_UNC,
+        CMD_DATA_UNC_READ,
+        CMD_DATA_UNC_WRITE,
         CMD_DATA_WRITE,
         CMD_DATA_LL,
@@ -202 +203 @@
         //  b1 accÚs table llsc type SW / other
         //  b2 WRITE/CAS/LL/SC
-        TYPE_READ_DATA_UNC          = 0x0,
+        TYPE_DATA_UNC               = 0x0,
         TYPE_READ_DATA_MISS         = 0x1,
         TYPE_READ_INS_UNC           = 0x2,
@@ -274 +275 @@
     };
 
-    enum transaction_type_d_e
-    {
-        // b0 : 1 if cached
-        // b1 : 1 if instruction
-        TYPE_DATA_UNC     = 0x0,
-        TYPE_DATA_MISS    = 0x1,
-        TYPE_INS_UNC      = 0x2,
-        TYPE_INS_MISS     = 0x3,
-    };
+//    enum transaction_type_d_e
+//    {
+//        // b0 : 1 if cached
+//        // b1 : 1 if instruction
+//        TYPE_DATA_UNC     = 0x0,
+//        TYPE_DATA_MISS    = 0x1,
+//        TYPE_INS_UNC      = 0x2,
+//        TYPE_INS_MISS     = 0x3,
+//    };
 
 public:
@@ -412 +413 @@
     sc_signal<uint32_t>     r_dcache_save_be;           // byte enable (from proc)
     sc_signal<paddr_t>      r_dcache_save_paddr;        // physical address
-    sc_signal<bool>         r_dcache_save_cacheable;    // address cacheable
     sc_signal<size_t>       r_dcache_save_cache_way;    // selected way (from dcache)
     sc_signal<size_t>       r_dcache_save_cache_set;    // selected set (from dcache)
@@ -423 +423 @@
     // communication between DCACHE FSM and VCI_CMD FSM
     sc_signal<paddr_t>      r_dcache_vci_paddr;             // physical address for VCI command
+    sc_signal<uint32_t>     r_dcache_vci_wdata;             // write unc data for VCI command
     sc_signal<bool>         r_dcache_vci_miss_req;      // read miss request
-    sc_signal<bool>         r_dcache_vci_unc_req;       // uncacheable read request
-    sc_signal<uint32_t>     r_dcache_vci_unc_be;        // uncacheable read byte enable
+    sc_signal<bool>         r_dcache_vci_unc_req;       // uncacheable request (read/write)
+    sc_signal<uint32_t>     r_dcache_vci_unc_be;        // uncacheable byte enable
+    sc_signal<uint32_t>     r_dcache_vci_unc_write;     // uncacheable data write request
     sc_signal<bool>         r_dcache_vci_cas_req;       // atomic write request CAS
     sc_signal<uint32_t>     r_dcache_vci_cas_old;       // previous data value for a CAS
@@ -436 +438 @@
     sc_signal<size_t>       r_dcache_xtn_way;               // selected way (from dcache)
     sc_signal<size_t>       r_dcache_xtn_set;               // selected set (from dcache)
-
-    // write buffer state extension
-    sc_signal<bool>         r_dcache_pending_unc_write; // pending uncacheable write in WBUF
 
     // handling dcache miss