- Timestamp:
- Mar 2, 2014, 10:14:35 PM (10 years ago)
- Location:
- branches/fault_tolerance/platform/tsar_generic_iob
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top.cpp (modified) (48 diffs)
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branches/fault_tolerance/platform/tsar_generic_iob/top.cpp
r618 r648 1 1 /////////////////////////////////////////////////////////////////////////////// 2 // File: top.cpp 3 // Author: Alain Greiner 2 // File: top.cpp 3 // Author: Alain Greiner 4 4 // Copyright: UPMC/LIP6 5 5 // Date : august 2013 6 6 // This program is released under the GNU public license 7 // 8 // Modified by: Cesar Fuguet 9 // Modified on: mars 2014 7 10 /////////////////////////////////////////////////////////////////////////////// 8 // This file define a generic TSAR architecture with an IO network emulating 11 // This file define a generic TSAR architecture with an IO network emulating 9 12 // an external bus (i.e. Hypertransport) to access external peripherals: 10 13 // … … 15 18 // - CDMA : Chained Buffer DMA controller (up to 4 channels) 16 19 // - BDEV : Dlock Device controler (1 channel) 17 // 20 // 18 21 // The internal physical address space is 40 bits. 19 22 // … … 24 27 // 25 28 // 1) the INT network supports Read/Write transactions 26 // between processors and L2 caches or peripherals. 29 // between processors and L2 caches or peripherals. 27 30 // (VCI ADDDRESS = 40 bits / VCI DATA width = 32 bits) 28 31 // It supports also coherence transactions between L1 & L2 caches. … … 34 37 // 6 external peripheral controllers. 35 38 // (VCI ADDDRESS = 40 bits / VCI DATA width = 64 bits) 36 // 39 // 37 40 // The external peripherals IRQs are connected to the XICU component 38 // in cluster(0,0): therefore, the number of channels for the external 41 // in cluster(0,0): therefore, the number of channels for the external 39 42 // peripherals (MTTY, MNIC, CDMA) is limited by the number of IRQ ports... 40 43 // … … 47 50 // - IRQ_IN[31] is connected to BDEV 48 51 // In other clusters, the XICU HWI input ports are grounded. 49 // 52 // 50 53 // All clusters are identical, but cluster(0,0) and cluster(XMAX-1,YMAX-1) 51 54 // contain an extra IO bridge component. These IOB0 & IOB1 components are … … 53 56 // The number of clusters cannot be larger than 256. 54 57 // The number of processors per cluster cannot be larger than 4. 55 // 58 // 56 59 // - It uses two dspin_local_crossbar per cluster to implement the 57 // local interconnect correponding to the INT network. 60 // local interconnect correponding to the INT network. 58 61 // - It uses two dspin_local_crossbar per cluster to implement the 59 // local interconnect correponding to the coherence INT network. 62 // local interconnect correponding to the coherence INT network. 60 63 // - It uses two virtual_dspin_router per cluster to implement 61 64 // the INT network (routing both the direct and coherence trafic). … … 77 80 // - NB_TTY_CHANNELS : number of TTY channels in I/O network (< 16) 78 81 // - NB_NIC_CHANNELS : number of NIC channels in I/O network (< 9) 79 // 82 // 80 83 // Some secondary hardware parameters must be defined in this top.cpp file: 81 // - XRAM_LATENCY : external ram latency 84 // - XRAM_LATENCY : external ram latency 82 85 // - MEMC_WAYS : L2 cache number of ways 83 86 // - MEMC_SETS : L2 cache number of sets 84 // - L1_IWAYS 85 // - L1_ISETS 86 // - L1_DWAYS 87 // - L1_DSETS 87 // - L1_IWAYS 88 // - L1_ISETS 89 // - L1_DWAYS 90 // - L1_DSETS 88 91 // - FBUF_X_SIZE : width of frame buffer (pixels) 89 92 // - FBUF_Y_SIZE : heigth of frame buffer (lines) 90 93 // - BDEV_SECTOR_SIZE : block size for block drvice 91 // - BDEV_IMAGE_NAME : file pathname for block device 94 // - BDEV_IMAGE_NAME : file pathname for block device 92 95 // - NIC_RX_NAME : file pathname for NIC received packets 93 96 // - NIC_TX_NAME : file pathname for NIC transmited packets … … 96 99 // General policy for 40 bits physical address decoding: 97 100 // All physical segments base addresses are multiple of 1 Mbytes 98 // (=> the 24 LSB bits = 0, and the 16 MSB bits define the target) 101 // (=> the 24 LSB bits = 0, and the 16 MSB bits define the target) 99 102 // The (x_width + y_width) MSB bits (left aligned) define 100 103 // the cluster index, and the LADR bits define the local index: … … 142 145 // Parallelisation 143 146 /////////////////////////////////////////////////// 144 #define USE_OPENMP 147 #define USE_OPENMP 0 145 148 146 149 #if USE_OPENMP … … 149 152 150 153 /////////////////////////////////////////////////////////// 151 // DSPIN parameters 154 // DSPIN parameters 152 155 /////////////////////////////////////////////////////////// 153 156 … … 159 162 160 163 /////////////////////////////////////////////////////////// 161 // VCI fields width for the 3 VCI networks 164 // VCI fields width for the 3 VCI networks 162 165 /////////////////////////////////////////////////////////// 163 166 164 #define vci_cell_width_int 165 #define vci_cell_width_ext 166 167 #define vci_plen_width 168 #define vci_address_width 169 #define vci_rerror_width 170 #define vci_clen_width 171 #define vci_rflag_width 172 #define vci_srcid_width 173 #define vci_pktid_width 174 #define vci_trdid_width 175 #define vci_wrplen_width 167 #define vci_cell_width_int 4 168 #define vci_cell_width_ext 8 169 170 #define vci_plen_width 8 171 #define vci_address_width 40 172 #define vci_rerror_width 1 173 #define vci_clen_width 1 174 #define vci_rflag_width 1 175 #define vci_srcid_width 14 176 #define vci_pktid_width 4 177 #define vci_trdid_width 4 178 #define vci_wrplen_width 1 176 179 177 180 //////////////////////////////////////////////////////////// 178 // Main Hardware Parameters values 181 // Main Hardware Parameters values 179 182 //////////////////////i///////////////////////////////////// 180 183 181 #include "giet_vm/hard_config.h" 184 #define X_WIDTH 4 185 #define Y_WIDTH 4 186 #define X_MAX (1<<X_WIDTH) 187 #define Y_MAX (1<<Y_WIDTH) 182 188 183 189 //////////////////////////////////////////////////////////// 184 // Secondary Hardware Parameters values 190 // Secondary Hardware Parameters values 185 191 //////////////////////i///////////////////////////////////// 186 192 187 #define XMAX X_SIZE 188 #define YMAX Y_SIZE 189 190 #define XRAM_LATENCY 0 191 192 #define MEMC_WAYS 16 193 #define MEMC_SETS 256 194 195 #define L1_IWAYS 4 196 #define L1_ISETS 64 197 198 #define L1_DWAYS 4 199 #define L1_DSETS 64 200 201 #define FBUF_X_SIZE 128 202 #define FBUF_Y_SIZE 128 203 204 #define BDEV_SECTOR_SIZE 512 205 #define BDEV_IMAGE_NAME "../../../giet_vm/hdd/virt_hdd.dmg" 206 207 #define NIC_RX_NAME "giet_vm/nic/rx_packets.txt" 208 #define NIC_TX_NAME "giet_vm/nic/tx_packets.txt" 209 #define NIC_TIMEOUT 10000 210 211 #define NORTH 0 212 #define SOUTH 1 213 #define EAST 2 214 #define WEST 3 215 216 #define cluster(x,y) ((y) + (x<<4)) 193 #define XRAM_LATENCY 0 194 195 #define MEMC_WAYS 16 196 #define MEMC_SETS 256 197 198 #define L1_IWAYS 4 199 #define L1_ISETS 64 200 201 #define L1_DWAYS 4 202 #define L1_DSETS 64 203 204 #define FBUF_X_SIZE 128 205 #define FBUF_Y_SIZE 128 206 207 #define BDEV_SECTOR_SIZE 512 208 #define BDEV_IMAGE_NAME "../../../giet_vm/hdd/virt_hdd.dmg" 209 210 #define NIC_RX_NAME "giet_vm/nic/rx_packets.txt" 211 #define NIC_TX_NAME "giet_vm/nic/tx_packets.txt" 212 #define NIC_TIMEOUT 10000 213 214 #define cluster(x,y) ((y) + ((x)<<4)) 217 215 218 216 //////////////////////////////////////////////////////////// 219 // Software to be loaded in ROM & RAM 217 // Software to be loaded in ROM & RAM 220 218 //////////////////////i///////////////////////////////////// 221 219 222 #define BOOT_SOFT_NAME 220 #define BOOT_SOFT_NAME "../../softs/tsar_boot/preloader.elf" 223 221 224 222 //////////////////////////////////////////////////////////// 225 // DEBUG Parameters default values 223 // DEBUG Parameters default values 226 224 //////////////////////i///////////////////////////////////// 227 225 228 #define MAX_FROZEN_CYCLES 226 #define MAX_FROZEN_CYCLES 10000 229 227 230 228 ///////////////////////////////////////////////////////// … … 234 232 // Non replicated peripherals (must be in cluster 0) 235 233 236 #define BROM_BASE 0x00BFC00000237 #define BROM_SIZE 0x0000100000// 1 M Kbytes238 239 #define IOBX_BASE 240 #define IOBX_SIZE 0x0000001000// 4 K Kbytes241 242 #define BDEV_BASE 0x00B3000000243 #define BDEV_SIZE 0x0000008000// 4 Kbytes244 245 #define MTTY_BASE 0x00B4000000246 #define MTTY_SIZE 0x0000001000 * NB_TTY_CHANNELS// 4 Kbytes247 248 #define MNIC_BASE 0x00B5000000249 #define MNIC_SIZE 0x0000080000// 512 Kbytes250 251 #define CDMA_BASE 0x00B6000000252 #define CDMA_SIZE 0x0000001000 * (NB_NIC_CHANNELS * 2) // 4 Kbytes per channel253 254 #define FBUF_BASE 0x00B7000000255 #define FBUF_SIZE FBUF_X_SIZE * FBUF_Y_SIZE256 257 // Replicated peripherals : address is incremented by a cluster offset 258 // 259 260 #define XRAM_BASE 0x0000000000261 #define XRAM_SIZE 0x0010000000// 256 Mbytes262 263 #define XICU_BASE 0x00B0000000264 #define XICU_SIZE 0x0000001000// 4 Kbytes265 266 #define MDMA_BASE 0x00B1000000267 #define MDMA_SIZE 0x0000001000 * NB_DMA_CHANNELS // 4 Kbytes per channel268 269 // Replicated mem ory segments (XRAM) : address is incremented by a cluster offset270 // offset= cluster(x,y) << (address_width-x_width-y_width);271 272 #define MEMC_BASE 0x00B2000000273 #define MEMC_SIZE 0x0000001000 // 4 Kbytes234 #define BROM_BASE 0x00BFC00000 235 #define BROM_SIZE 0x0000100000 // 1 M Kbytes 236 237 #define IOBX_BASE 0x00BE000000 238 #define IOBX_SIZE 0x0000001000 // 4 K Kbytes 239 240 #define BDEV_BASE 0x00B3000000 241 #define BDEV_SIZE 0x0000008000 // 4 Kbytes 242 243 #define MTTY_BASE 0x00B4000000 244 #define MTTY_SIZE (0x0000001000 * 16) // 4 Kbytes 245 246 #define MNIC_BASE 0x00B5000000 247 #define MNIC_SIZE 0x0000080000 // 512 Kbytes 248 249 #define CDMA_BASE 0x00B6000000 250 #define CDMA_SIZE (0x0000001000 * 2) // 4 Kbytes per channel 251 252 #define FBUF_BASE 0x00B7000000 253 #define FBUF_SIZE (800 * 600 * 2) 254 255 // Replicated peripherals : address is incremented by a cluster offset 256 // offset = cluster(x,y) << (address_width-x_width-y_width); 257 258 #define XRAM_BASE 0x0000000000 259 #define XRAM_SIZE 0x0010000000 // 256 Mbytes 260 261 #define XICU_BASE 0x00B0000000 262 #define XICU_SIZE 0x0000001000 // 4 Kbytes 263 264 #define MDMA_BASE 0x00B1000000 265 #define MDMA_SIZE 0x0000001000 * 4 // 4 Kbytes per channel 266 267 // Replicated mem segments (XRAM) : address is incremented by a cluster offset 268 // offset = cluster(x,y) << (address_width-x_width-y_width); 269 270 #define MEMC_BASE 0x00B2000000 271 #define MEMC_SIZE 0x0000001000 // 4 Kbytes 274 272 275 273 //////////////////////////////////////////////////////////////////////// … … 280 278 // - The 10 MSB bits define the cluster index (left aligned) 281 279 // - The 4 LSB bits define the local index. 282 // Two different initiators cannot have the same SRCID, but a given 283 // initiator can have two alias SRCIDs: 280 // Two different initiators cannot have the same SRCID, but a given 281 // initiator can have two alias SRCIDs: 284 282 // - Internal initiators (procs, mdma) are replicated in all clusters, 285 283 // and each initiator has one single SRCID. 286 284 // - External initiators (bdev, cdma) are not replicated, but can be 287 // accessed in 2 clusters : cluster_iob0 and cluster_iob1. 285 // accessed in 2 clusters : cluster_iob0 and cluster_iob1. 288 286 // They have the same local index, but two different cluster indexes. 289 287 // As cluster_iob0 and cluster_iob1 contain both internal initiators 290 // and external initiators, they must have different local indexes. 288 // and external initiators, they must have different local indexes. 291 289 // Consequence: For a local interconnect, the INI_ID port index 292 290 // is NOT equal to the SRCID local index, and the local interconnect … … 294 292 //////////////////////////////////////////////////////////////////////// 295 293 296 #define PROC_LOCAL_SRCID 0x0// from 0 to 7297 #define MDMA_LOCAL_SRCID 298 #define IOBX_LOCAL_SRCID 299 #define MEMC_LOCAL_SRCID 300 #define CDMA_LOCAL_SRCID 0xE// hard-coded in dspin_tsar301 #define BDEV_LOCAL_SRCID 0xF// hard-coded in dspin_tsar294 #define PROC_LOCAL_SRCID 0x0 // from 0 to 7 295 #define MDMA_LOCAL_SRCID 0x8 296 #define IOBX_LOCAL_SRCID 0x9 297 #define MEMC_LOCAL_SRCID 0xA 298 #define CDMA_LOCAL_SRCID 0xE // hard-coded in dspin_tsar 299 #define BDEV_LOCAL_SRCID 0xF // hard-coded in dspin_tsar 302 300 303 301 /////////////////////////////////////////////////////////////////////// … … 305 303 /////////////////////////////////////////////////////////////////////// 306 304 307 #define INT_MEMC_TGT_ID 308 #define INT_XICU_TGT_ID 309 #define INT_MDMA_TGT_ID 310 #define INT_IOBX_TGT_ID 311 312 #define INT_PROC_INI_ID 0 // from 0 to (NB_PROCS_MAX-1)313 #define INT_MDMA_INI_ID NB_PROCS_MAX314 #define INT_IOBX_INI_ID (NB_PROCS_MAX+1)305 #define INT_MEMC_TGT_ID 0 306 #define INT_XICU_TGT_ID 1 307 #define INT_MDMA_TGT_ID 2 308 #define INT_IOBX_TGT_ID 3 309 310 #define INT_PROC_INI_ID 0 // from 0 to 7 311 #define INT_MDMA_INI_ID nb_procs 312 #define INT_IOBX_INI_ID (nb_procs + 1) 315 313 316 314 /////////////////////////////////////////////////////////////////////// … … 318 316 /////////////////////////////////////////////////////////////////////// 319 317 320 #define RAM_XRAM_TGT_ID 321 322 #define RAM_MEMC_INI_ID 323 #define RAM_IOBX_INI_ID 318 #define RAM_XRAM_TGT_ID 0 319 320 #define RAM_MEMC_INI_ID 0 321 #define RAM_IOBX_INI_ID 1 324 322 325 323 /////////////////////////////////////////////////////////////////////// … … 327 325 /////////////////////////////////////////////////////////////////////// 328 326 329 #define IOX_IOB0_TGT_ID 0// don't change this value330 #define IOX_IOB1_TGT_ID 1// don't change this value331 #define IOX_FBUF_TGT_ID 332 #define IOX_BDEV_TGT_ID 333 #define IOX_MNIC_TGT_ID 334 #define IOX_CDMA_TGT_ID 335 #define IOX_BROM_TGT_ID 336 #define IOX_MTTY_TGT_ID 337 338 #define IOX_IOB0_INI_ID 0 // Don't change this value339 #define IOX_IOB1_INI_ID 1 // Don't change this value340 #define IOX_BDEV_INI_ID 2341 #define IOX_CDMA_INI_ID 3327 #define IOX_IOB0_TGT_ID 0 // don't change this value 328 #define IOX_IOB1_TGT_ID 1 // don't change this value 329 #define IOX_FBUF_TGT_ID 2 330 #define IOX_BDEV_TGT_ID 3 331 #define IOX_MNIC_TGT_ID 4 332 #define IOX_CDMA_TGT_ID 5 333 #define IOX_BROM_TGT_ID 6 334 #define IOX_MTTY_TGT_ID 7 335 336 #define IOX_IOB0_INI_ID 0 // Don't change this value 337 #define IOX_IOB1_INI_ID 1 // Don't change this value 338 #define IOX_BDEV_INI_ID 2 339 #define IOX_CDMA_INI_ID 3 342 340 343 341 //////////////////////////////////////////////////////////////////////// … … 349 347 using namespace soclib::common; 350 348 351 352 char soft_name[256] = BOOT_SOFT_NAME; // pathname: binary code 353 size_t ncycles = 1000000000; // simulated cycles 354 char disk_name[256] = BDEV_IMAGE_NAME; // pathname: disk image 355 char nic_rx_name[256] = NIC_RX_NAME; // pathname: rx packets file 356 char nic_tx_name[256] = NIC_TX_NAME; // pathname: tx packets file 357 ssize_t threads_nr = 1; // simulator's threads number 358 bool debug_ok = false; // trace activated 359 size_t debug_period = 1; // trace period 360 size_t debug_memc_id = 0xFFFFFFFF; // index of traced memc 361 size_t debug_proc_id = 0xFFFFFFFF; // index of traced proc 362 bool debug_iob = false; // trace iob0 & iob1 when true 363 uint32_t debug_from = 0; // trace start cycle 364 uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor 365 size_t cluster_iob0 = cluster(0,0); // cluster containing IOB0 366 size_t cluster_iob1 = cluster(XMAX-1,YMAX-1); // cluster containing IOB1 367 size_t block_size = BDEV_SECTOR_SIZE; // disk block size 368 size_t x_width = 4; // at most 256 clusters 369 size_t y_width = 4; // at most 256 clusters 370 371 assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and 372 "ERROR: we must have X_WIDTH == Y_WIDTH == 4"); 373 349 char soft_name[256] = BOOT_SOFT_NAME; // pathname: binary code 350 size_t ncycles = 1000000000; // simulated cycles 351 char disk_name[256] = BDEV_IMAGE_NAME; // pathname: disk image 352 char nic_rx_name[256] = NIC_RX_NAME; // pathname: rx packets file 353 char nic_tx_name[256] = NIC_TX_NAME; // pathname: tx packets file 354 ssize_t threads_nr = 1; // simulator's threads number 355 bool debug_ok = false; // trace activated 356 size_t debug_period = 1; // trace period 357 size_t debug_memc_id = 0xFFFFFFFF; // idx of traced memc 358 size_t debug_proc_id = 0xFFFFFFFF; // idx of traced proc 359 bool debug_iob = false; // trace iobs when true 360 uint32_t debug_from = 0; // trace start cycle 361 uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen procs 362 size_t block_size = BDEV_SECTOR_SIZE; // disk block size 363 size_t nb_procs = 1; 364 size_t x_size = 2; 365 size_t y_size = 2; 366 size_t nb_tty_channels = 1; 367 size_t nb_nic_channels = 1; 368 369 assert((X_WIDTH == 4) and (Y_WIDTH == 4)); 370 374 371 ////////////// command line arguments ////////////////////// 375 372 if (argc > 1) … … 380 377 { 381 378 ncycles = atoi(argv[n+1]); 379 continue; 382 380 } 383 elseif ((strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) )381 if ((strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) ) 384 382 { 385 383 strcpy(soft_name, argv[n+1]); 384 continue; 386 385 } 387 else if ((strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) ) 388 { 389 debug_ok = true; 390 debug_from = atoi(argv[n+1]); 391 } 392 else if ((strcmp(argv[n],"-DISK") == 0) && (n+1<argc) ) 386 if ((strcmp(argv[n],"-DISK") == 0) && (n+1<argc) ) 393 387 { 394 388 strcpy(disk_name, argv[n+1]); 389 continue; 395 390 } 396 else if ((strcmp(argv[n],"-MEMCID") == 0) && (n+1<argc) ) 391 if ((strcmp(argv[n],"-NPROCS") == 0) && (n+1<argc)) 392 { 393 nb_procs = atoi(argv[n+1]); 394 assert((nb_procs > 0) && (nb_procs < 5)); 395 continue; 396 } 397 if ((strcmp(argv[n],"-XSIZE") == 0) && (n+1<argc)) 398 { 399 x_size = atoi(argv[n+1]); 400 assert((x_size > 0) && (x_size < X_MAX)); 401 continue; 402 } 403 if ((strcmp(argv[n],"-YSIZE") == 0) && (n+1<argc)) 404 { 405 y_size = atoi(argv[n+1]); 406 assert((y_size > 0) && (y_size < Y_MAX)); 407 continue; 408 } 409 if ((strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) ) 410 { 411 debug_ok = true; 412 debug_from = atoi(argv[n+1]); 413 continue; 414 } 415 if ((strcmp(argv[n],"-MEMCID") == 0) && (n+1<argc) ) 397 416 { 398 417 debug_memc_id = atoi(argv[n+1]); 399 size_t x = debug_memc_id >> 4; 400 size_t y = debug_memc_id & 0xF; 401 if( (x>=XMAX) || (y>=YMAX) ) 402 { 403 std::cout << "PROCID parameter does'nt fit XMAX/YMAX" << std::endl; 404 exit(0); 405 } 418 size_t x = debug_memc_id >> Y_WIDTH; 419 size_t y = debug_memc_id & ((1 << Y_WIDTH) - 1); 420 assert((x < x_size) && (y < y_size)); 421 continue; 406 422 } 407 elseif ((strcmp(argv[n],"-IOB") == 0) && (n+1<argc) )423 if ((strcmp(argv[n],"-IOB") == 0) && (n+1<argc) ) 408 424 { 409 debug_iob = atoi(argv[n+1]); 425 debug_iob = (atoi(argv[n+1]) != 0) ? 1 : 0; 426 continue; 410 427 } 411 elseif ((strcmp(argv[n],"-PROCID") == 0) && (n+1<argc) )428 if ((strcmp(argv[n],"-PROCID") == 0) && (n+1<argc) ) 412 429 { 413 430 debug_proc_id = atoi(argv[n+1]); 414 size_t cluster_xy = debug_proc_id / NB_PROCS_MAX ; 415 size_t x = cluster_xy >> 4; 416 size_t y = cluster_xy & 0xF; 417 if( (x>=XMAX) || (y>=YMAX) ) 418 { 419 std::cout << "PROCID parameter does'nt fit XMAX/YMAX" << std::endl; 420 exit(0); 421 } 431 size_t cluster_xy = debug_proc_id / nb_procs ; 432 size_t x = cluster_xy >> Y_WIDTH; 433 size_t y = cluster_xy & ((1 << Y_WIDTH) - 1); 434 assert((x < x_size) && (y < y_size)); 435 continue; 422 436 } 423 elseif ((strcmp(argv[n], "-THREADS") == 0) && ((n+1) < argc))437 if ((strcmp(argv[n], "-THREADS") == 0) && ((n+1) < argc)) 424 438 { 425 439 threads_nr = atoi(argv[n+1]); 426 threads_nr = (threads_nr < 1) ? 1 : threads_nr; 440 assert(threads_nr > 0); 441 continue; 427 442 } 428 elseif ((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc))443 if ((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc)) 429 444 { 430 445 frozen_cycles = atoi(argv[n+1]); 446 assert(frozen_cycles > 0); 447 continue; 431 448 } 432 elseif ((strcmp(argv[n], "-PERIOD") == 0) && (n+1 < argc))449 if ((strcmp(argv[n], "-PERIOD") == 0) && (n+1 < argc)) 433 450 { 434 451 debug_period = atoi(argv[n+1]); 452 assert(debug_period > 0); 453 continue; 435 454 } 436 else 437 { 438 std::cout << " Arguments are (key,value) couples." << std::endl; 439 std::cout << " The order is not important." << std::endl; 440 std::cout << " Accepted arguments are :" << std::endl << std::endl; 441 std::cout << " -SOFT pathname_for_embedded_soft" << std::endl; 442 std::cout << " -DISK pathname_for_disk_image" << std::endl; 443 std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl; 444 std::cout << " -DEBUG debug_start_cycle" << std::endl; 445 std::cout << " -THREADS simulator's threads number" << std::endl; 446 std::cout << " -FROZEN max_number_of_lines" << std::endl; 447 std::cout << " -PERIOD number_of_cycles between trace" << std::endl; 448 std::cout << " -MEMCID index_memc_to_be_traced" << std::endl; 449 std::cout << " -PROCID index_proc_to_be_traced" << std::endl; 450 std::cout << " -IOB non_zero_value" << std::endl; 451 exit(0); 452 } 455 456 std::cout << " Arguments are (key,value) couples.\n" 457 << " The order is not important.\n" 458 << " Accepted arguments are :\n\n" 459 << " -NCYCLES number of simulated_cycles\n" 460 << " -SOFT pathname for embedded soft\n" 461 << " -DISK pathname for disk image\n" 462 << " -NPROCS number of processors per cluster\n" 463 << " -XSIZE number of clusters on X\n" 464 << " -YSIZE number of clusters on Y\n" 465 << " -DEBUG debug start cycle\n" 466 << " -MEMCID index of memc to trace\n" 467 << " -IOB debug IOBs if non_zero_value\n\n" 468 << " -PROCID index of proc to trace\n" 469 << " -THREADS simulator's threads number\n" 470 << " -FROZEN max number of frozen cycles\n" 471 << " -PERIOD number of cycles between trace\n\n"; 472 exit(0); 453 473 } 454 474 } 455 475 456 // checking hardware parameters 457 assert( (XMAX <= 16) and 458 "The XMAX parameter cannot be larger than 16" ); 459 460 assert( (YMAX <= 16) and 461 "The YMAX parameter cannot be larger than 16" ); 462 463 assert( (NB_PROCS_MAX <= 8) and 464 "The NB_PROCS_MAX parameter cannot be larger than 8" ); 465 466 assert( (NB_DMA_CHANNELS <= 4) and 467 "The NB_DMA_CHANNELS parameter cannot be larger than 4" ); 468 469 assert( (NB_TTY_CHANNELS < 16) and 476 // one DMA channel per proc 477 size_t nb_dma_channels = nb_procs; 478 479 // clusters containing IOB0 and IOB1 480 size_t cluster_iob0 = cluster(0,0); 481 size_t cluster_iob1 = cluster(x_size - 1, y_size - 1); 482 483 assert( (nb_tty_channels < 16) and 470 484 "The NB_TTY_CHANNELS parameter must be smaller than 16" ); 471 485 472 assert( ( NB_NIC_CHANNELS == 2) and473 "The NB_NIC_CHANNELS parameter must be 2" );486 assert( (nb_nic_channels == 1) and 487 "The NB_NIC_CHANNELS parameter must be 1" ); 474 488 475 489 std::cout << std::endl; 476 std::cout << " - X MAX = " << XMAX<< std::endl;477 std::cout << " - Y MAX = " << YMAX<< std::endl;478 std::cout << " - NB_PROCS _MAX = " << NB_PROCS_MAX <<std::endl;479 std::cout << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS <<std::endl;480 std::cout << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS <<std::endl;481 std::cout << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS <<std::endl;482 std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl;483 std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl;484 std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl;485 std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl;490 std::cout << " - X_SIZE = " << x_size << std::endl; 491 std::cout << " - Y_SIZE = " << y_size << std::endl; 492 std::cout << " - NB_PROCS = " << nb_procs << std::endl; 493 std::cout << " - NB_DMA_CHANNELS = " << nb_dma_channels << std::endl; 494 std::cout << " - NB_TTY_CHANNELS = " << nb_tty_channels << std::endl; 495 std::cout << " - NB_NIC_CHANNELS = " << nb_nic_channels << std::endl; 496 std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl; 497 std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl; 498 std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl; 499 std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl; 486 500 487 501 std::cout << std::endl; … … 508 522 vci_plen_width, 509 523 vci_address_width, 510 vci_rerror_width, 524 vci_rerror_width, 511 525 vci_clen_width, 512 526 vci_rflag_width, … … 523 537 // - 4 local targets (MEMC, XICU, MDMA, IOBX) per cluster 524 538 ///////////////////////////////////////////////////////////////////// 525 MappingTable maptab_int( vci_address_width, 526 IntTab(x_width + y_width, 16 - x_width - y_width), 527 IntTab(x_width + y_width, vci_srcid_width - x_width - y_width), 528 0x00FF000000); 529 530 for (size_t x = 0; x < XMAX; x++) 539 MappingTable maptab_int( 540 vci_address_width, 541 IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH), 542 IntTab(X_WIDTH + Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH), 543 0x00FF000000); 544 545 for (size_t x = 0; x < x_size; x++) 531 546 { 532 for (size_t y = 0; y < YMAX; y++)547 for (size_t y = 0; y < y_size; y++) 533 548 { 534 uint64_t offset = ((uint64_t)cluster(x,y)) 535 << (vci_address_width-x_width-y_width);549 uint64_t offset = ((uint64_t)cluster(x,y)) 550 << (vci_address_width - X_WIDTH - Y_WIDTH); 536 551 bool config = true; 537 552 bool cacheable = true; … … 539 554 // the four following segments are defined in all clusters 540 555 541 std::ostringstream 556 std::ostringstream smemc_conf; 542 557 smemc_conf << "int_seg_memc_conf_" << x << "_" << y; 543 558 maptab_int.add(Segment(smemc_conf.str(), MEMC_BASE+offset, MEMC_SIZE, 544 IntTab(cluster(x,y),INT_MEMC_TGT_ID), not cacheable, config )); 545 546 std::ostringstream smemc_xram; 559 IntTab(cluster(x,y),INT_MEMC_TGT_ID), 560 not cacheable, config )); 561 562 std::ostringstream smemc_xram; 547 563 smemc_xram << "int_seg_memc_xram_" << x << "_" << y; 548 564 maptab_int.add(Segment(smemc_xram.str(), XRAM_BASE+offset, XRAM_SIZE, 549 IntTab(cluster(x,y),INT_MEMC_TGT_ID), cacheable)); 550 551 std::ostringstream sxicu; 565 IntTab(cluster(x,y),INT_MEMC_TGT_ID), 566 cacheable)); 567 568 std::ostringstream sxicu; 552 569 sxicu << "int_seg_xicu_" << x << "_" << y; 553 maptab_int.add(Segment(sxicu.str(), XICU_BASE+offset, XICU_SIZE, 554 IntTab(cluster(x,y),INT_XICU_TGT_ID), not cacheable)); 555 556 std::ostringstream smdma; 570 maptab_int.add(Segment(sxicu.str(), XICU_BASE+offset, XICU_SIZE, 571 IntTab(cluster(x,y),INT_XICU_TGT_ID), 572 not cacheable)); 573 574 std::ostringstream smdma; 557 575 smdma << "int_seg_mdma_" << x << "_" << y; 558 maptab_int.add(Segment(smdma.str(), MDMA_BASE+offset, MDMA_SIZE, 559 IntTab(cluster(x,y),INT_MDMA_TGT_ID), not cacheable)); 560 561 // the following segments are only defined in cluster_iob0 or in cluster_iob1 562 563 if ( (cluster(x,y) == cluster_iob0) or (cluster(x,y) == cluster_iob1) ) 576 maptab_int.add(Segment(smdma.str(), MDMA_BASE+offset, MDMA_SIZE, 577 IntTab(cluster(x,y),INT_MDMA_TGT_ID), 578 not cacheable)); 579 580 // the following segments are only defined in cluster_iob0 or in 581 // cluster_iob1 582 if ((cluster(x,y) == cluster_iob0) || (cluster(x,y) == cluster_iob1)) 564 583 { 565 std::ostringstream 584 std::ostringstream siobx; 566 585 siobx << "int_seg_iobx_" << x << "_" << y; 567 maptab_int.add(Segment(siobx.str(), IOBX_BASE+offset, IOBX_SIZE, 568 IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable, config )); 569 570 std::ostringstream stty; 586 maptab_int.add(Segment(siobx.str(), IOBX_BASE+offset, IOBX_SIZE, 587 IntTab(cluster(x,y), INT_IOBX_TGT_ID), 588 not cacheable, config )); 589 590 std::ostringstream stty; 571 591 stty << "int_seg_mtty_" << x << "_" << y; 572 maptab_int.add(Segment(stty.str(), MTTY_BASE+offset, MTTY_SIZE, 573 IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); 574 575 std::ostringstream sfbf; 592 maptab_int.add(Segment(stty.str(), MTTY_BASE+offset, MTTY_SIZE, 593 IntTab(cluster(x,y), INT_IOBX_TGT_ID), 594 not cacheable)); 595 596 std::ostringstream sfbf; 576 597 sfbf << "int_seg_fbuf_" << x << "_" << y; 577 maptab_int.add(Segment(sfbf.str(), FBUF_BASE+offset, FBUF_SIZE, 578 IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); 579 580 std::ostringstream sbdv; 598 maptab_int.add(Segment(sfbf.str(), FBUF_BASE+offset, FBUF_SIZE, 599 IntTab(cluster(x,y), INT_IOBX_TGT_ID), 600 not cacheable)); 601 602 std::ostringstream sbdv; 581 603 sbdv << "int_seg_bdev_" << x << "_" << y; 582 maptab_int.add(Segment(sbdv.str(), BDEV_BASE+offset, BDEV_SIZE, 583 IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); 584 585 std::ostringstream snic; 604 maptab_int.add(Segment(sbdv.str(), BDEV_BASE+offset, BDEV_SIZE, 605 IntTab(cluster(x,y), INT_IOBX_TGT_ID), 606 not cacheable)); 607 608 std::ostringstream snic; 586 609 snic << "int_seg_mnic_" << x << "_" << y; 587 maptab_int.add(Segment(snic.str(), MNIC_BASE+offset, MNIC_SIZE, 588 IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); 589 590 std::ostringstream srom; 610 maptab_int.add(Segment(snic.str(), MNIC_BASE+offset, MNIC_SIZE, 611 IntTab(cluster(x,y), INT_IOBX_TGT_ID), 612 not cacheable)); 613 614 std::ostringstream srom; 591 615 srom << "int_seg_brom_" << x << "_" << y; 592 maptab_int.add(Segment(srom.str(), BROM_BASE+offset, BROM_SIZE, 593 IntTab(cluster(x,y), INT_IOBX_TGT_ID), cacheable )); 594 595 std::ostringstream sdma; 616 maptab_int.add(Segment(srom.str(), BROM_BASE+offset, BROM_SIZE, 617 IntTab(cluster(x,y), INT_IOBX_TGT_ID), 618 cacheable )); 619 620 std::ostringstream sdma; 596 621 sdma << "int_seg_cdma_" << x << "_" << y; 597 maptab_int.add(Segment(sdma.str(), CDMA_BASE+offset, CDMA_SIZE, 598 IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); 622 maptab_int.add(Segment(sdma.str(), CDMA_BASE+offset, CDMA_SIZE, 623 IntTab(cluster(x,y), INT_IOBX_TGT_ID), 624 not cacheable)); 599 625 } 600 626 … … 602 628 // and the port index on the local interconnect. 603 629 604 maptab_int.srcid_map( IntTab( cluster(x,y), MDMA_LOCAL_SRCID ), 605 IntTab( cluster(x,y), INT_MDMA_INI_ID ) ); 606 607 maptab_int.srcid_map( IntTab( cluster(x,y), IOBX_LOCAL_SRCID ), 608 IntTab( cluster(x,y), INT_IOBX_INI_ID ) ); 609 610 for ( size_t p = 0 ; p < NB_PROCS_MAX ; p++ ) 611 maptab_int.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID+p ), 612 IntTab( cluster(x,y), INT_PROC_INI_ID+p ) ); 630 maptab_int.srcid_map(IntTab(cluster(x,y), MDMA_LOCAL_SRCID), 631 IntTab(cluster(x,y), INT_MDMA_INI_ID)); 632 maptab_int.srcid_map(IntTab(cluster(x,y), IOBX_LOCAL_SRCID), 633 IntTab(cluster(x,y), INT_IOBX_INI_ID)); 634 635 for ( size_t p = 0 ; p < nb_procs ; p++ ) 636 { 637 maptab_int.srcid_map(IntTab(cluster(x,y), PROC_LOCAL_SRCID + p), 638 IntTab(cluster(x,y), INT_PROC_INI_ID + p)); 639 } 613 640 } 614 641 } … … 616 643 617 644 ///////////////////////////////////////////////////////////////////////// 618 // RAM network mapping table 645 // RAM network mapping table 619 646 // - two levels address decoding for commands 620 647 // - two levels srcid decoding for responses 621 // - 2 local initiators (MEMC, IOBX) per cluster 648 // - 2 local initiators (MEMC, IOBX) per cluster 622 649 // (IOBX component only in cluster_iob0 and cluster_iob1) 623 650 // - 1 local target (XRAM) per cluster 624 651 //////////////////////////////////////////////////////////////////////// 625 MappingTable maptab_ram( vci_address_width, 626 IntTab(x_width+y_width, 16 - x_width - y_width), 627 IntTab(x_width+y_width, vci_srcid_width - x_width - y_width), 628 0x00FF000000); 629 630 for (size_t x = 0; x < XMAX; x++) 652 MappingTable maptab_ram( 653 vci_address_width, 654 IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH), 655 IntTab(X_WIDTH + Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH), 656 0x00FF000000); 657 658 for (size_t x = 0; x < x_size; x++) 631 659 { 632 for (size_t y = 0; y < YMAX; y++)633 { 634 uint64_t offset = ((uint64_t)cluster(x,y))635 << (vci_address_width-x_width-y_width);660 for (size_t y = 0; y < y_size ; y++) 661 { 662 uint64_t offset = ((uint64_t)cluster(x,y)) 663 << (vci_address_width - X_WIDTH - Y_WIDTH); 636 664 637 665 std::ostringstream sxram; 638 666 sxram << "ext_seg_xram_" << x << "_" << y; 639 maptab_ram.add(Segment(sxram.str(), XRAM_BASE+offset, 640 XRAM_SIZE, IntTab(cluster(x,y), 0), false));667 maptab_ram.add(Segment(sxram.str(), XRAM_BASE+offset, 668 XRAM_SIZE, IntTab(cluster(x,y), 0), false)); 641 669 } 642 670 } … … 644 672 // This define the mapping between the initiators SRCID 645 673 // and the port index on the RAM local interconnect. 646 // External initiator have two alias SRCID (iob0 / iob1) 647 648 maptab_ram.srcid_map( IntTab( cluster_iob0, CDMA_LOCAL_SRCID ), 649 IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); 650 651 maptab_ram.srcid_map( IntTab( cluster_iob1, CDMA_LOCAL_SRCID ), 652 IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); 653 654 maptab_ram.srcid_map( IntTab( cluster_iob0, BDEV_LOCAL_SRCID ), 655 IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); 656 657 maptab_ram.srcid_map( IntTab( cluster_iob1, BDEV_LOCAL_SRCID ), 658 IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); 659 660 maptab_ram.srcid_map( IntTab( cluster_iob1, MEMC_LOCAL_SRCID ), 661 IntTab( cluster_iob1, RAM_MEMC_INI_ID ) ); 674 // External initiator have two alias SRCID (iob0 / iob1) 675 676 maptab_ram.srcid_map(IntTab(cluster_iob0, CDMA_LOCAL_SRCID), 677 IntTab(cluster_iob0, RAM_IOBX_INI_ID)); 678 maptab_ram.srcid_map(IntTab(cluster_iob1, CDMA_LOCAL_SRCID), 679 IntTab(cluster_iob1, RAM_IOBX_INI_ID)); 680 maptab_ram.srcid_map(IntTab(cluster_iob0, BDEV_LOCAL_SRCID), 681 IntTab(cluster_iob0, RAM_IOBX_INI_ID)); 682 maptab_ram.srcid_map(IntTab(cluster_iob1, BDEV_LOCAL_SRCID), 683 IntTab(cluster_iob1, RAM_IOBX_INI_ID)); 684 maptab_ram.srcid_map(IntTab(cluster_iob1, MEMC_LOCAL_SRCID), 685 IntTab(cluster_iob1, RAM_MEMC_INI_ID)); 662 686 663 687 std::cout << "RAM network " << maptab_ram << std::endl; 664 688 665 689 /////////////////////////////////////////////////////////////////////// 666 // IOX network mapping table 690 // IOX network mapping table 667 691 // - two levels address decoding for commands 668 692 // - two levels srcid decoding for responses … … 670 694 // - 8 targets (IOB0, IOB1, BDEV, CDMA, MTTY, FBUF, BROM, MNIC) 671 695 /////////////////////////////////////////////////////////////////////// 672 MappingTable maptab_iox( vci_address_width, 673 IntTab(x_width+y_width, 16 - x_width - y_width), 674 IntTab(x_width+y_width, vci_srcid_width - x_width - y_width), 675 0x00FF000000); 696 MappingTable maptab_iox( 697 vci_address_width, 698 IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH), 699 IntTab(X_WIDTH + Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH), 700 0x00FF000000); 676 701 677 702 // compute base addresses for cluster_iob0 and cluster_iob1 678 uint64_t iob0_base = ((uint64_t)cluster_iob0) << (vci_address_width - x_width - y_width); 679 uint64_t iob1_base = ((uint64_t)cluster_iob1) << (vci_address_width - x_width - y_width); 703 uint64_t iob0_base = ((uint64_t)cluster_iob0) 704 << (vci_address_width - X_WIDTH - Y_WIDTH); 705 uint64_t iob1_base = ((uint64_t)cluster_iob1) 706 << (vci_address_width - X_WIDTH - Y_WIDTH); 680 707 681 708 // Each peripheral can be accessed through two segments, 682 709 // depending on the used IOB (IOB0 or IOB1). 683 maptab_iox.add(Segment("iox_seg_mtty_0", MTTY_BASE + iob0_base, MTTY_SIZE, 684 IntTab(cluster_iob0,IOX_MTTY_TGT_ID), false)); 685 maptab_iox.add(Segment("iox_seg_mtty_1", MTTY_BASE + iob1_base, MTTY_SIZE, 686 IntTab(cluster_iob1,IOX_MTTY_TGT_ID), false)); 687 688 maptab_iox.add(Segment("iox_seg_fbuf_0", FBUF_BASE + iob0_base, FBUF_SIZE, 689 IntTab(cluster_iob0,IOX_FBUF_TGT_ID), false)); 690 maptab_iox.add(Segment("iox_seg_fbuf_1", FBUF_BASE + iob1_base, FBUF_SIZE, 691 IntTab(cluster_iob1,IOX_FBUF_TGT_ID), false)); 692 693 maptab_iox.add(Segment("iox_seg_bdev_0", BDEV_BASE + iob0_base, BDEV_SIZE, 694 IntTab(cluster_iob0,IOX_BDEV_TGT_ID), false)); 695 maptab_iox.add(Segment("iox_seg_bdev_1", BDEV_BASE + iob1_base, BDEV_SIZE, 696 IntTab(cluster_iob1,IOX_BDEV_TGT_ID), false)); 697 698 maptab_iox.add(Segment("iox_seg_mnic_0", MNIC_BASE + iob0_base, MNIC_SIZE, 699 IntTab(cluster_iob0,IOX_MNIC_TGT_ID), false)); 700 maptab_iox.add(Segment("iox_seg_mnic_1", MNIC_BASE + iob1_base, MNIC_SIZE, 701 IntTab(cluster_iob1,IOX_MNIC_TGT_ID), false)); 702 703 maptab_iox.add(Segment("iox_seg_cdma_0", CDMA_BASE + iob0_base, CDMA_SIZE, 704 IntTab(cluster_iob0,IOX_CDMA_TGT_ID), false)); 705 maptab_iox.add(Segment("iox_seg_cdma_1", CDMA_BASE + iob1_base, CDMA_SIZE, 706 IntTab(cluster_iob1,IOX_CDMA_TGT_ID), false)); 707 708 maptab_iox.add(Segment("iox_seg_brom_0", BROM_BASE + iob0_base, BROM_SIZE, 709 IntTab(cluster_iob0,IOX_BROM_TGT_ID), false)); 710 maptab_iox.add(Segment("iox_seg_brom_1", BROM_BASE + iob1_base, BROM_SIZE, 711 IntTab(cluster_iob1,IOX_BROM_TGT_ID), false)); 710 maptab_iox.add(Segment("iox_seg_mtty_0", MTTY_BASE + iob0_base, MTTY_SIZE, 711 IntTab(cluster_iob0, IOX_MTTY_TGT_ID), false)); 712 maptab_iox.add(Segment("iox_seg_mtty_1", MTTY_BASE + iob1_base, MTTY_SIZE, 713 IntTab(cluster_iob1, IOX_MTTY_TGT_ID), false)); 714 maptab_iox.add(Segment("iox_seg_fbuf_0", FBUF_BASE + iob0_base, FBUF_SIZE, 715 IntTab(cluster_iob0, IOX_FBUF_TGT_ID), false)); 716 maptab_iox.add(Segment("iox_seg_fbuf_1", FBUF_BASE + iob1_base, FBUF_SIZE, 717 IntTab(cluster_iob1, IOX_FBUF_TGT_ID), false)); 718 maptab_iox.add(Segment("iox_seg_bdev_0", BDEV_BASE + iob0_base, BDEV_SIZE, 719 IntTab(cluster_iob0, IOX_BDEV_TGT_ID), false)); 720 maptab_iox.add(Segment("iox_seg_bdev_1", BDEV_BASE + iob1_base, BDEV_SIZE, 721 IntTab(cluster_iob1, IOX_BDEV_TGT_ID), false)); 722 maptab_iox.add(Segment("iox_seg_mnic_0", MNIC_BASE + iob0_base, MNIC_SIZE, 723 IntTab(cluster_iob0, IOX_MNIC_TGT_ID), false)); 724 maptab_iox.add(Segment("iox_seg_mnic_1", MNIC_BASE + iob1_base, MNIC_SIZE, 725 IntTab(cluster_iob1, IOX_MNIC_TGT_ID), false)); 726 maptab_iox.add(Segment("iox_seg_cdma_0", CDMA_BASE + iob0_base, CDMA_SIZE, 727 IntTab(cluster_iob0, IOX_CDMA_TGT_ID), false)); 728 maptab_iox.add(Segment("iox_seg_cdma_1", CDMA_BASE + iob1_base, CDMA_SIZE, 729 IntTab(cluster_iob1, IOX_CDMA_TGT_ID), false)); 730 maptab_iox.add(Segment("iox_seg_brom_0", BROM_BASE + iob0_base, BROM_SIZE, 731 IntTab(cluster_iob0,IOX_BROM_TGT_ID), false)); 732 maptab_iox.add(Segment("iox_seg_brom_1", BROM_BASE + iob1_base, BROM_SIZE, 733 IntTab(cluster_iob1,IOX_BROM_TGT_ID), false)); 712 734 713 735 // Each physical RAM can be accessed through IOB0, or through IOB1. 714 736 // if IOMMU is not activated, addresses are 40 bits (physical addresses), 715 737 // and the choice depends on on address bit A[39]. 716 // if IOMMU is activated the addresses use only 32 bits (virtual addresses),717 // a nd the choice depends on address bit A[31].718 for (size_t x = 0; x < XMAX; x++)738 // if IOMMU is activated the addresses use only 32 bits (virtual 739 // addresses), and the choice depends on address bit A[31]. 740 for (size_t x = 0; x < x_size; x++) 719 741 { 720 for (size_t y = 0; y < YMAX ; y++) 721 { 722 uint64_t offset = ((uint64_t)cluster(x,y)) 723 << (vci_address_width-x_width-y_width); 724 725 if ( x < (XMAX/2) ) // send command to XRAM through IOB0 742 for (size_t y = 0; y < y_size ; y++) 743 { 744 uint64_t offset = ((uint64_t)cluster(x,y)) 745 << (vci_address_width - X_WIDTH - Y_WIDTH); 746 747 // send command to XRAM through IOB0 748 if ( x < (x_size/2) ) 726 749 { 727 750 std::ostringstream siob0; 728 751 siob0 << "iox_seg_xram_" << x << "_" << y; 729 maptab_iox.add(Segment(siob0.str(), offset, 0x80000000, 730 IntTab(cluster_iob0,IOX_IOB0_TGT_ID), false)); 752 maptab_iox.add(Segment(siob0.str(), offset, 0x80000000, 753 IntTab(cluster_iob0,IOX_IOB0_TGT_ID), 754 false)); 731 755 } 732 else // send command to XRAM through IOB1 756 // send command to XRAM through IOB1 757 else 733 758 { 734 759 std::ostringstream siob1; 735 760 siob1 << "iox_seg_xram_" << x << "_" << y; 736 maptab_iox.add(Segment(siob1.str(), offset, 0x80000000, 737 IntTab(cluster_iob1,IOX_IOB1_TGT_ID), false)); 761 maptab_iox.add(Segment(siob1.str(), offset, 0x80000000, 762 IntTab(cluster_iob1,IOX_IOB1_TGT_ID), 763 false)); 738 764 } 739 765 } 740 766 } 741 767 // useful when IOMMU activated 742 maptab_iox.add(Segment("iox_seg_xram ", 0xc0000000, 0x40000000,743 IntTab(cluster_iob1,IOX_IOB1_TGT_ID), false));768 maptab_iox.add(Segment("iox_seg_xram", 0xc0000000, 0x40000000, 769 IntTab(cluster_iob1,IOX_IOB1_TGT_ID), false)); 744 770 745 771 // This define the mapping between the initiators (identified by the SRCID) 746 772 // and the port index on the IOX local interconnect. 747 // External initiator have two alias SRCID (iob0 / iob1 access) 748 749 maptab_iox.srcid_map( IntTab( cluster_iob0, CDMA_LOCAL_SRCID ), 750 IntTab( cluster_iob0, IOX_CDMA_INI_ID ) ); 751 752 maptab_iox.srcid_map( IntTab( cluster_iob1, CDMA_LOCAL_SRCID ), 753 IntTab( cluster_iob1, IOX_CDMA_INI_ID ) ); 754 755 maptab_iox.srcid_map( IntTab( cluster_iob0, BDEV_LOCAL_SRCID ), 756 IntTab( cluster_iob0, IOX_BDEV_INI_ID ) ); 757 758 maptab_iox.srcid_map( IntTab( cluster_iob1, BDEV_LOCAL_SRCID ), 759 IntTab( cluster_iob0, IOX_BDEV_INI_ID ) ); 760 761 for (size_t x = 0; x < XMAX; x++) 773 // External initiator have two alias SRCID (iob0 / iob1 access) 774 775 maptab_iox.srcid_map(IntTab(cluster_iob0, CDMA_LOCAL_SRCID), 776 IntTab(cluster_iob0, IOX_CDMA_INI_ID)); 777 maptab_iox.srcid_map(IntTab(cluster_iob1, CDMA_LOCAL_SRCID), 778 IntTab(cluster_iob1, IOX_CDMA_INI_ID)); 779 maptab_iox.srcid_map(IntTab(cluster_iob0, BDEV_LOCAL_SRCID), 780 IntTab(cluster_iob0, IOX_BDEV_INI_ID)); 781 maptab_iox.srcid_map(IntTab(cluster_iob1, BDEV_LOCAL_SRCID), 782 IntTab(cluster_iob0, IOX_BDEV_INI_ID)); 783 784 for (size_t x = 0; x < x_size; x++) 762 785 { 763 for (size_t y = 0; y < YMAX ; y++) 764 { 765 size_t iob = ( x < (XMAX/2) ) ? IOX_IOB0_INI_ID : IOX_IOB1_INI_ID; 766 767 for (size_t p = 0 ; p < NB_PROCS_MAX ; p++) 768 maptab_iox.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID + p ), 769 IntTab( cluster(x,y), iob ) ); 770 771 maptab_iox.srcid_map( IntTab( cluster(x,y), MDMA_LOCAL_SRCID ), 772 IntTab( cluster(x,y), IOX_IOB0_INI_ID ) ); 786 for (size_t y = 0; y < y_size ; y++) 787 { 788 size_t iob = (x < (x_size / 2)) ? IOX_IOB0_INI_ID 789 : IOX_IOB1_INI_ID; 790 791 for (size_t p = 0 ; p < nb_procs ; p++) 792 { 793 maptab_iox.srcid_map(IntTab(cluster(x,y), PROC_LOCAL_SRCID + p), 794 IntTab(cluster(x,y), iob)); 795 } 796 maptab_iox.srcid_map(IntTab( cluster(x,y), MDMA_LOCAL_SRCID), 797 IntTab( cluster(x,y), IOX_IOB0_INI_ID)); 773 798 } 774 799 } … … 778 803 //////////////////// 779 804 // Signals 780 /////////////////// 781 782 sc_clock 783 sc_signal<bool> 784 785 sc_signal<bool> 786 sc_signal<bool> 787 sc_signal<bool> signal_irq_mnic_rx[NB_NIC_CHANNELS];788 sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS];789 sc_signal<bool> signal_irq_mtty[NB_TTY_CHANNELS];790 sc_signal<bool> signal_irq_cdma[NB_NIC_CHANNELS*2];805 //////////////////// 806 807 sc_clock signal_clk("clk"); 808 sc_signal<bool> signal_resetn("resetn"); 809 810 sc_signal<bool> signal_irq_false; 811 sc_signal<bool> signal_irq_bdev; 812 sc_signal<bool> signal_irq_mnic_rx[1]; 813 sc_signal<bool> signal_irq_mnic_tx[1]; 814 sc_signal<bool> signal_irq_mtty[16]; 815 sc_signal<bool> signal_irq_cdma[1*2]; 791 816 792 817 // DSPIN signals for loopback in cluster_iob0 & cluster_iob1 793 DspinSignals<dspin_ram_cmd_width> signal_dspin_cmd_iob0_loopback; 794 DspinSignals<dspin_ram_rsp_width> signal_dspin_rsp_iob0_loopback; 795 DspinSignals<dspin_ram_cmd_width> signal_dspin_cmd_iob1_loopback; 796 DspinSignals<dspin_ram_rsp_width> signal_dspin_rsp_iob1_loopback; 818 DspinSignals<dspin_ram_cmd_width> signal_dspin_cmd_iob0_loopback; 819 DspinSignals<dspin_ram_rsp_width> signal_dspin_rsp_iob0_loopback; 820 DspinSignals<dspin_ram_cmd_width> signal_dspin_cmd_iob1_loopback; 821 DspinSignals<dspin_ram_rsp_width> signal_dspin_rsp_iob1_loopback; 797 822 798 823 // VCI signals for IOX network 799 VciSignals<vci_param_ext> 800 VciSignals<vci_param_ext> 801 VciSignals<vci_param_ext> 802 VciSignals<vci_param_ext> 803 804 VciSignals<vci_param_ext> 805 VciSignals<vci_param_ext> 806 VciSignals<vci_param_ext> 807 VciSignals<vci_param_ext> 808 VciSignals<vci_param_ext> 809 VciSignals<vci_param_ext> 810 VciSignals<vci_param_ext> 811 VciSignals<vci_param_ext> 812 813 // Horizontal inter-clusters INT network DSPIN 824 VciSignals<vci_param_ext> signal_vci_ini_iob0("signal_vci_ini_iob0"); 825 VciSignals<vci_param_ext> signal_vci_ini_iob1("signal_vci_ini_iob1"); 826 VciSignals<vci_param_ext> signal_vci_ini_bdev("signal_vci_ini_bdev"); 827 VciSignals<vci_param_ext> signal_vci_ini_cdma("signal_vci_ini_cdma"); 828 829 VciSignals<vci_param_ext> signal_vci_tgt_iob0("signal_vci_tgt_iob0"); 830 VciSignals<vci_param_ext> signal_vci_tgt_iob1("signal_vci_tgt_iob1"); 831 VciSignals<vci_param_ext> signal_vci_tgt_mtty("signal_vci_tgt_mtty"); 832 VciSignals<vci_param_ext> signal_vci_tgt_fbuf("signal_vci_tgt_fbuf"); 833 VciSignals<vci_param_ext> signal_vci_tgt_mnic("signal_vci_tgt_mnic"); 834 VciSignals<vci_param_ext> signal_vci_tgt_brom("signal_vci_tgt_brom"); 835 VciSignals<vci_param_ext> signal_vci_tgt_bdev("signal_vci_tgt_bdev"); 836 VciSignals<vci_param_ext> signal_vci_tgt_cdma("signal_vci_tgt_cdma"); 837 838 // Horizontal inter-clusters INT network DSPIN 814 839 DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_h_inc = 815 alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_h_inc", XMAX-1, YMAX, 3); 840 alloc_elems<DspinSignals<dspin_int_cmd_width> >( 841 "signal_dspin_int_cmd_h_inc", x_size-1, y_size, 3); 816 842 DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_h_dec = 817 alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_h_dec", XMAX-1, YMAX, 3); 843 alloc_elems<DspinSignals<dspin_int_cmd_width> >( 844 "signal_dspin_int_cmd_h_dec", x_size-1, y_size, 3); 818 845 DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_h_inc = 819 alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_h_inc", XMAX-1, YMAX, 2); 846 alloc_elems<DspinSignals<dspin_int_rsp_width> >( 847 "signal_dspin_int_rsp_h_inc", x_size-1, y_size, 2); 820 848 DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_h_dec = 821 alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_h_dec", XMAX-1, YMAX, 2); 849 alloc_elems<DspinSignals<dspin_int_rsp_width> >( 850 "signal_dspin_int_rsp_h_dec", x_size-1, y_size, 2); 822 851 823 852 // Vertical inter-clusters INT network DSPIN 824 853 DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_v_inc = 825 alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_v_inc", XMAX, YMAX-1, 3); 854 alloc_elems<DspinSignals<dspin_int_cmd_width> >( 855 "signal_dspin_int_cmd_v_inc", x_size, y_size-1, 3); 826 856 DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_v_dec = 827 alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_v_dec", XMAX, YMAX-1, 3); 857 alloc_elems<DspinSignals<dspin_int_cmd_width> >( 858 "signal_dspin_int_cmd_v_dec", x_size, y_size-1, 3); 828 859 DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_v_inc = 829 alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_v_inc", XMAX, YMAX-1, 2); 860 alloc_elems<DspinSignals<dspin_int_rsp_width> >( 861 "signal_dspin_int_rsp_v_inc", x_size, y_size-1, 2); 830 862 DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_v_dec = 831 alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_v_dec", XMAX, YMAX-1, 2); 832 833 // Mesh boundaries INT network DSPIN 863 alloc_elems<DspinSignals<dspin_int_rsp_width> >( 864 "signal_dspin_int_rsp_v_dec", x_size, y_size-1, 2); 865 866 // Mesh boundaries INT network DSPIN 834 867 DspinSignals<dspin_int_cmd_width>**** signal_dspin_false_int_cmd_in = 835 alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cmd_in", XMAX, YMAX, 4, 3); 868 alloc_elems<DspinSignals<dspin_int_cmd_width> >( 869 "signal_dspin_false_int_cmd_in", x_size, y_size, 4, 3); 836 870 DspinSignals<dspin_int_cmd_width>**** signal_dspin_false_int_cmd_out = 837 alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cmd_out", XMAX, YMAX, 4, 3); 871 alloc_elems<DspinSignals<dspin_int_cmd_width> >( 872 "signal_dspin_false_int_cmd_out", x_size, y_size, 4, 3); 838 873 DspinSignals<dspin_int_rsp_width>**** signal_dspin_false_int_rsp_in = 839 alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_rsp_in", XMAX, YMAX, 4, 2); 874 alloc_elems<DspinSignals<dspin_int_rsp_width> >( 875 "signal_dspin_false_int_rsp_in", x_size, y_size, 4, 2); 840 876 DspinSignals<dspin_int_rsp_width>**** signal_dspin_false_int_rsp_out = 841 alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_rsp_out", XMAX, YMAX, 4, 2); 842 843 844 // Horizontal inter-clusters RAM network DSPIN 877 alloc_elems<DspinSignals<dspin_int_rsp_width> >( 878 "signal_dspin_false_int_rsp_out", x_size, y_size, 4, 2); 879 880 881 // Horizontal inter-clusters RAM network DSPIN 845 882 DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_inc = 846 alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_h_inc", XMAX-1, YMAX); 883 alloc_elems<DspinSignals<dspin_ram_cmd_width> >( 884 "signal_dspin_ram_cmd_h_inc", x_size-1, y_size); 847 885 DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_dec = 848 alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_h_dec", XMAX-1, YMAX); 886 alloc_elems<DspinSignals<dspin_ram_cmd_width> >( 887 "signal_dspin_ram_cmd_h_dec", x_size-1, y_size); 849 888 DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_inc = 850 alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_h_inc", XMAX-1, YMAX); 889 alloc_elems<DspinSignals<dspin_ram_rsp_width> >( 890 "signal_dspin_ram_rsp_h_inc", x_size-1, y_size); 851 891 DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_dec = 852 alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_h_dec", XMAX-1, YMAX); 892 alloc_elems<DspinSignals<dspin_ram_rsp_width> >( 893 "signal_dspin_ram_rsp_h_dec", x_size-1, y_size); 853 894 854 895 // Vertical inter-clusters RAM network DSPIN 855 896 DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_inc = 856 alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_v_inc", XMAX, YMAX-1); 897 alloc_elems<DspinSignals<dspin_ram_cmd_width> >( 898 "signal_dspin_ram_cmd_v_inc", x_size, y_size-1); 857 899 DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_dec = 858 alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_v_dec", XMAX, YMAX-1); 900 alloc_elems<DspinSignals<dspin_ram_cmd_width> >( 901 "signal_dspin_ram_cmd_v_dec", x_size, y_size-1); 859 902 DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_inc = 860 alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_v_inc", XMAX, YMAX-1); 903 alloc_elems<DspinSignals<dspin_ram_rsp_width> >( 904 "signal_dspin_ram_rsp_v_inc", x_size, y_size-1); 861 905 DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_dec = 862 alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_v_dec", XMAX, YMAX-1); 863 864 // Mesh boundaries RAM network DSPIN 906 alloc_elems<DspinSignals<dspin_ram_rsp_width> >( 907 "signal_dspin_ram_rsp_v_dec", x_size, y_size-1); 908 909 // Mesh boundaries RAM network DSPIN 865 910 DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_in = 866 alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_false_ram_cmd_in", XMAX, YMAX, 4); 911 alloc_elems<DspinSignals<dspin_ram_cmd_width> >( 912 "signal_dspin_false_ram_cmd_in", x_size, y_size, 4); 867 913 DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_out = 868 alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_false_ram_cmd_out", XMAX, YMAX, 4); 914 alloc_elems<DspinSignals<dspin_ram_cmd_width> >( 915 "signal_dspin_false_ram_cmd_out", x_size, y_size, 4); 869 916 DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_in = 870 alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_false_ram_rsp_in", XMAX, YMAX, 4); 917 alloc_elems<DspinSignals<dspin_ram_rsp_width> >( 918 "signal_dspin_false_ram_rsp_in", x_size, y_size, 4); 871 919 DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_out = 872 alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_false_ram_rsp_out", XMAX, YMAX, 4); 920 alloc_elems<DspinSignals<dspin_ram_rsp_width> >( 921 "signal_dspin_false_ram_rsp_out", x_size, y_size, 4); 873 922 874 923 //////////////////////////// 875 // Loader 924 // Loader 876 925 //////////////////////////// 877 926 … … 891 940 //////////////////////////////////////// 892 941 893 std::cout << std::endl << "External Bus and Peripherals" << std::endl << std::endl; 942 std::cout << std::endl << "External Bus and Peripherals" << std::endl 943 << std::endl; 894 944 895 945 // IOX network 896 946 VciIoxNetwork<vci_param_ext>* iox_network; 897 iox_network = new VciIoxNetwork<vci_param_ext>( "iox_network",898 899 8,// number of targets900 4 );// number of initiators947 iox_network = new VciIoxNetwork<vci_param_ext>("iox_network", 948 maptab_iox, 949 8, // number of targets 950 4 ); // number of initiators 901 951 // boot ROM 902 952 VciSimpleRom<vci_param_ext>* brom; 903 brom = new VciSimpleRom<vci_param_ext>( 904 905 906 953 brom = new VciSimpleRom<vci_param_ext>("brom", 954 IntTab(0, IOX_BROM_TGT_ID), 955 maptab_iox, 956 loader ); 907 957 // Network Controller 908 958 VciMultiNic<vci_param_ext>* mnic; 909 mnic = new VciMultiNic<vci_param_ext>( 910 911 912 NB_NIC_CHANNELS,913 914 915 916 959 mnic = new VciMultiNic<vci_param_ext>("mnic", 960 IntTab(0, IOX_MNIC_TGT_ID), 961 maptab_iox, 962 nb_nic_channels, 963 0, // mac_4 address 964 0, // mac_2 address 965 nic_rx_name, 966 nic_tx_name); 917 967 918 968 // Frame Buffer 919 969 VciFrameBuffer<vci_param_ext>* fbuf; 920 fbuf = new VciFrameBuffer<vci_param_ext>( 921 922 923 970 fbuf = new VciFrameBuffer<vci_param_ext>("fbuf", 971 IntTab(0, IOX_FBUF_TGT_ID), 972 maptab_iox, 973 FBUF_X_SIZE, FBUF_Y_SIZE ); 924 974 925 975 // Block Device 926 976 // for AHCI 927 977 // std::vector<std::string> filenames; 928 // filenames.push_back(disk_name); 978 // filenames.push_back(disk_name); // one single disk 929 979 VciBlockDeviceTsar<vci_param_ext>* bdev; 930 bdev = new VciBlockDeviceTsar<vci_param_ext>( 931 932 933 934 935 936 64, // burst size (bytes)937 0 ); // disk latency980 bdev = new VciBlockDeviceTsar<vci_param_ext>("bdev", 981 maptab_iox, 982 IntTab(0, BDEV_LOCAL_SRCID), 983 IntTab(0, IOX_BDEV_TGT_ID), 984 disk_name, 985 block_size, 986 64, // burst size (bytes) 987 0 ); // disk latency 938 988 939 989 // Chained Buffer DMA controller 940 990 VciChbufDma<vci_param_ext>* cdma; 941 cdma = new VciChbufDma<vci_param_ext>( 942 943 944 945 64,// burst size (bytes)946 2*NB_NIC_CHANNELS);991 cdma = new VciChbufDma<vci_param_ext>("cdma", 992 maptab_iox, 993 IntTab(0, CDMA_LOCAL_SRCID), 994 IntTab(0, IOX_CDMA_TGT_ID), 995 64, // burst size (bytes) 996 2 * nb_nic_channels); 947 997 // Multi-TTY controller 948 998 std::vector<std::string> vect_names; 949 for( size_t tid = 0 ; tid < NB_TTY_CHANNELS; tid++ )999 for( size_t tid = 0 ; tid < nb_tty_channels ; tid++ ) 950 1000 { 951 1001 std::ostringstream term_name; … … 954 1004 } 955 1005 VciMultiTty<vci_param_ext>* mtty; 956 mtty = new VciMultiTty<vci_param_ext>( "mtty", 957 IntTab(0, IOX_MTTY_TGT_ID), 958 maptab_iox, 959 vect_names); 960 // Clusters 961 TsarIobCluster<vci_param_int, 962 vci_param_ext, 963 dspin_int_cmd_width, 964 dspin_int_rsp_width, 965 dspin_ram_cmd_width, 966 dspin_ram_rsp_width>* clusters[XMAX][YMAX]; 1006 mtty = new VciMultiTty<vci_param_ext>("mtty_iox", 1007 IntTab(0, IOX_MTTY_TGT_ID), 1008 maptab_iox, 1009 vect_names); 1010 // Clusters 1011 typedef TsarIobCluster<vci_param_int, vci_param_ext, dspin_int_cmd_width, 1012 dspin_int_rsp_width, dspin_ram_cmd_width, dspin_ram_rsp_width> 1013 TsarIobClusterType; 1014 1015 TsarIobClusterType* clusters[x_size][y_size]; 967 1016 968 1017 #if USE_OPENMP … … 971 1020 #pragma omp for 972 1021 #endif 973 for(size_t i = 0; i < (XMAX * YMAX); i++) 1022 1023 for(size_t i = 0; i < (x_size * y_size); i++) 974 1024 { 975 size_t x = i / YMAX;976 size_t y = i % YMAX;1025 size_t x = i / y_size; 1026 size_t y = i % y_size; 977 1027 978 1028 #if USE_OPENMP … … 986 1036 std::ostringstream sc; 987 1037 sc << "cluster_" << x << "_" << y; 988 clusters[x][y] = new TsarIobCluster<vci_param_int, 989 vci_param_ext, 990 dspin_int_cmd_width, 991 dspin_int_rsp_width, 992 dspin_ram_cmd_width, 993 dspin_ram_rsp_width> 994 ( 995 sc.str().c_str(), 996 NB_PROCS_MAX, 997 NB_DMA_CHANNELS, 998 x, 999 y, 1000 XMAX, 1001 YMAX, 1002 1003 maptab_int, 1004 maptab_ram, 1005 maptab_iox, 1006 1007 x_width, 1008 y_width, 1009 vci_srcid_width - x_width - y_width, // l_id width, 1010 1011 INT_MEMC_TGT_ID, 1012 INT_XICU_TGT_ID, 1013 INT_MDMA_TGT_ID, 1014 INT_IOBX_TGT_ID, 1015 1016 INT_PROC_INI_ID, 1017 INT_MDMA_INI_ID, 1018 INT_IOBX_INI_ID, 1019 1020 RAM_XRAM_TGT_ID, 1021 1022 RAM_MEMC_INI_ID, 1023 RAM_IOBX_INI_ID, 1024 1025 MEMC_WAYS, 1026 MEMC_SETS, 1027 L1_IWAYS, 1028 L1_ISETS, 1029 L1_DWAYS, 1030 L1_DSETS, 1031 XRAM_LATENCY, 1032 1033 loader, 1034 1035 frozen_cycles, 1036 debug_from, 1037 debug_ok and (cluster(x,y) == debug_memc_id), 1038 debug_ok and (cluster(x,y) == debug_proc_id), 1039 debug_ok and debug_iob 1040 ); 1038 1039 bool memc_debug = 1040 debug_ok && (cluster(x,y) == debug_memc_id); 1041 bool proc_debug = 1042 debug_ok && (cluster(x,y) == (debug_proc_id / nb_procs)); 1043 1044 TsarIobClusterType::ClusterParams params = { 1045 .insname = sc.str().c_str(), 1046 .nb_procs = nb_procs, 1047 .nb_dmas = nb_dma_channels, 1048 .x_id = x, 1049 .y_id = y, 1050 .x_size = x_size, 1051 .y_size = y_size, 1052 .mt_int = maptab_int, 1053 .mt_ext = maptab_ram, 1054 .mt_iox = maptab_iox, 1055 .x_width = X_WIDTH, 1056 .y_width = Y_WIDTH, 1057 .l_width = vci_srcid_width - X_WIDTH - Y_WIDTH, 1058 .int_memc_tgtid = INT_MEMC_TGT_ID, 1059 .int_xicu_tgtid = INT_XICU_TGT_ID, 1060 .int_mdma_tgtid = INT_MDMA_TGT_ID, 1061 .int_iobx_tgtid = INT_IOBX_TGT_ID, 1062 .int_proc_srcid = INT_PROC_INI_ID, 1063 .int_mdma_srcid = INT_MDMA_INI_ID, 1064 .int_iobx_srcid = INT_IOBX_INI_ID, 1065 .ext_xram_tgtid = RAM_XRAM_TGT_ID, 1066 .ext_memc_srcid = RAM_MEMC_INI_ID, 1067 .ext_iobx_srcid = RAM_IOBX_INI_ID, 1068 .memc_ways = MEMC_WAYS, 1069 .memc_sets = MEMC_SETS, 1070 .l1_i_ways = L1_IWAYS, 1071 .l1_i_sets = L1_ISETS, 1072 .l1_d_ways = L1_DWAYS, 1073 .l1_d_sets = L1_DSETS, 1074 .xram_latency = XRAM_LATENCY, 1075 .loader = loader, 1076 .frozen_cycles = frozen_cycles, 1077 .debug_start_cycle = debug_from, 1078 .memc_debug_ok = memc_debug, 1079 .proc_debug_ok = proc_debug, 1080 .iob_debug_ok = debug_ok and debug_iob 1081 }; 1082 1083 clusters[x][y] = new TsarIobClusterType(params); 1041 1084 1042 1085 #if USE_OPENMP … … 1050 1093 std::cout << std::endl; 1051 1094 1052 /////////////////////////////////////////////////////////////////////////// ////1053 // Net-list 1054 /////////////////////////////////////////////////////////////////////////// ////1095 /////////////////////////////////////////////////////////////////////////// 1096 // Net-list 1097 /////////////////////////////////////////////////////////////////////////// 1055 1098 1056 1099 // IOX network connexion 1057 iox_network->p_clk 1058 iox_network->p_resetn 1059 iox_network->p_to_ini[IOX_IOB0_INI_ID] 1060 iox_network->p_to_ini[IOX_IOB1_INI_ID] 1061 iox_network->p_to_ini[IOX_BDEV_INI_ID] 1062 iox_network->p_to_ini[IOX_CDMA_INI_ID] 1063 iox_network->p_to_tgt[IOX_IOB0_TGT_ID] 1064 iox_network->p_to_tgt[IOX_IOB1_TGT_ID] 1065 iox_network->p_to_tgt[IOX_MTTY_TGT_ID] 1066 iox_network->p_to_tgt[IOX_FBUF_TGT_ID] 1067 iox_network->p_to_tgt[IOX_MNIC_TGT_ID] 1068 iox_network->p_to_tgt[IOX_BROM_TGT_ID] 1069 iox_network->p_to_tgt[IOX_BDEV_TGT_ID] 1070 iox_network->p_to_tgt[IOX_CDMA_TGT_ID] 1100 iox_network->p_clk (signal_clk); 1101 iox_network->p_resetn (signal_resetn); 1102 iox_network->p_to_ini[IOX_IOB0_INI_ID] (signal_vci_ini_iob0); 1103 iox_network->p_to_ini[IOX_IOB1_INI_ID] (signal_vci_ini_iob1); 1104 iox_network->p_to_ini[IOX_BDEV_INI_ID] (signal_vci_ini_bdev); 1105 iox_network->p_to_ini[IOX_CDMA_INI_ID] (signal_vci_ini_cdma); 1106 iox_network->p_to_tgt[IOX_IOB0_TGT_ID] (signal_vci_tgt_iob0); 1107 iox_network->p_to_tgt[IOX_IOB1_TGT_ID] (signal_vci_tgt_iob1); 1108 iox_network->p_to_tgt[IOX_MTTY_TGT_ID] (signal_vci_tgt_mtty); 1109 iox_network->p_to_tgt[IOX_FBUF_TGT_ID] (signal_vci_tgt_fbuf); 1110 iox_network->p_to_tgt[IOX_MNIC_TGT_ID] (signal_vci_tgt_mnic); 1111 iox_network->p_to_tgt[IOX_BROM_TGT_ID] (signal_vci_tgt_brom); 1112 iox_network->p_to_tgt[IOX_BDEV_TGT_ID] (signal_vci_tgt_bdev); 1113 iox_network->p_to_tgt[IOX_CDMA_TGT_ID] (signal_vci_tgt_cdma); 1071 1114 1072 1115 // BDEV connexion 1073 bdev->p_clk(signal_clk);1074 bdev->p_resetn 1075 bdev->p_irq 1116 bdev->p_clk (signal_clk); 1117 bdev->p_resetn (signal_resetn); 1118 bdev->p_irq (signal_irq_bdev); 1076 1119 1077 1120 // For AHCI 1078 // bdev->p_channel_irq[0] 1079 1080 bdev->p_vci_target 1081 bdev->p_vci_initiator 1121 // bdev->p_channel_irq[0] (signal_irq_bdev); 1122 1123 bdev->p_vci_target (signal_vci_tgt_bdev); 1124 bdev->p_vci_initiator (signal_vci_ini_bdev); 1082 1125 1083 1126 std::cout << " - BDEV connected" << std::endl; 1084 1127 1085 1128 // FBUF connexion 1086 fbuf->p_clk 1087 fbuf->p_resetn 1088 fbuf->p_vci 1129 fbuf->p_clk (signal_clk); 1130 fbuf->p_resetn (signal_resetn); 1131 fbuf->p_vci (signal_vci_tgt_fbuf); 1089 1132 1090 1133 std::cout << " - FBUF connected" << std::endl; 1091 1134 1092 1135 // MNIC connexion 1093 mnic->p_clk 1094 mnic->p_resetn 1095 mnic->p_vci 1096 for ( size_t i=0 ; i< NB_NIC_CHANNELS; i++ )1136 mnic->p_clk (signal_clk); 1137 mnic->p_resetn (signal_resetn); 1138 mnic->p_vci (signal_vci_tgt_mnic); 1139 for ( size_t i=0 ; i<nb_nic_channels ; i++ ) 1097 1140 { 1098 mnic->p_rx_irq[i] 1099 mnic->p_tx_irq[i] 1141 mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]); 1142 mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]); 1100 1143 } 1101 1144 … … 1103 1146 1104 1147 // BROM connexion 1105 brom->p_clk 1106 brom->p_resetn 1107 brom->p_vci 1148 brom->p_clk (signal_clk); 1149 brom->p_resetn (signal_resetn); 1150 brom->p_vci (signal_vci_tgt_brom); 1108 1151 1109 1152 std::cout << " - BROM connected" << std::endl; 1110 1153 1111 1154 // MTTY connexion 1112 mtty->p_clk 1113 mtty->p_resetn 1114 mtty->p_vci 1115 for ( size_t i=0 ; i< NB_TTY_CHANNELS; i++ )1155 mtty->p_clk (signal_clk); 1156 mtty->p_resetn (signal_resetn); 1157 mtty->p_vci (signal_vci_tgt_mtty); 1158 for ( size_t i=0 ; i<nb_tty_channels ; i++ ) 1116 1159 { 1117 mtty->p_irq[i] 1160 mtty->p_irq[i] (signal_irq_mtty[i]); 1118 1161 } 1119 1162 … … 1121 1164 1122 1165 // CDMA connexion 1123 cdma->p_clk 1124 cdma->p_resetn 1125 cdma->p_vci_target 1126 cdma->p_vci_initiator 1127 for ( size_t i=0 ; i<( NB_NIC_CHANNELS*2) ; i++)1166 cdma->p_clk (signal_clk); 1167 cdma->p_resetn (signal_resetn); 1168 cdma->p_vci_target (signal_vci_tgt_cdma); 1169 cdma->p_vci_initiator (signal_vci_ini_cdma); 1170 for ( size_t i=0 ; i<(nb_nic_channels*2) ; i++) 1128 1171 { 1129 cdma->p_irq[i] 1172 cdma->p_irq[i] (signal_irq_cdma[i]); 1130 1173 } 1131 1174 … … 1139 1182 // IRQ_BDEV -> IRQ[31] 1140 1183 1141 size_t mx = 16 + NB_TTY_CHANNELS;1184 size_t mx = 16 + nb_tty_channels; 1142 1185 for ( size_t n=0 ; n<32 ; n++ ) 1143 1186 { 1144 if ( n < 8 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false); 1145 1146 else if ( n < 10 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false); 1147 // else if ( n < 10 ) (*clusters[0][0]->p_irq[n]) (signal_irq_mnic_rx[n-8]); 1148 1149 else if ( n < 12 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false); 1150 // else if ( n < 12 ) (*clusters[0][0]->p_irq[n]) (signal_irq_mnic_tx[n-10]); 1151 1152 else if ( n < 16 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false); 1153 // else if ( n < 16 ) (*clusters[0][0]->p_irq[n]) (signal_irq_cdma[n-12]); 1154 1155 else if ( n < mx ) (*clusters[0][0]->p_irq[n]) (signal_irq_mtty[n-16]); 1156 else if ( n < 31 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false); 1157 1158 else (*clusters[0][0]->p_irq[n]) (signal_irq_bdev); 1187 if ( n < 8 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false); 1188 else if ( n < 10 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false); 1189 else if ( n < 12 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false); 1190 else if ( n < 16 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false); 1191 else if ( n < mx ) (*clusters[0][0]->p_irq[n]) (signal_irq_mtty[n-16]); 1192 else if ( n < 31 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false); 1193 else (*clusters[0][0]->p_irq[n]) (signal_irq_bdev); 1159 1194 } 1160 1195 1161 1196 // IOB0 cluster connexion to IOX network 1162 (*clusters[0][0]->p_vci_iob_iox_ini) 1163 (*clusters[0][0]->p_vci_iob_iox_tgt) 1197 (*clusters[0][0]->p_vci_iob_iox_ini) (signal_vci_ini_iob0); 1198 (*clusters[0][0]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob0); 1164 1199 1165 1200 // IOB1 cluster connexion to IOX network 1166 (*clusters[ XMAX-1][YMAX-1]->p_vci_iob_iox_ini)(signal_vci_ini_iob1);1167 (*clusters[ XMAX-1][YMAX-1]->p_vci_iob_iox_tgt)(signal_vci_tgt_iob1);1201 (*clusters[x_size-1][y_size-1]->p_vci_iob_iox_ini) (signal_vci_ini_iob1); 1202 (*clusters[x_size-1][y_size-1]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob1); 1168 1203 1169 1204 // All clusters Clock & RESET connexions 1170 for ( size_t x = 0; x < ( XMAX); x++ )1205 for ( size_t x = 0; x < (x_size); x++ ) 1171 1206 { 1172 for (size_t y = 0; y < YMAX; y++)1207 for (size_t y = 0; y < y_size; y++) 1173 1208 { 1174 clusters[x][y]->p_clk 1175 clusters[x][y]->p_resetn 1209 clusters[x][y]->p_clk (signal_clk); 1210 clusters[x][y]->p_resetn (signal_resetn); 1176 1211 } 1177 1212 } 1178 1213 1214 const int& NORTH = VirtualDspinRouter<dspin_int_cmd_width>::NORTH; 1215 const int& SOUTH = VirtualDspinRouter<dspin_int_cmd_width>::SOUTH; 1216 const int& EAST = VirtualDspinRouter<dspin_int_cmd_width>::EAST; 1217 const int& WEST = VirtualDspinRouter<dspin_int_cmd_width>::WEST; 1218 1179 1219 // Inter Clusters horizontal connections 1180 if ( XMAX> 1)1220 if (x_size > 1) 1181 1221 { 1182 for (size_t x = 0; x < ( XMAX-1); x++)1222 for (size_t x = 0; x < (x_size-1); x++) 1183 1223 { 1184 for (size_t y = 0; y < YMAX; y++)1224 for (size_t y = 0; y < y_size; y++) 1185 1225 { 1186 1226 for (size_t k = 0; k < 3; k++) 1187 1227 { 1188 clusters[x][y]->p_dspin_int_cmd_out[EAST][k] (signal_dspin_int_cmd_h_inc[x][y][k]); 1189 clusters[x+1][y]->p_dspin_int_cmd_in[WEST][k] (signal_dspin_int_cmd_h_inc[x][y][k]); 1190 clusters[x][y]->p_dspin_int_cmd_in[EAST][k] (signal_dspin_int_cmd_h_dec[x][y][k]); 1191 clusters[x+1][y]->p_dspin_int_cmd_out[WEST][k] (signal_dspin_int_cmd_h_dec[x][y][k]); 1228 clusters[x][y]->p_dspin_int_cmd_out[EAST][k]( 1229 signal_dspin_int_cmd_h_inc[x][y][k]); 1230 clusters[x+1][y]->p_dspin_int_cmd_in[WEST][k]( 1231 signal_dspin_int_cmd_h_inc[x][y][k]); 1232 clusters[x][y]->p_dspin_int_cmd_in[EAST][k]( 1233 signal_dspin_int_cmd_h_dec[x][y][k]); 1234 clusters[x+1][y]->p_dspin_int_cmd_out[WEST][k]( 1235 signal_dspin_int_cmd_h_dec[x][y][k]); 1192 1236 } 1193 1237 1194 1238 for (size_t k = 0; k < 2; k++) 1195 1239 { 1196 clusters[x][y]->p_dspin_int_rsp_out[EAST][k] (signal_dspin_int_rsp_h_inc[x][y][k]); 1197 clusters[x+1][y]->p_dspin_int_rsp_in[WEST][k] (signal_dspin_int_rsp_h_inc[x][y][k]); 1198 clusters[x][y]->p_dspin_int_rsp_in[EAST][k] (signal_dspin_int_rsp_h_dec[x][y][k]); 1199 clusters[x+1][y]->p_dspin_int_rsp_out[WEST][k] (signal_dspin_int_rsp_h_dec[x][y][k]); 1240 clusters[x][y]->p_dspin_int_rsp_out[EAST][k]( 1241 signal_dspin_int_rsp_h_inc[x][y][k]); 1242 clusters[x+1][y]->p_dspin_int_rsp_in[WEST][k]( 1243 signal_dspin_int_rsp_h_inc[x][y][k]); 1244 clusters[x][y]->p_dspin_int_rsp_in[EAST][k]( 1245 signal_dspin_int_rsp_h_dec[x][y][k]); 1246 clusters[x+1][y]->p_dspin_int_rsp_out[WEST][k]( 1247 signal_dspin_int_rsp_h_dec[x][y][k]); 1200 1248 } 1201 1249 1202 clusters[x][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_ram_cmd_h_inc[x][y]); 1203 clusters[x+1][y]->p_dspin_ram_cmd_in[WEST] (signal_dspin_ram_cmd_h_inc[x][y]); 1204 clusters[x][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_ram_cmd_h_dec[x][y]); 1205 clusters[x+1][y]->p_dspin_ram_cmd_out[WEST] (signal_dspin_ram_cmd_h_dec[x][y]); 1206 clusters[x][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_ram_rsp_h_inc[x][y]); 1207 clusters[x+1][y]->p_dspin_ram_rsp_in[WEST] (signal_dspin_ram_rsp_h_inc[x][y]); 1208 clusters[x][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_ram_rsp_h_dec[x][y]); 1209 clusters[x+1][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_ram_rsp_h_dec[x][y]); 1250 clusters[x][y]->p_dspin_ram_cmd_out[EAST]( 1251 signal_dspin_ram_cmd_h_inc[x][y]); 1252 clusters[x+1][y]->p_dspin_ram_cmd_in[WEST]( 1253 signal_dspin_ram_cmd_h_inc[x][y]); 1254 clusters[x][y]->p_dspin_ram_cmd_in[EAST]( 1255 signal_dspin_ram_cmd_h_dec[x][y]); 1256 clusters[x+1][y]->p_dspin_ram_cmd_out[WEST]( 1257 signal_dspin_ram_cmd_h_dec[x][y]); 1258 clusters[x][y]->p_dspin_ram_rsp_out[EAST]( 1259 signal_dspin_ram_rsp_h_inc[x][y]); 1260 clusters[x+1][y]->p_dspin_ram_rsp_in[WEST]( 1261 signal_dspin_ram_rsp_h_inc[x][y]); 1262 clusters[x][y]->p_dspin_ram_rsp_in[EAST]( 1263 signal_dspin_ram_rsp_h_dec[x][y]); 1264 clusters[x+1][y]->p_dspin_ram_rsp_out[WEST]( 1265 signal_dspin_ram_rsp_h_dec[x][y]); 1210 1266 } 1211 1267 } 1212 1268 } 1213 1269 1214 std::cout << std::endl << "Horizontal connections established" << std::endl; 1270 std::cout << std::endl << "Horizontal connections established" 1271 << std::endl; 1215 1272 1216 1273 // Inter Clusters vertical connections 1217 if ( YMAX > 1)1274 if (y_size > 1) 1218 1275 { 1219 for (size_t y = 0; y < ( YMAX-1); y++)1276 for (size_t y = 0; y < (y_size-1); y++) 1220 1277 { 1221 for (size_t x = 0; x < XMAX; x++)1278 for (size_t x = 0; x < x_size; x++) 1222 1279 { 1223 1280 for (size_t k = 0; k < 3; k++) 1224 1281 { 1225 clusters[x][y]->p_dspin_int_cmd_out[NORTH][k] (signal_dspin_int_cmd_v_inc[x][y][k]); 1226 clusters[x][y+1]->p_dspin_int_cmd_in[SOUTH][k] (signal_dspin_int_cmd_v_inc[x][y][k]); 1227 clusters[x][y]->p_dspin_int_cmd_in[NORTH][k] (signal_dspin_int_cmd_v_dec[x][y][k]); 1228 clusters[x][y+1]->p_dspin_int_cmd_out[SOUTH][k] (signal_dspin_int_cmd_v_dec[x][y][k]); 1282 clusters[x][y]->p_dspin_int_cmd_out[NORTH][k]( 1283 signal_dspin_int_cmd_v_inc[x][y][k]); 1284 clusters[x][y+1]->p_dspin_int_cmd_in[SOUTH][k]( 1285 signal_dspin_int_cmd_v_inc[x][y][k]); 1286 clusters[x][y]->p_dspin_int_cmd_in[NORTH][k]( 1287 signal_dspin_int_cmd_v_dec[x][y][k]); 1288 clusters[x][y+1]->p_dspin_int_cmd_out[SOUTH][k]( 1289 signal_dspin_int_cmd_v_dec[x][y][k]); 1229 1290 } 1230 1291 1231 1292 for (size_t k = 0; k < 2; k++) 1232 1293 { 1233 clusters[x][y]->p_dspin_int_rsp_out[NORTH][k] (signal_dspin_int_rsp_v_inc[x][y][k]); 1234 clusters[x][y+1]->p_dspin_int_rsp_in[SOUTH][k] (signal_dspin_int_rsp_v_inc[x][y][k]); 1235 clusters[x][y]->p_dspin_int_rsp_in[NORTH][k] (signal_dspin_int_rsp_v_dec[x][y][k]); 1236 clusters[x][y+1]->p_dspin_int_rsp_out[SOUTH][k] (signal_dspin_int_rsp_v_dec[x][y][k]); 1294 clusters[x][y]->p_dspin_int_rsp_out[NORTH][k]( 1295 signal_dspin_int_rsp_v_inc[x][y][k]); 1296 clusters[x][y+1]->p_dspin_int_rsp_in[SOUTH][k]( 1297 signal_dspin_int_rsp_v_inc[x][y][k]); 1298 clusters[x][y]->p_dspin_int_rsp_in[NORTH][k]( 1299 signal_dspin_int_rsp_v_dec[x][y][k]); 1300 clusters[x][y+1]->p_dspin_int_rsp_out[SOUTH][k]( 1301 signal_dspin_int_rsp_v_dec[x][y][k]); 1237 1302 } 1238 1303 1239 clusters[x][y]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_ram_cmd_v_inc[x][y]); 1240 clusters[x][y+1]->p_dspin_ram_cmd_in[SOUTH] (signal_dspin_ram_cmd_v_inc[x][y]); 1241 clusters[x][y]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_ram_cmd_v_dec[x][y]); 1242 clusters[x][y+1]->p_dspin_ram_cmd_out[SOUTH] (signal_dspin_ram_cmd_v_dec[x][y]); 1243 clusters[x][y]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_ram_rsp_v_inc[x][y]); 1244 clusters[x][y+1]->p_dspin_ram_rsp_in[SOUTH] (signal_dspin_ram_rsp_v_inc[x][y]); 1245 clusters[x][y]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_ram_rsp_v_dec[x][y]); 1246 clusters[x][y+1]->p_dspin_ram_rsp_out[SOUTH] (signal_dspin_ram_rsp_v_dec[x][y]); 1304 clusters[x][y]->p_dspin_ram_cmd_out[NORTH]( 1305 signal_dspin_ram_cmd_v_inc[x][y]); 1306 clusters[x][y+1]->p_dspin_ram_cmd_in[SOUTH]( 1307 signal_dspin_ram_cmd_v_inc[x][y]); 1308 clusters[x][y]->p_dspin_ram_cmd_in[NORTH]( 1309 signal_dspin_ram_cmd_v_dec[x][y]); 1310 clusters[x][y+1]->p_dspin_ram_cmd_out[SOUTH]( 1311 signal_dspin_ram_cmd_v_dec[x][y]); 1312 clusters[x][y]->p_dspin_ram_rsp_out[NORTH]( 1313 signal_dspin_ram_rsp_v_inc[x][y]); 1314 clusters[x][y+1]->p_dspin_ram_rsp_in[SOUTH]( 1315 signal_dspin_ram_rsp_v_inc[x][y]); 1316 clusters[x][y]->p_dspin_ram_rsp_in[NORTH]( 1317 signal_dspin_ram_rsp_v_dec[x][y]); 1318 clusters[x][y+1]->p_dspin_ram_rsp_out[SOUTH]( 1319 signal_dspin_ram_rsp_v_dec[x][y]); 1247 1320 } 1248 1321 } … … 1252 1325 1253 1326 // East & West boundary cluster connections 1254 for (size_t y = 0; y < YMAX; y++)1327 for (size_t y = 0; y < y_size; y++) 1255 1328 { 1256 1329 for (size_t k = 0; k < 3; k++) 1257 1330 { 1258 clusters[0][y]->p_dspin_int_cmd_in[WEST][k] (signal_dspin_false_int_cmd_in[0][y][WEST][k]); 1259 clusters[0][y]->p_dspin_int_cmd_out[WEST][k] (signal_dspin_false_int_cmd_out[0][y][WEST][k]); 1260 clusters[XMAX-1][y]->p_dspin_int_cmd_in[EAST][k] (signal_dspin_false_int_cmd_in[XMAX-1][y][EAST][k]); 1261 clusters[XMAX-1][y]->p_dspin_int_cmd_out[EAST][k] (signal_dspin_false_int_cmd_out[XMAX-1][y][EAST][k]); 1331 clusters[0][y]->p_dspin_int_cmd_in[WEST][k]( 1332 signal_dspin_false_int_cmd_in[0][y][WEST][k]); 1333 clusters[0][y]->p_dspin_int_cmd_out[WEST][k]( 1334 signal_dspin_false_int_cmd_out[0][y][WEST][k]); 1335 clusters[x_size-1][y]->p_dspin_int_cmd_in[EAST][k]( 1336 signal_dspin_false_int_cmd_in[x_size-1][y][EAST][k]); 1337 clusters[x_size-1][y]->p_dspin_int_cmd_out[EAST][k]( 1338 signal_dspin_false_int_cmd_out[x_size-1][y][EAST][k]); 1262 1339 } 1263 1340 1264 1341 for (size_t k = 0; k < 2; k++) 1265 1342 { 1266 clusters[0][y]->p_dspin_int_rsp_in[WEST][k] (signal_dspin_false_int_rsp_in[0][y][WEST][k]); 1267 clusters[0][y]->p_dspin_int_rsp_out[WEST][k] (signal_dspin_false_int_rsp_out[0][y][WEST][k]); 1268 clusters[XMAX-1][y]->p_dspin_int_rsp_in[EAST][k] (signal_dspin_false_int_rsp_in[XMAX-1][y][EAST][k]); 1269 clusters[XMAX-1][y]->p_dspin_int_rsp_out[EAST][k] (signal_dspin_false_int_rsp_out[XMAX-1][y][EAST][k]); 1343 clusters[0][y]->p_dspin_int_rsp_in[WEST][k]( 1344 signal_dspin_false_int_rsp_in[0][y][WEST][k]); 1345 clusters[0][y]->p_dspin_int_rsp_out[WEST][k]( 1346 signal_dspin_false_int_rsp_out[0][y][WEST][k]); 1347 clusters[x_size-1][y]->p_dspin_int_rsp_in[EAST][k]( 1348 signal_dspin_false_int_rsp_in[x_size-1][y][EAST][k]); 1349 clusters[x_size-1][y]->p_dspin_int_rsp_out[EAST][k]( 1350 signal_dspin_false_int_rsp_out[x_size-1][y][EAST][k]); 1270 1351 } 1271 1352 1272 if( y == 0 ) // handling IOB to RAM network connection in cluster_iob0 1353 // handling IOB to RAM network connection in cluster_iob0 1354 if( y == 0 ) 1273 1355 { 1274 (*clusters[0][0]->p_dspin_iob_cmd_out) (signal_dspin_cmd_iob0_loopback); 1275 clusters[0][0]->p_dspin_ram_cmd_in[WEST] (signal_dspin_cmd_iob0_loopback); 1276 1277 clusters[0][0]->p_dspin_ram_cmd_out[WEST] (signal_dspin_false_ram_cmd_out[0][0][WEST]); 1278 clusters[0][0]->p_dspin_ram_rsp_in[WEST] (signal_dspin_false_ram_rsp_in[0][0][WEST]); 1279 1280 clusters[0][0]->p_dspin_ram_rsp_out[WEST] (signal_dspin_rsp_iob0_loopback); 1281 (*clusters[0][0]->p_dspin_iob_rsp_in) (signal_dspin_rsp_iob0_loopback); 1282 1356 (*clusters[0][0]->p_dspin_iob_cmd_out)( 1357 signal_dspin_cmd_iob0_loopback); 1358 clusters[0][0]->p_dspin_ram_cmd_in[WEST]( 1359 signal_dspin_cmd_iob0_loopback); 1360 clusters[0][0]->p_dspin_ram_cmd_out[WEST]( 1361 signal_dspin_false_ram_cmd_out[0][0][WEST]); 1362 clusters[0][0]->p_dspin_ram_rsp_in[WEST]( 1363 signal_dspin_false_ram_rsp_in[0][0][WEST]); 1364 clusters[0][0]->p_dspin_ram_rsp_out[WEST]( 1365 signal_dspin_rsp_iob0_loopback); 1366 (*clusters[0][0]->p_dspin_iob_rsp_in)( 1367 signal_dspin_rsp_iob0_loopback); 1283 1368 } 1284 1369 else 1285 1370 { 1286 clusters[0][y]->p_dspin_ram_cmd_in[WEST] (signal_dspin_false_ram_cmd_in[0][y][WEST]); 1287 clusters[0][y]->p_dspin_ram_cmd_out[WEST] (signal_dspin_false_ram_cmd_out[0][y][WEST]); 1288 clusters[0][y]->p_dspin_ram_rsp_in[WEST] (signal_dspin_false_ram_rsp_in[0][y][WEST]); 1289 clusters[0][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_false_ram_rsp_out[0][y][WEST]); 1371 clusters[0][y]->p_dspin_ram_cmd_in[WEST]( 1372 signal_dspin_false_ram_cmd_in[0][y][WEST]); 1373 clusters[0][y]->p_dspin_ram_cmd_out[WEST]( 1374 signal_dspin_false_ram_cmd_out[0][y][WEST]); 1375 clusters[0][y]->p_dspin_ram_rsp_in[WEST]( 1376 signal_dspin_false_ram_rsp_in[0][y][WEST]); 1377 clusters[0][y]->p_dspin_ram_rsp_out[WEST]( 1378 signal_dspin_false_ram_rsp_out[0][y][WEST]); 1290 1379 } 1291 1380 1292 if( y == YMAX-1 ) // handling IOB to RAM network connection in cluster_iob1 1381 // handling IOB to RAM network connection in cluster_iob1 1382 if( y == y_size-1 ) 1293 1383 { 1294 (*clusters[XMAX-1][YMAX-1]->p_dspin_iob_cmd_out) (signal_dspin_cmd_iob1_loopback); 1295 clusters[XMAX-1][YMAX-1]->p_dspin_ram_cmd_in[EAST] (signal_dspin_cmd_iob1_loopback); 1296 1297 clusters[XMAX-1][YMAX-1]->p_dspin_ram_cmd_out[EAST] (signal_dspin_false_ram_cmd_out[XMAX-1][YMAX-1][EAST]); 1298 clusters[XMAX-1][YMAX-1]->p_dspin_ram_rsp_in[EAST] (signal_dspin_false_ram_rsp_in[XMAX-1][YMAX-1][EAST]); 1299 1300 clusters[XMAX-1][YMAX-1]->p_dspin_ram_rsp_out[EAST] (signal_dspin_rsp_iob1_loopback); 1301 (*clusters[XMAX-1][YMAX-1]->p_dspin_iob_rsp_in) (signal_dspin_rsp_iob1_loopback); 1384 (*clusters[x_size-1][y_size-1]->p_dspin_iob_cmd_out)( 1385 signal_dspin_cmd_iob1_loopback); 1386 clusters[x_size-1][y_size-1]->p_dspin_ram_cmd_in[EAST]( 1387 signal_dspin_cmd_iob1_loopback); 1388 1389 clusters[x_size-1][y_size-1]->p_dspin_ram_cmd_out[EAST]( 1390 signal_dspin_false_ram_cmd_out[x_size-1][y_size-1][EAST]); 1391 clusters[x_size-1][y_size-1]->p_dspin_ram_rsp_in[EAST]( 1392 signal_dspin_false_ram_rsp_in[x_size-1][y_size-1][EAST]); 1393 1394 clusters[x_size-1][y_size-1]->p_dspin_ram_rsp_out[EAST]( 1395 signal_dspin_rsp_iob1_loopback); 1396 (*clusters[x_size-1][y_size-1]->p_dspin_iob_rsp_in)( 1397 signal_dspin_rsp_iob1_loopback); 1302 1398 } 1303 1399 else 1304 1400 { 1305 clusters[XMAX-1][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_false_ram_cmd_in[XMAX-1][y][EAST]); 1306 clusters[XMAX-1][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_false_ram_cmd_out[XMAX-1][y][EAST]); 1307 clusters[XMAX-1][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_false_ram_rsp_in[XMAX-1][y][EAST]); 1308 clusters[XMAX-1][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_false_ram_rsp_out[XMAX-1][y][EAST]); 1401 clusters[x_size-1][y]->p_dspin_ram_cmd_in[EAST]( 1402 signal_dspin_false_ram_cmd_in[x_size-1][y][EAST]); 1403 clusters[x_size-1][y]->p_dspin_ram_cmd_out[EAST]( 1404 signal_dspin_false_ram_cmd_out[x_size-1][y][EAST]); 1405 clusters[x_size-1][y]->p_dspin_ram_rsp_in[EAST]( 1406 signal_dspin_false_ram_rsp_in[x_size-1][y][EAST]); 1407 clusters[x_size-1][y]->p_dspin_ram_rsp_out[EAST]( 1408 signal_dspin_false_ram_rsp_out[x_size-1][y][EAST]); 1309 1409 } 1310 1410 } … … 1313 1413 1314 1414 // North & South boundary clusters connections 1315 for (size_t x = 0; x < XMAX; x++)1415 for (size_t x = 0; x < x_size; x++) 1316 1416 { 1317 1417 for (size_t k = 0; k < 3; k++) 1318 1418 { 1319 clusters[x][0]->p_dspin_int_cmd_in[SOUTH][k] (signal_dspin_false_int_cmd_in[x][0][SOUTH][k]); 1320 clusters[x][0]->p_dspin_int_cmd_out[SOUTH][k] (signal_dspin_false_int_cmd_out[x][0][SOUTH][k]); 1321 clusters[x][YMAX-1]->p_dspin_int_cmd_in[NORTH][k] (signal_dspin_false_int_cmd_in[x][YMAX-1][NORTH][k]); 1322 clusters[x][YMAX-1]->p_dspin_int_cmd_out[NORTH][k] (signal_dspin_false_int_cmd_out[x][YMAX-1][NORTH][k]); 1419 clusters[x][0]->p_dspin_int_cmd_in[SOUTH][k]( 1420 signal_dspin_false_int_cmd_in[x][0][SOUTH][k]); 1421 clusters[x][0]->p_dspin_int_cmd_out[SOUTH][k]( 1422 signal_dspin_false_int_cmd_out[x][0][SOUTH][k]); 1423 clusters[x][y_size-1]->p_dspin_int_cmd_in[NORTH][k]( 1424 signal_dspin_false_int_cmd_in[x][y_size-1][NORTH][k]); 1425 clusters[x][y_size-1]->p_dspin_int_cmd_out[NORTH][k]( 1426 signal_dspin_false_int_cmd_out[x][y_size-1][NORTH][k]); 1323 1427 } 1324 1428 1325 1429 for (size_t k = 0; k < 2; k++) 1326 1430 { 1327 clusters[x][0]->p_dspin_int_rsp_in[SOUTH][k] (signal_dspin_false_int_rsp_in[x][0][SOUTH][k]); 1328 clusters[x][0]->p_dspin_int_rsp_out[SOUTH][k] (signal_dspin_false_int_rsp_out[x][0][SOUTH][k]); 1329 clusters[x][YMAX-1]->p_dspin_int_rsp_in[NORTH][k] (signal_dspin_false_int_rsp_in[x][YMAX-1][NORTH][k]); 1330 clusters[x][YMAX-1]->p_dspin_int_rsp_out[NORTH][k] (signal_dspin_false_int_rsp_out[x][YMAX-1][NORTH][k]); 1431 clusters[x][0]->p_dspin_int_rsp_in[SOUTH][k]( 1432 signal_dspin_false_int_rsp_in[x][0][SOUTH][k]); 1433 clusters[x][0]->p_dspin_int_rsp_out[SOUTH][k]( 1434 signal_dspin_false_int_rsp_out[x][0][SOUTH][k]); 1435 clusters[x][y_size-1]->p_dspin_int_rsp_in[NORTH][k]( 1436 signal_dspin_false_int_rsp_in[x][y_size-1][NORTH][k]); 1437 clusters[x][y_size-1]->p_dspin_int_rsp_out[NORTH][k]( 1438 signal_dspin_false_int_rsp_out[x][y_size-1][NORTH][k]); 1331 1439 } 1332 1440 1333 clusters[x][0]->p_dspin_ram_cmd_in[SOUTH] (signal_dspin_false_ram_cmd_in[x][0][SOUTH]); 1334 clusters[x][0]->p_dspin_ram_cmd_out[SOUTH] (signal_dspin_false_ram_cmd_out[x][0][SOUTH]); 1335 clusters[x][0]->p_dspin_ram_rsp_in[SOUTH] (signal_dspin_false_ram_rsp_in[x][0][SOUTH]); 1336 clusters[x][0]->p_dspin_ram_rsp_out[SOUTH] (signal_dspin_false_ram_rsp_out[x][0][SOUTH]); 1337 1338 clusters[x][YMAX-1]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_false_ram_cmd_in[x][YMAX-1][NORTH]); 1339 clusters[x][YMAX-1]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_false_ram_cmd_out[x][YMAX-1][NORTH]); 1340 clusters[x][YMAX-1]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_false_ram_rsp_in[x][YMAX-1][NORTH]); 1341 clusters[x][YMAX-1]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_false_ram_rsp_out[x][YMAX-1][NORTH]); 1441 clusters[x][0]->p_dspin_ram_cmd_in[SOUTH]( 1442 signal_dspin_false_ram_cmd_in[x][0][SOUTH]); 1443 clusters[x][0]->p_dspin_ram_cmd_out[SOUTH]( 1444 signal_dspin_false_ram_cmd_out[x][0][SOUTH]); 1445 clusters[x][0]->p_dspin_ram_rsp_in[SOUTH]( 1446 signal_dspin_false_ram_rsp_in[x][0][SOUTH]); 1447 clusters[x][0]->p_dspin_ram_rsp_out[SOUTH]( 1448 signal_dspin_false_ram_rsp_out[x][0][SOUTH]); 1449 1450 clusters[x][y_size-1]->p_dspin_ram_cmd_in[NORTH]( 1451 signal_dspin_false_ram_cmd_in[x][y_size-1][NORTH]); 1452 clusters[x][y_size-1]->p_dspin_ram_cmd_out[NORTH]( 1453 signal_dspin_false_ram_cmd_out[x][y_size-1][NORTH]); 1454 clusters[x][y_size-1]->p_dspin_ram_rsp_in[NORTH]( 1455 signal_dspin_false_ram_rsp_in[x][y_size-1][NORTH]); 1456 clusters[x][y_size-1]->p_dspin_ram_rsp_out[NORTH]( 1457 signal_dspin_false_ram_rsp_out[x][y_size-1][NORTH]); 1342 1458 } 1343 1459 1344 std::cout << "North & South boundaries established" << std::endl << std::endl; 1460 std::cout << "North & South boundaries established" << std::endl 1461 << std::endl; 1345 1462 1346 1463 //////////////////////////////////////////////////////// … … 1355 1472 1356 1473 // network boundaries signals 1357 for (size_t x = 0; x < XMAX; x++)1474 for (size_t x = 0; x < x_size ; x++) 1358 1475 { 1359 for (size_t y = 0; y < YMAX; y++)1476 for (size_t y = 0; y < y_size ; y++) 1360 1477 { 1361 1478 for (size_t a = 0; a < 4; a++) … … 1363 1480 for (size_t k = 0; k < 3; k++) 1364 1481 { 1365 signal_dspin_false_int_cmd_in[x][y][a][k].write = false;1366 signal_dspin_false_int_cmd_in[x][y][a][k].read = true;1482 signal_dspin_false_int_cmd_in[x][y][a][k].write = false; 1483 signal_dspin_false_int_cmd_in[x][y][a][k].read = true; 1367 1484 signal_dspin_false_int_cmd_out[x][y][a][k].write = false; 1368 signal_dspin_false_int_cmd_out[x][y][a][k].read = true;1485 signal_dspin_false_int_cmd_out[x][y][a][k].read = true; 1369 1486 } 1370 1487 1371 1488 for (size_t k = 0; k < 2; k++) 1372 1489 { 1373 signal_dspin_false_int_rsp_in[x][y][a][k].write = false;1374 signal_dspin_false_int_rsp_in[x][y][a][k].read = true;1490 signal_dspin_false_int_rsp_in[x][y][a][k].write = false; 1491 signal_dspin_false_int_rsp_in[x][y][a][k].read = true; 1375 1492 signal_dspin_false_int_rsp_out[x][y][a][k].write = false; 1376 signal_dspin_false_int_rsp_out[x][y][a][k].read = true;1493 signal_dspin_false_int_rsp_out[x][y][a][k].read = true; 1377 1494 } 1378 1495 1379 signal_dspin_false_ram_cmd_in[x][y][a].write = false;1380 signal_dspin_false_ram_cmd_in[x][y][a].read = true;1496 signal_dspin_false_ram_cmd_in[x][y][a].write = false; 1497 signal_dspin_false_ram_cmd_in[x][y][a].read = true; 1381 1498 signal_dspin_false_ram_cmd_out[x][y][a].write = false; 1382 signal_dspin_false_ram_cmd_out[x][y][a].read = true;1383 1384 signal_dspin_false_ram_rsp_in[x][y][a].write = false;1385 signal_dspin_false_ram_rsp_in[x][y][a].read = true;1499 signal_dspin_false_ram_cmd_out[x][y][a].read = true; 1500 1501 signal_dspin_false_ram_rsp_in[x][y][a].write = false; 1502 signal_dspin_false_ram_rsp_in[x][y][a].read = true; 1386 1503 signal_dspin_false_ram_rsp_out[x][y][a].write = false; 1387 signal_dspin_false_ram_rsp_out[x][y][a].read = true;1504 signal_dspin_false_ram_rsp_out[x][y][a].read = true; 1388 1505 } 1389 1506 } … … 1402 1519 1403 1520 // Monitor a specific address for one XRAM 1404 // if (n == 3000000) clusters[0][0]->xram->start_monitor( 0x170000ULL , 64); 1521 // if (n == 3000000) 1522 // clusters[0][0]->xram->start_monitor( 0x170000ULL , 64); 1405 1523 1406 1524 if (debug_ok and (n > debug_from) and (n % debug_period == 0)) 1407 1525 { 1408 std::cout << "****************** cycle " << std::dec << n ; 1409 std::cout << " ************************************************" << std::endl; 1410 1411 // trace proc[debug_proc_id] 1526 std::cout << " ***********************" 1527 << " cycle " << std::dec << n 1528 << " ***********************" 1529 << std::endl; 1530 1531 // trace proc[debug_proc_id] 1412 1532 if ( debug_proc_id != 0xFFFFFFFF ) 1413 1533 { 1414 size_t l = debug_proc_id % NB_PROCS_MAX;1415 size_t cluster_xy = debug_proc_id / NB_PROCS_MAX;1416 size_t x = cluster_xy >> 4;1417 size_t y = cluster_xy & 0xF;1534 size_t l = debug_proc_id % nb_procs ; 1535 size_t cluster_xy = debug_proc_id / nb_procs ; 1536 size_t x = cluster_xy >> Y_WIDTH; 1537 size_t y = cluster_xy & ((1 << Y_WIDTH) - 1); 1418 1538 1419 1539 clusters[x][y]->proc[l]->print_trace(1); … … 1421 1541 std::ostringstream proc_signame; 1422 1542 proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; 1423 clusters[x][y]->signal_int_vci_ini_proc[l].print_trace(proc_signame.str()); 1543 clusters[x][y]->signal_int_vci_ini_proc[l].print_trace( 1544 proc_signame.str()); 1424 1545 1425 1546 clusters[x][y]->xicu->print_trace(l); … … 1427 1548 std::ostringstream xicu_signame; 1428 1549 xicu_signame << "[SIG]XICU_" << x << "_" << y; 1429 clusters[x][y]->signal_int_vci_tgt_xicu.print_trace(xicu_signame.str()); 1430 1431 if( clusters[x][y]->signal_proc_it[l].read() ) 1550 clusters[x][y]->signal_int_vci_tgt_xicu.print_trace( 1551 xicu_signame.str()); 1552 1553 if( clusters[x][y]->signal_proc_it[l].read() ) 1432 1554 std::cout << "### IRQ_PROC_" << std::dec 1433 << x << "_" << y << "_" << l << " ACTIVE" << std::endl; 1434 } 1555 << x << "_" << y << "_" << l 1556 << " ACTIVE" << std::endl; 1557 } 1435 1558 1436 1559 // trace INT network … … 1438 1561 // clusters[0][0]->int_xbar_rsp_d->print_trace(); 1439 1562 1440 // clusters[0][0]->signal_int_dspin_cmd_l2g_d.print_trace("[SIG] INT_CMD_L2G_D_0_0"); 1441 // clusters[0][0]->signal_int_dspin_rsp_g2l_d.print_trace("[SIG] INT_RSP_G2L_D_0_0"); 1563 // clusters[0][0]->signal_int_dspin_cmd_l2g_d.print_trace( 1564 // "[SIG] INT_CMD_L2G_D_0_0"); 1565 // clusters[0][0]->signal_int_dspin_rsp_g2l_d.print_trace( 1566 // "[SIG] INT_RSP_G2L_D_0_0"); 1442 1567 1443 1568 // clusters[0][0]->int_router_cmd->print_trace(0); … … 1447 1572 // clusters[0][1]->int_router_cmd->print_trace(0); 1448 1573 // clusters[0][1]->int_router_rsp->print_trace(0); 1449 1450 // clusters[0][1]->signal_int_dspin_cmd_g2l_d.print_trace("[SIG] INT_CMD_G2L_D_0_0"); 1451 // clusters[0][1]->signal_int_dspin_rsp_l2g_d.print_trace("[SIG] INT_RSP_L2G_D_0_0"); 1452 1574 1575 // clusters[0][1]->signal_int_dspin_cmd_g2l_d.print_trace( 1576 // "[SIG] INT_CMD_G2L_D_0_0"); 1577 // clusters[0][1]->signal_int_dspin_rsp_l2g_d.print_trace( 1578 // "[SIG] INT_RSP_L2G_D_0_0"); 1579 1453 1580 // clusters[0][1]->int_xbar_cmd_d->print_trace(); 1454 1581 // clusters[0][1]->int_xbar_rsp_d->print_trace(); 1455 1582 1456 // trace memc[debug_memc_id] 1583 // trace memc[debug_memc_id] 1457 1584 if ( debug_memc_id != 0xFFFFFFFF ) 1458 1585 { 1459 size_t x = debug_memc_id >> 4;1460 size_t y = debug_memc_id & 0xF;1461 1586 size_t x = debug_memc_id >> Y_WIDTH; 1587 size_t y = debug_memc_id & ((1 << Y_WIDTH) - 1); 1588 1462 1589 clusters[x][y]->memc->print_trace(0); 1463 1590 std::ostringstream smemc_tgt; 1464 1591 smemc_tgt << "[SIG]MEMC_TGT_" << x << "_" << y; 1465 clusters[x][y]->signal_int_vci_tgt_memc.print_trace(smemc_tgt.str()); 1592 clusters[x][y]->signal_int_vci_tgt_memc.print_trace( 1593 smemc_tgt.str()); 1466 1594 std::ostringstream smemc_ini; 1467 1595 smemc_ini << "[SIG]MEMC_INI_" << x << "_" << y; 1468 clusters[x][y]->signal_ram_vci_ini_memc.print_trace(smemc_ini.str()); 1596 clusters[x][y]->signal_ram_vci_ini_memc.print_trace( 1597 smemc_ini.str()); 1469 1598 clusters[x][y]->xram->print_trace(); 1470 1599 std::ostringstream sxram_tgt; 1471 1600 sxram_tgt << "[SIG]XRAM_TGT_" << x << "_" << y; 1472 clusters[x][y]->signal_ram_vci_tgt_xram.print_trace(sxram_tgt.str()); 1601 clusters[x][y]->signal_ram_vci_tgt_xram.print_trace( 1602 sxram_tgt.str()); 1473 1603 } 1474 1604 … … 1481 1611 // clusters[x][y]->ram_router_rsp->print_trace(); 1482 1612 // } 1483 1484 // trace iob, iox and external peripherals 1613 1614 // trace iob, iox and external peripherals 1485 1615 if ( debug_iob ) 1486 1616 { 1487 1617 clusters[0][0]->iob->print_trace(); 1488 clusters[0][0]->signal_int_vci_tgt_iobx.print_trace( "[SIG]IOB0_INT_TGT"); 1489 clusters[0][0]->signal_int_vci_ini_iobx.print_trace( "[SIG]IOB0_INT_INI"); 1490 clusters[0][0]->signal_ram_vci_ini_iobx.print_trace( "[SIG]IOB0_RAM_INI"); 1618 clusters[0][0]->signal_int_vci_tgt_iobx.print_trace( 1619 "[SIG]IOB0_INT_TGT"); 1620 clusters[0][0]->signal_int_vci_ini_iobx.print_trace( 1621 "[SIG]IOB0_INT_INI"); 1622 clusters[0][0]->signal_ram_vci_ini_iobx.print_trace( 1623 "[SIG]IOB0_RAM_INI"); 1491 1624 1492 1625 signal_vci_ini_iob0.print_trace("[SIG]IOB0_IOX_INI"); 1493 1626 signal_vci_tgt_iob0.print_trace("[SIG]IOB0_IOX_TGT"); 1494 1627 1495 // signal_dspin_cmd_iob0_loopback.print_trace("[SIG]IOB0_CMD_LOOPBACK"); 1496 // signal_dspin_rsp_iob0_loopback.print_trace("[SIG]IOB0_RSP_LOOPBACK"); 1628 // signal_dspin_cmd_iob0_loopback.print_trace( 1629 // "[SIG]IOB0_CMD_LOOPBACK"); 1630 // signal_dspin_rsp_iob0_loopback.print_trace( 1631 // "[SIG]IOB0_RSP_LOOPBACK"); 1497 1632 1498 1633 cdma->print_trace(); … … 1516 1651 1517 1652 // interrupts 1518 if (signal_irq_bdev) std::cout << "### IRQ_BDEV ACTIVATED" << std::endl; 1653 if (signal_irq_bdev) std::cout << "### IRQ_BDEV ACTIVATED" 1654 << std::endl; 1519 1655 } 1520 1656 } … … 1522 1658 sc_start(sc_core::sc_time(1, SC_NS)); 1523 1659 } 1524 return EXIT_SUCCESS; 1660 1661 delete iox_network; 1662 delete brom; 1663 delete mnic; 1664 delete fbuf; 1665 delete bdev; 1666 delete cdma; 1667 delete mtty; 1668 1669 for(size_t x = 0; x < x_size; x++) 1670 { 1671 for(size_t y = 0; y < y_size; y++) 1672 { 1673 delete clusters[x][y]; 1674 } 1675 } 1676 1677 return EXIT_SUCCESS; 1525 1678 } 1526 1679 … … 1548 1701 // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 1549 1702 1550 1551
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