Changeset 648 for branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp
- Timestamp:
- Mar 2, 2014, 10:14:35 PM (10 years ago)
- Location:
- branches/fault_tolerance/platform/tsar_generic_iob
- Files:
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- 1 edited
- 1 copied
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. (copied) (copied from trunk/platforms/tsar_generic_iob)
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tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp (modified) (4 diffs)
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branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp
r607 r648 5 5 // Date : april 2013 6 6 // This program is released under the GNU public license 7 // 8 // Modified by: Cesar Fuguet 9 // Modified on: mars 2014 7 10 ////////////////////////////////////////////////////////////////////////////// 8 11 // Cluster(0,0) & Cluster(xmax-1,ymax-1) contains the IOB0 & IOB1 components. … … 15 18 #include "../include/tsar_iob_cluster.h" 16 19 20 #define tmpl(x) \ 21 template<typename vci_param_int , typename vci_param_ext,\ 22 size_t dspin_int_cmd_width, size_t dspin_int_rsp_width,\ 23 size_t dspin_ram_cmd_width, size_t dspin_ram_rsp_width>\ 24 x TsarIobCluster<\ 25 vci_param_int , vci_param_ext,\ 26 dspin_int_cmd_width, dspin_int_rsp_width,\ 27 dspin_ram_cmd_width, dspin_ram_rsp_width> 28 17 29 namespace soclib { namespace caba { 18 30 … … 20 32 // Constructor 21 33 ////////////////////////////////////////////////////////////////////////// 22 template<typename vci_param_int, 23 typename vci_param_ext, 24 size_t dspin_int_cmd_width, 25 size_t dspin_int_rsp_width, 26 size_t dspin_ram_cmd_width, 27 size_t dspin_ram_rsp_width> 28 TsarIobCluster<vci_param_int, 29 vci_param_ext, 30 dspin_int_cmd_width, 31 dspin_int_rsp_width, 32 dspin_ram_cmd_width, 33 dspin_ram_rsp_width>::TsarIobCluster( 34 ////////////////////////////////////////////////////////////////////////// 35 sc_module_name insname, 36 size_t nb_procs, 37 size_t nb_dmas, 38 size_t x_id, 39 size_t y_id, 40 size_t xmax, 41 size_t ymax, 42 43 const soclib::common::MappingTable &mt_int, 44 const soclib::common::MappingTable &mt_ram, 45 const soclib::common::MappingTable &mt_iox, 46 47 size_t x_width, 48 size_t y_width, 49 size_t l_width, 50 51 size_t memc_int_tgtid, // local index 52 size_t xicu_int_tgtid, // local index 53 size_t mdma_int_tgtid, // local index 54 size_t iobx_int_tgtid, // local index 55 56 size_t proc_int_srcid, // local index 57 size_t mdma_int_srcid, // local index 58 size_t iobx_int_srcid, // local index 59 60 size_t xram_ram_tgtid, // local index 61 62 size_t memc_ram_srcid, // local index 63 size_t iobx_ram_srcid, // local index 64 65 size_t memc_ways, 66 size_t memc_sets, 67 size_t l1_i_ways, 68 size_t l1_i_sets, 69 size_t l1_d_ways, 70 size_t l1_d_sets, 71 size_t xram_latency, 72 73 const Loader &loader, 74 75 uint32_t frozen_cycles, 76 uint32_t debug_start_cycle, 77 bool memc_debug_ok, 78 bool proc_debug_ok, 79 bool iob_debug_ok ) 80 : soclib::caba::BaseModule(insname), 81 p_clk("clk"), 82 p_resetn("resetn") 34 tmpl(/**/)::TsarIobCluster(struct ClusterParams& params) : 35 soclib::caba::BaseModule(params.insname), p_clk("clk"), p_resetn("resetn") 83 36 { 84 assert( (x_id < xmax) and (y_id < ymax) and "Illegal cluster coordinates"); 85 86 size_t cluster_id = (x_id<<4) + y_id; 87 88 size_t cluster_iob0 = 0; // South-West cluster 89 size_t cluster_iob1 = ((xmax-1)<<4) + ymax-1; // North-East cluster 90 91 // Vectors of DSPIN ports for inter-cluster communications 92 p_dspin_int_cmd_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4, 3); 93 p_dspin_int_cmd_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4, 3); 94 p_dspin_int_rsp_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4, 2); 95 p_dspin_int_rsp_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4, 2); 96 97 p_dspin_ram_cmd_in = alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4); 98 p_dspin_ram_cmd_out = alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4); 99 p_dspin_ram_rsp_in = alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4); 100 p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4); 101 102 // ports in cluster_iob0 and cluster_iob1 only 103 if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) 104 { 105 // VCI ports from IOB to IOX network 106 p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>; 107 p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>; 108 109 // DSPIN ports from IOB to RAM network 110 p_dspin_iob_cmd_out = new soclib::caba::DspinOutput<dspin_ram_cmd_width>; 111 p_dspin_iob_rsp_in = new soclib::caba::DspinInput<dspin_ram_rsp_width>; 112 } 113 114 // IRQ ports in cluster_iob0 only 115 if ( cluster_id == cluster_iob0 ) 116 { 117 for ( size_t n=0 ; n<32 ; n++ ) p_irq[n] = new sc_in<bool>; 118 } 119 120 ///////////////////////////////////////////////////////////////////////////// 121 // Hardware components 122 ///////////////////////////////////////////////////////////////////////////// 123 124 //////////// PROCS 125 for (size_t p = 0; p < nb_procs; p++) 126 { 127 std::ostringstream s_proc; 128 s_proc << "proc_" << x_id << "_" << y_id << "_" << p; 129 proc[p] = new VciCcVCacheWrapper<vci_param_int, 130 dspin_int_cmd_width, 131 dspin_int_rsp_width, 132 GdbServer<Mips32ElIss> >( 133 s_proc.str().c_str(), 134 cluster_id*nb_procs + p, // GLOBAL PROC_ID 135 mt_int, // Mapping Table INT network 136 IntTab(cluster_id,p), // SRCID 137 (cluster_id << l_width) + p, // CC_GLOBAL_ID 138 8, // ITLB ways 139 8, // ITLB sets 140 8, // DTLB ways 141 8, // DTLB sets 142 l1_i_ways,l1_i_sets,16, // ICACHE size 143 l1_d_ways,l1_d_sets,16, // DCACHE size 144 4, // WBUF nlines 145 4, // WBUF nwords 146 x_width, 147 y_width, 148 frozen_cycles, // max frozen cycles 149 debug_start_cycle, 150 proc_debug_ok); 151 152 std::ostringstream s_wi_proc; 153 s_wi_proc << "proc_wi_" << x_id << "_" << y_id << "_" << p; 154 proc_wi[p] = new VciDspinInitiatorWrapper<vci_param_int, 155 dspin_int_cmd_width, 156 dspin_int_rsp_width>( 157 s_wi_proc.str().c_str(), 158 x_width + y_width + l_width); 159 } 160 161 /////////// MEMC 162 std::ostringstream s_memc; 163 s_memc << "memc_" << x_id << "_" << y_id; 164 memc = new VciMemCache<vci_param_int, 165 vci_param_ext, 166 dspin_int_rsp_width, 167 dspin_int_cmd_width>( 168 s_memc.str().c_str(), 169 mt_int, // Mapping Table INT network 170 mt_ram, // Mapping Table RAM network 171 IntTab(cluster_id, memc_ram_srcid), // SRCID RAM network 172 IntTab(cluster_id, memc_int_tgtid), // TGTID INT network 173 x_width, // number of bits for x coordinate 174 y_width, // number of bits for y coordinate 175 memc_ways, memc_sets, 16, // CACHE SIZE 176 3, // MAX NUMBER OF COPIES 177 4096, // HEAP SIZE 178 8, // TRANSACTION TABLE DEPTH 179 8, // UPDATE TABLE DEPTH 180 8, // INVALIDATE TABLE DEPTH 181 debug_start_cycle, 182 memc_debug_ok ); 183 184 std::ostringstream s_wt_memc; 185 s_wt_memc << "memc_wt_" << x_id << "_" << y_id; 186 memc_int_wt = new VciDspinTargetWrapper<vci_param_int, 187 dspin_int_cmd_width, 188 dspin_int_rsp_width>( 189 s_wt_memc.str().c_str(), 190 x_width + y_width + l_width); 191 192 std::ostringstream s_wi_memc; 193 s_wi_memc << "memc_wi_" << x_id << "_" << y_id; 194 memc_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext, 195 dspin_ram_cmd_width, 196 dspin_ram_rsp_width>( 197 s_wi_memc.str().c_str(), 198 x_width + y_width + l_width); 199 200 /////////// XICU 201 std::ostringstream s_xicu; 202 s_xicu << "xicu_" << x_id << "_" << y_id; 203 xicu = new VciXicu<vci_param_int>( 204 s_xicu.str().c_str(), 205 mt_int, // mapping table INT network 206 IntTab(cluster_id,xicu_int_tgtid), // TGTID direct space 207 32, // number of timer IRQs 208 32, // number of hard IRQs 209 32, // number of soft IRQs 210 nb_procs); // number of output IRQs 211 212 std::ostringstream s_wt_xicu; 213 s_wt_xicu << "xicu_wt_" << x_id << "_" << y_id; 214 xicu_int_wt = new VciDspinTargetWrapper<vci_param_int, 215 dspin_int_cmd_width, 216 dspin_int_rsp_width>( 217 s_wt_xicu.str().c_str(), 218 x_width + y_width + l_width); 219 220 //////////// MDMA 221 std::ostringstream s_mdma; 222 s_mdma << "mdma_" << x_id << "_" << y_id; 223 mdma = new VciMultiDma<vci_param_int>( 224 s_mdma.str().c_str(), 225 mt_int, 226 IntTab(cluster_id, nb_procs), // SRCID 227 IntTab(cluster_id, mdma_int_tgtid), // TGTID 228 64, // burst size 229 nb_dmas); // number of IRQs 230 231 std::ostringstream s_wt_mdma; 232 s_wt_mdma << "mdma_wt_" << x_id << "_" << y_id; 233 mdma_int_wt = new VciDspinTargetWrapper<vci_param_int, 234 dspin_int_cmd_width, 235 dspin_int_rsp_width>( 236 s_wt_mdma.str().c_str(), 237 x_width + y_width + l_width); 238 239 std::ostringstream s_wi_mdma; 240 s_wi_mdma << "mdma_wi_" << x_id << "_" << y_id; 241 mdma_int_wi = new VciDspinInitiatorWrapper<vci_param_int, 242 dspin_int_cmd_width, 243 dspin_int_rsp_width>( 244 s_wi_mdma.str().c_str(), 245 x_width + y_width + l_width); 246 247 /////////// Direct LOCAL_XBAR(S) 248 size_t nb_direct_initiators = nb_procs + 1; 249 size_t nb_direct_targets = 3; 250 if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) 251 { 252 nb_direct_initiators = nb_procs + 2; 253 nb_direct_targets = 4; 254 } 255 256 std::ostringstream s_int_xbar_cmd_d; 257 s_int_xbar_cmd_d << "int_xbar_cmd_d_" << x_id << "_" << y_id; 258 int_xbar_cmd_d = new DspinLocalCrossbar<dspin_int_cmd_width>( 259 s_int_xbar_cmd_d.str().c_str(), 260 mt_int, // mapping table 261 x_id, y_id, // cluster coordinates 262 x_width, y_width, l_width, 263 nb_direct_initiators, // number of local of sources 264 nb_direct_targets, // number of local dests 265 2, 2, // fifo depths 266 true, // CMD crossbar 267 true, // use routing table 268 false ); // no broacast 269 270 std::ostringstream s_int_xbar_rsp_d; 271 s_int_xbar_rsp_d << "int_xbar_rsp_d_" << x_id << "_" << y_id; 272 int_xbar_rsp_d = new DspinLocalCrossbar<dspin_int_rsp_width>( 273 s_int_xbar_rsp_d.str().c_str(), 274 mt_int, // mapping table 275 x_id, y_id, // cluster coordinates 276 x_width, y_width, l_width, 277 nb_direct_targets, // number of local sources 278 nb_direct_initiators, // number of local dests 279 2, 2, // fifo depths 280 false, // RSP crossbar 281 false, // don't use routing table 282 false ); // no broacast 283 284 //////////// Coherence LOCAL_XBAR(S) 285 std::ostringstream s_int_xbar_m2p_c; 286 s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id; 287 int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>( 288 s_int_xbar_m2p_c.str().c_str(), 289 mt_int, // mapping table 290 x_id, y_id, // cluster coordinates 291 x_width, y_width, l_width, // several dests 292 1, // number of local sources 293 nb_procs, // number of local dests 294 2, 2, // fifo depths 295 true, // pseudo CMD 296 false, // no routing table 297 true ); // broacast 298 299 std::ostringstream s_int_xbar_p2m_c; 300 s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id; 301 int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>( 302 s_int_xbar_p2m_c.str().c_str(), 303 mt_int, // mapping table 304 x_id, y_id, // cluster coordinates 305 x_width, y_width, 0, // only one dest 306 nb_procs, // number of local sources 307 1, // number of local dests 308 2, 2, // fifo depths 309 false, // pseudo RSP 310 false, // no routing table 311 false ); // no broacast 312 313 std::ostringstream s_int_xbar_clack_c; 314 s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id; 315 int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>( 316 s_int_xbar_clack_c.str().c_str(), 317 mt_int, // mapping table 318 x_id, y_id, // cluster coordinates 319 x_width, y_width, l_width, 320 1, // number of local sources 321 nb_procs, // number of local targets 322 1, 1, // fifo depths 323 true, // CMD 324 false, // don't use local routing table 325 false); // broadcast 326 327 ////////////// INT ROUTER(S) 328 std::ostringstream s_int_router_cmd; 329 s_int_router_cmd << "router_cmd_" << x_id << "_" << y_id; 330 int_router_cmd = new VirtualDspinRouter<dspin_int_cmd_width>( 331 s_int_router_cmd.str().c_str(), 332 x_id,y_id, // coordinate in the mesh 333 x_width, y_width, // x & y fields width 334 3, // nb virtual channels 335 4,4); // input & output fifo depths 336 337 std::ostringstream s_int_router_rsp; 338 s_int_router_rsp << "router_rsp_" << x_id << "_" << y_id; 339 int_router_rsp = new VirtualDspinRouter<dspin_int_rsp_width>( 340 s_int_router_rsp.str().c_str(), 341 x_id,y_id, // router coordinates in mesh 342 x_width, y_width, // x & y fields width 343 2, // nb virtual channels 344 4,4); // input & output fifo depths 345 346 ////////////// XRAM 347 std::ostringstream s_xram; 348 s_xram << "xram_" << x_id << "_" << y_id; 349 xram = new VciSimpleRam<vci_param_ext>( 350 s_xram.str().c_str(), 351 IntTab(cluster_id, xram_ram_tgtid ), 352 mt_ram, 353 loader, 354 xram_latency); 355 356 std::ostringstream s_wt_xram; 357 s_wt_xram << "xram_wt_" << x_id << "_" << y_id; 358 xram_ram_wt = new VciDspinTargetWrapper<vci_param_ext, 359 dspin_ram_cmd_width, 360 dspin_ram_rsp_width>( 361 s_wt_xram.str().c_str(), 362 x_width + y_width + l_width); 363 364 ///////////// RAM ROUTER(S) 365 std::ostringstream s_ram_router_cmd; 366 s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id; 367 size_t is_iob0 = (x_id == 0) and (y_id == 0); 368 size_t is_iob1 = (x_id == (xmax-1)) and (y_id == (ymax-1)); 369 ram_router_cmd = new DspinRouterTsar<dspin_ram_cmd_width>( 370 s_ram_router_cmd.str().c_str(), 371 x_id, y_id, // router coordinates in mesh 372 x_width, // x field width in first flit 373 y_width, // y field width in first flit 374 4, 4, // input & output fifo depths 375 is_iob0, // cluster contains IOB0 376 is_iob1, // cluster contains IOB1 377 false, // not a response router 378 l_width); // local field width in first flit 379 380 std::ostringstream s_ram_router_rsp; 381 s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id; 382 ram_router_rsp = new DspinRouterTsar<dspin_ram_rsp_width>( 383 s_ram_router_rsp.str().c_str(), 384 x_id, y_id, // coordinates in mesh 385 x_width, // x field width in first flit 386 y_width, // y field width in first flit 387 4, 4, // input & output fifo depths 388 is_iob0, // cluster contains IOB0 389 is_iob1, // cluster contains IOB1 390 true, // response router 391 l_width); // local field width in first flit 392 393 394 ////////////////////// I/O CLUSTER ONLY /////////////////////// 395 if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) 396 { 397 /////////// IO_BRIDGE 398 size_t iox_local_id; 399 size_t global_id; 400 bool has_irqs; 401 if ( cluster_id == cluster_iob0 ) 402 { 403 iox_local_id = 0; 404 global_id = cluster_iob0; 405 has_irqs = true; 406 } 407 else 408 { 409 iox_local_id = 1; 410 global_id = cluster_iob1; 411 has_irqs = false; 412 } 413 414 std::ostringstream s_iob; 415 s_iob << "iob_" << x_id << "_" << y_id; 416 iob = new VciIoBridge<vci_param_int, 417 vci_param_ext>( 418 s_iob.str().c_str(), 419 mt_ram, // EXT network maptab 420 mt_int, // INT network maptab 421 mt_iox, // IOX network maptab 422 IntTab( global_id, iobx_int_tgtid ), // INT TGTID 423 IntTab( global_id, iobx_int_srcid ), // INT SRCID 424 IntTab( global_id, iox_local_id ), // IOX TGTID 425 has_irqs, 426 16, // cache line words 427 8, // IOTLB ways 428 8, // IOTLB sets 429 debug_start_cycle, 430 iob_debug_ok ); 431 432 std::ostringstream s_iob_int_wi; 433 s_iob_int_wi << "iob_int_wi_" << x_id << "_" << y_id; 434 iob_int_wi = new VciDspinInitiatorWrapper<vci_param_int, 435 dspin_int_cmd_width, 436 dspin_int_rsp_width>( 437 s_iob_int_wi.str().c_str(), 438 x_width + y_width + l_width); 439 440 std::ostringstream s_iob_int_wt; 441 s_iob_int_wt << "iob_int_wt_" << x_id << "_" << y_id; 442 iob_int_wt = new VciDspinTargetWrapper<vci_param_int, 443 dspin_int_cmd_width, 444 dspin_int_rsp_width>( 445 s_iob_int_wt.str().c_str(), 446 x_width + y_width + l_width); 447 448 std::ostringstream s_iob_ram_wi; 449 s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id; 450 iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext, 451 dspin_ram_cmd_width, 452 dspin_ram_rsp_width>( 453 s_iob_ram_wi.str().c_str(), 454 x_width + y_width + l_width); 455 } // end if IO 456 457 //////////////////////////////////// 458 // Connections are defined here 459 //////////////////////////////////// 460 461 // on coherence network : local srcid[proc] in [0...nb_procs-1] 462 // : local srcid[memc] = nb_procs 463 // In cluster_iob0, 32 HWI interrupts from external peripherals 464 // are connected to the XICU ports p_hwi[0:31] 465 // In other clusters, no HWI interrupts are connected to XICU 466 467 //////////////////////// internal CMD & RSP routers 468 int_router_cmd->p_clk (this->p_clk); 469 int_router_cmd->p_resetn (this->p_resetn); 470 int_router_rsp->p_clk (this->p_clk); 471 int_router_rsp->p_resetn (this->p_resetn); 472 473 for (int i = 0; i < 4; i++) 474 { 475 for(int k = 0; k < 3; k++) 476 { 477 int_router_cmd->p_out[i][k] (this->p_dspin_int_cmd_out[i][k]); 478 int_router_cmd->p_in[i][k] (this->p_dspin_int_cmd_in[i][k]); 479 } 480 481 for(int k = 0; k < 2; k++) 482 { 483 int_router_rsp->p_out[i][k] (this->p_dspin_int_rsp_out[i][k]); 484 int_router_rsp->p_in[i][k] (this->p_dspin_int_rsp_in[i][k]); 485 } 486 } 487 488 // local ports 489 int_router_cmd->p_out[4][0] (signal_int_dspin_cmd_g2l_d); 490 int_router_cmd->p_out[4][1] (signal_int_dspin_m2p_g2l_c); 491 int_router_cmd->p_out[4][2] (signal_int_dspin_clack_g2l_c); 492 int_router_cmd->p_in[4][0] (signal_int_dspin_cmd_l2g_d); 493 int_router_cmd->p_in[4][1] (signal_int_dspin_m2p_l2g_c); 494 int_router_cmd->p_in[4][2] (signal_int_dspin_clack_l2g_c); 495 496 int_router_rsp->p_out[4][0] (signal_int_dspin_rsp_g2l_d); 497 int_router_rsp->p_out[4][1] (signal_int_dspin_p2m_g2l_c); 498 int_router_rsp->p_in[4][0] (signal_int_dspin_rsp_l2g_d); 499 int_router_rsp->p_in[4][1] (signal_int_dspin_p2m_l2g_c); 500 501 ///////////////////// CMD DSPIN local crossbar direct 502 int_xbar_cmd_d->p_clk (this->p_clk); 503 int_xbar_cmd_d->p_resetn (this->p_resetn); 504 int_xbar_cmd_d->p_global_out (signal_int_dspin_cmd_l2g_d); 505 int_xbar_cmd_d->p_global_in (signal_int_dspin_cmd_g2l_d); 506 507 int_xbar_cmd_d->p_local_out[memc_int_tgtid] (signal_int_dspin_cmd_memc_t); 508 int_xbar_cmd_d->p_local_out[xicu_int_tgtid] (signal_int_dspin_cmd_xicu_t); 509 int_xbar_cmd_d->p_local_out[mdma_int_tgtid] (signal_int_dspin_cmd_mdma_t); 510 511 int_xbar_cmd_d->p_local_in[mdma_int_srcid] (signal_int_dspin_cmd_mdma_i); 512 513 for (size_t p = 0; p < nb_procs; p++) 514 int_xbar_cmd_d->p_local_in[proc_int_srcid+p] (signal_int_dspin_cmd_proc_i[p]); 515 516 if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) 517 { 518 int_xbar_cmd_d->p_local_out[iobx_int_tgtid] (signal_int_dspin_cmd_iobx_t); 519 int_xbar_cmd_d->p_local_in[iobx_int_srcid] (signal_int_dspin_cmd_iobx_i); 520 } 521 522 //////////////////////// RSP DSPIN local crossbar direct 523 int_xbar_rsp_d->p_clk (this->p_clk); 524 int_xbar_rsp_d->p_resetn (this->p_resetn); 525 int_xbar_rsp_d->p_global_out (signal_int_dspin_rsp_l2g_d); 526 int_xbar_rsp_d->p_global_in (signal_int_dspin_rsp_g2l_d); 527 528 int_xbar_rsp_d->p_local_in[memc_int_tgtid] (signal_int_dspin_rsp_memc_t); 529 int_xbar_rsp_d->p_local_in[xicu_int_tgtid] (signal_int_dspin_rsp_xicu_t); 530 int_xbar_rsp_d->p_local_in[mdma_int_tgtid] (signal_int_dspin_rsp_mdma_t); 531 532 int_xbar_rsp_d->p_local_out[mdma_int_srcid] (signal_int_dspin_rsp_mdma_i); 533 534 for (size_t p = 0; p < nb_procs; p++) 535 int_xbar_rsp_d->p_local_out[proc_int_srcid+p] (signal_int_dspin_rsp_proc_i[p]); 536 537 if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) 538 { 539 int_xbar_rsp_d->p_local_in[iobx_int_tgtid] (signal_int_dspin_rsp_iobx_t); 540 int_xbar_rsp_d->p_local_out[iobx_int_srcid] (signal_int_dspin_rsp_iobx_i); 541 } 542 543 ////////////////////// M2P DSPIN local crossbar coherence 544 int_xbar_m2p_c->p_clk (this->p_clk); 545 int_xbar_m2p_c->p_resetn (this->p_resetn); 546 int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c); 547 int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c); 548 int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc); 549 for (size_t p = 0; p < nb_procs; p++) 550 int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]); 551 552 ////////////////////////// P2M DSPIN local crossbar coherence 553 int_xbar_p2m_c->p_clk (this->p_clk); 554 int_xbar_p2m_c->p_resetn (this->p_resetn); 555 int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c); 556 int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c); 557 int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc); 558 for (size_t p = 0; p < nb_procs; p++) 559 int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]); 560 561 ////////////////////// CLACK DSPIN local crossbar coherence 562 int_xbar_clack_c->p_clk (this->p_clk); 563 int_xbar_clack_c->p_resetn (this->p_resetn); 564 int_xbar_clack_c->p_global_out (signal_int_dspin_clack_l2g_c); 565 int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c); 566 int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc); 567 for (size_t p = 0; p < nb_procs; p++) 568 int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]); 569 570 //////////////////////////////////// Processors 571 for (size_t p = 0; p < nb_procs; p++) 572 { 573 proc[p]->p_clk (this->p_clk); 574 proc[p]->p_resetn (this->p_resetn); 575 proc[p]->p_vci (signal_int_vci_ini_proc[p]); 576 proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]); 577 proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]); 578 proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]); 579 proc[p]->p_irq[0] (signal_proc_it[p]); 580 for ( size_t j = 1 ; j < 6 ; j++) 581 { 582 proc[p]->p_irq[j] (signal_false); 583 } 584 585 proc_wi[p]->p_clk (this->p_clk); 586 proc_wi[p]->p_resetn (this->p_resetn); 587 proc_wi[p]->p_dspin_cmd (signal_int_dspin_cmd_proc_i[p]); 588 proc_wi[p]->p_dspin_rsp (signal_int_dspin_rsp_proc_i[p]); 589 proc_wi[p]->p_vci (signal_int_vci_ini_proc[p]); 590 } 591 592 ///////////////////////////////////// XICU 593 xicu->p_clk (this->p_clk); 594 xicu->p_resetn (this->p_resetn); 595 xicu->p_vci (signal_int_vci_tgt_xicu); 596 for ( size_t p=0 ; p<nb_procs ; p++) 597 { 598 xicu->p_irq[p] (signal_proc_it[p]); 599 } 600 for ( size_t i=0 ; i<32 ; i++) 601 { 602 if (cluster_id == cluster_iob0) 603 xicu->p_hwi[i] (*(this->p_irq[i])); 604 else 605 xicu->p_hwi[i] (signal_false); 606 } 607 608 // wrapper XICU 609 xicu_int_wt->p_clk (this->p_clk); 610 xicu_int_wt->p_resetn (this->p_resetn); 611 xicu_int_wt->p_dspin_cmd (signal_int_dspin_cmd_xicu_t); 612 xicu_int_wt->p_dspin_rsp (signal_int_dspin_rsp_xicu_t); 613 xicu_int_wt->p_vci (signal_int_vci_tgt_xicu); 614 615 ///////////////////////////////////// MEMC 616 memc->p_clk (this->p_clk); 617 memc->p_resetn (this->p_resetn); 618 memc->p_vci_ixr (signal_ram_vci_ini_memc); 619 memc->p_vci_tgt (signal_int_vci_tgt_memc); 620 memc->p_dspin_p2m (signal_int_dspin_p2m_memc); 621 memc->p_dspin_m2p (signal_int_dspin_m2p_memc); 622 memc->p_dspin_clack (signal_int_dspin_clack_memc); 623 memc->p_irq (signal_irq_memc); 624 625 // wrapper to INT network 626 memc_int_wt->p_clk (this->p_clk); 627 memc_int_wt->p_resetn (this->p_resetn); 628 memc_int_wt->p_dspin_cmd (signal_int_dspin_cmd_memc_t); 629 memc_int_wt->p_dspin_rsp (signal_int_dspin_rsp_memc_t); 630 memc_int_wt->p_vci (signal_int_vci_tgt_memc); 631 632 // wrapper to RAM network 633 memc_ram_wi->p_clk (this->p_clk); 634 memc_ram_wi->p_resetn (this->p_resetn); 635 memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i); 636 memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i); 637 memc_ram_wi->p_vci (signal_ram_vci_ini_memc); 638 639 //////////////////////////////////// XRAM 640 xram->p_clk (this->p_clk); 641 xram->p_resetn (this->p_resetn); 642 xram->p_vci (signal_ram_vci_tgt_xram); 643 644 // wrapper to RAM network 645 xram_ram_wt->p_clk (this->p_clk); 646 xram_ram_wt->p_resetn (this->p_resetn); 647 xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t); 648 xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t); 649 xram_ram_wt->p_vci (signal_ram_vci_tgt_xram); 650 651 /////////////////////////////////// MDMA 652 mdma->p_clk (this->p_clk); 653 mdma->p_resetn (this->p_resetn); 654 mdma->p_vci_target (signal_int_vci_tgt_mdma); 655 mdma->p_vci_initiator (signal_int_vci_ini_mdma); 656 for (size_t i=0 ; i<nb_dmas ; i++) 657 mdma->p_irq[i] (signal_irq_mdma[i]); 658 659 // target wrapper 660 mdma_int_wt->p_clk (this->p_clk); 661 mdma_int_wt->p_resetn (this->p_resetn); 662 mdma_int_wt->p_dspin_cmd (signal_int_dspin_cmd_mdma_t); 663 mdma_int_wt->p_dspin_rsp (signal_int_dspin_rsp_mdma_t); 664 mdma_int_wt->p_vci (signal_int_vci_tgt_mdma); 665 666 // initiator wrapper 667 mdma_int_wi->p_clk (this->p_clk); 668 mdma_int_wi->p_resetn (this->p_resetn); 669 mdma_int_wi->p_dspin_cmd (signal_int_dspin_cmd_mdma_i); 670 mdma_int_wi->p_dspin_rsp (signal_int_dspin_rsp_mdma_i); 671 mdma_int_wi->p_vci (signal_int_vci_ini_mdma); 672 673 //////////////////////////// RAM network CMD & RSP routers 674 ram_router_cmd->p_clk (this->p_clk); 675 ram_router_cmd->p_resetn (this->p_resetn); 676 ram_router_rsp->p_clk (this->p_clk); 677 ram_router_rsp->p_resetn (this->p_resetn); 678 for( size_t n=0 ; n<4 ; n++) 679 { 680 ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]); 681 ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]); 682 ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]); 683 ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]); 684 } 685 ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t); 686 ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i); 687 ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i); 688 ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t); 689 690 ///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1. 691 if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) 692 { 693 // IO bridge 694 iob->p_clk (this->p_clk); 695 iob->p_resetn (this->p_resetn); 696 iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini)); 697 iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt)); 698 iob->p_vci_tgt_int (signal_int_vci_tgt_iobx); 699 iob->p_vci_ini_int (signal_int_vci_ini_iobx); 700 iob->p_vci_ini_ram (signal_ram_vci_ini_iobx); 701 702 if ( cluster_id == cluster_iob0 ) 703 for ( size_t n=0 ; n<32 ; n++ ) 704 (*iob->p_irq[n]) (*(this->p_irq[n])); 705 706 // initiator wrapper to RAM network 707 iob_ram_wi->p_clk (this->p_clk); 708 iob_ram_wi->p_resetn (this->p_resetn); 709 iob_ram_wi->p_dspin_cmd (*(this->p_dspin_iob_cmd_out)); 710 iob_ram_wi->p_dspin_rsp (*(this->p_dspin_iob_rsp_in)); 711 iob_ram_wi->p_vci (signal_ram_vci_ini_iobx); 712 713 // initiator wrapper to INT network 714 iob_int_wi->p_clk (this->p_clk); 715 iob_int_wi->p_resetn (this->p_resetn); 716 iob_int_wi->p_dspin_cmd (signal_int_dspin_cmd_iobx_i); 717 iob_int_wi->p_dspin_rsp (signal_int_dspin_rsp_iobx_i); 718 iob_int_wi->p_vci (signal_int_vci_ini_iobx); 719 720 // target wrapper to INT network 721 iob_int_wt->p_clk (this->p_clk); 722 iob_int_wt->p_resetn (this->p_resetn); 723 iob_int_wt->p_dspin_cmd (signal_int_dspin_cmd_iobx_t); 724 iob_int_wt->p_dspin_rsp (signal_int_dspin_rsp_iobx_t); 725 iob_int_wt->p_vci (signal_int_vci_tgt_iobx); 726 } 727 37 assert((params.x_id < params.x_size) and (params.y_id < params.y_size)); 38 39 this->m_procs = params.nb_procs; 40 size_t cluster_id = (params.x_id << 4) + params.y_id; 41 42 size_t cluster_iob0 = 0; 43 size_t cluster_iob1 = ((params.x_size - 1) << 4) + params.y_size - 1; 44 45 // Vectors of DSPIN ports for inter-cluster communications 46 p_dspin_int_cmd_in = 47 alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4, 3); 48 p_dspin_int_cmd_out = 49 alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4, 3); 50 p_dspin_int_rsp_in = 51 alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4, 2); 52 p_dspin_int_rsp_out = 53 alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4, 2); 54 55 p_dspin_ram_cmd_in = 56 alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4); 57 p_dspin_ram_cmd_out = 58 alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4); 59 p_dspin_ram_rsp_in = 60 alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4); 61 p_dspin_ram_rsp_out = 62 alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4); 63 64 // ports in cluster_iob0 and cluster_iob1 only 65 if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) 66 { 67 // VCI ports from IOB to IOX network 68 p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>; 69 p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>; 70 71 // DSPIN ports from IOB to RAM network 72 p_dspin_iob_cmd_out = 73 new soclib::caba::DspinOutput<dspin_ram_cmd_width>; 74 p_dspin_iob_rsp_in = 75 new soclib::caba::DspinInput<dspin_ram_rsp_width>; 76 } 77 else 78 { 79 p_vci_iob_iox_ini = NULL; 80 p_vci_iob_iox_tgt = NULL; 81 p_dspin_iob_cmd_out = NULL; 82 p_dspin_iob_rsp_in = NULL; 83 } 84 85 // IRQ ports in cluster_iob0 only 86 for ( size_t n = 0 ; n < 32 ; n++ ) 87 { 88 if ( cluster_id == cluster_iob0 ) 89 { 90 p_irq[n] = new sc_in<bool>; 91 } 92 else 93 { 94 p_irq[n] = NULL; 95 } 96 } 97 98 /////////////////////////////////////////////////////////////////////////// 99 // Hardware components 100 /////////////////////////////////////////////////////////////////////////// 101 102 //////////// PROCS 103 for (size_t p = 0; p < params.nb_procs; p++) 104 { 105 std::ostringstream s_proc; 106 s_proc << "proc_" << params.x_id << "_" << params.y_id << "_" << p; 107 proc[p] = new VciCcVCacheWrapperType ( 108 s_proc.str().c_str(), 109 cluster_id * params.nb_procs + p, 110 params.mt_int, 111 IntTab(cluster_id,p), 112 (cluster_id << params.l_width) + p, 113 8, 8, 114 8, 8, 115 params.l1_i_ways, params.l1_i_sets, 16, 116 params.l1_d_ways, params.l1_d_sets, 16, 117 4, 4, 118 params.x_width, params.y_width, 119 params.frozen_cycles, 120 params.debug_start_cycle, params.proc_debug_ok); 121 122 std::ostringstream s_wi_proc; 123 s_wi_proc << "proc_wi_" << params.x_id << "_" << params.y_id << "_" 124 << p; 125 proc_wi[p] = new VciIntDspinInitiatorWrapperType( 126 s_wi_proc.str().c_str(), 127 params.x_width + params.y_width + params.l_width); 128 } 129 130 /////////// MEMC 131 std::ostringstream s_memc; 132 s_memc << "memc_" << params.x_id << "_" << params.y_id; 133 memc = new VciMemCacheType ( 134 s_memc.str().c_str(), 135 params.mt_int, 136 params.mt_ext, 137 IntTab(cluster_id, params.ext_memc_srcid), 138 IntTab(cluster_id, params.int_memc_tgtid), 139 params.x_width, 140 params.y_width, 141 params.memc_ways, params.memc_sets, 16, 142 3, 143 4096, 144 8, 145 8, 146 8, 147 params.debug_start_cycle, 148 params.memc_debug_ok); 149 150 std::ostringstream s_wt_memc; 151 s_wt_memc << "memc_wt_" << params.x_id << "_" << params.y_id; 152 memc_int_wt = new VciIntDspinTargetWrapperType ( 153 s_wt_memc.str().c_str(), 154 params.x_width + params.y_width + params.l_width); 155 156 std::ostringstream s_wi_memc; 157 s_wi_memc << "memc_wi_" << params.x_id << "_" << params.y_id; 158 memc_ram_wi = new VciExtDspinInitiatorWrapperType ( 159 s_wi_memc.str().c_str(), 160 params.x_width + params.y_width + params.l_width); 161 162 /////////// XICU 163 std::ostringstream s_xicu; 164 s_xicu << "xicu_" << params.x_id << "_" << params.y_id; 165 xicu = new VciXicu<vci_param_int>( 166 s_xicu.str().c_str(), 167 params.mt_int, 168 IntTab(cluster_id,params.int_xicu_tgtid), 169 32, 32, 32, 170 params.nb_procs); 171 172 std::ostringstream s_wt_xicu; 173 s_wt_xicu << "xicu_wt_" << params.x_id << "_" << params.y_id; 174 xicu_int_wt = new VciIntDspinTargetWrapperType ( 175 s_wt_xicu.str().c_str(), 176 params.x_width + params.y_width + params.l_width); 177 178 //////////// MDMA 179 std::ostringstream s_mdma; 180 s_mdma << "mdma_" << params.x_id << "_" << params.y_id; 181 mdma = new VciMultiDma<vci_param_int>( 182 s_mdma.str().c_str(), 183 params.mt_int, 184 IntTab(cluster_id, params.nb_procs), 185 IntTab(cluster_id, params.int_mdma_tgtid), 186 64, 187 params.nb_dmas); 188 189 std::ostringstream s_wt_mdma; 190 s_wt_mdma << "mdma_wt_" << params.x_id << "_" << params.y_id; 191 mdma_int_wt = new VciIntDspinTargetWrapperType( 192 s_wt_mdma.str().c_str(), 193 params.x_width + params.y_width + params.l_width); 194 195 std::ostringstream s_wi_mdma; 196 s_wi_mdma << "mdma_wi_" << params.x_id << "_" << params.y_id; 197 mdma_int_wi = new VciIntDspinInitiatorWrapperType( 198 s_wi_mdma.str().c_str(), 199 params.x_width + params.y_width + params.l_width); 200 201 /////////// Direct LOCAL_XBAR(S) 202 size_t nb_direct_initiators = params.nb_procs + 1; 203 size_t nb_direct_targets = 3; 204 if ((cluster_id == cluster_iob0) or (cluster_id == cluster_iob1)) 205 { 206 nb_direct_initiators = params.nb_procs + 2; 207 nb_direct_targets = 4; 208 } 209 210 std::ostringstream s_int_xbar_cmd_d; 211 s_int_xbar_cmd_d << "int_xbar_cmd_d_" << params.x_id << "_" << params.y_id; 212 int_xbar_cmd_d = new DspinLocalCrossbar<dspin_int_cmd_width>( 213 s_int_xbar_cmd_d.str().c_str(), 214 params.mt_int, 215 params.x_id, params.y_id, 216 params.x_width, params.y_width, params.l_width, 217 nb_direct_initiators, 218 nb_direct_targets, 219 2, 2, 220 true, 221 true, 222 false); 223 224 std::ostringstream s_int_xbar_rsp_d; 225 s_int_xbar_rsp_d << "int_xbar_rsp_d_" << params.x_id << "_" << params.y_id; 226 int_xbar_rsp_d = new DspinLocalCrossbar<dspin_int_rsp_width>( 227 s_int_xbar_rsp_d.str().c_str(), 228 params.mt_int, 229 params.x_id, params.y_id, 230 params.x_width, params.y_width, params.l_width, 231 nb_direct_targets, 232 nb_direct_initiators, 233 2, 2, 234 false, 235 false, 236 false); 237 238 //////////// Coherence LOCAL_XBAR(S) 239 std::ostringstream s_int_xbar_m2p_c; 240 s_int_xbar_m2p_c << "int_xbar_m2p_c_" << params.x_id << "_" << params.y_id; 241 int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>( 242 s_int_xbar_m2p_c.str().c_str(), 243 params.mt_int, 244 params.x_id, params.y_id, 245 params.x_width, params.y_width, params.l_width, 246 1, 247 params.nb_procs, 248 2, 2, 249 true, 250 false, 251 true); 252 253 std::ostringstream s_int_xbar_p2m_c; 254 s_int_xbar_p2m_c << "int_xbar_p2m_c_" << params.x_id << "_" << params.y_id; 255 int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>( 256 s_int_xbar_p2m_c.str().c_str(), 257 params.mt_int, 258 params.x_id, params.y_id, 259 params.x_width, params.y_width, 0, 260 params.nb_procs, 261 1, 262 2, 2, 263 false, 264 false, 265 false); 266 267 std::ostringstream s_int_xbar_clack_c; 268 s_int_xbar_clack_c << "int_xbar_clack_c_" << params.x_id << "_" 269 << params.y_id; 270 int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>( 271 s_int_xbar_clack_c.str().c_str(), 272 params.mt_int, 273 params.x_id, params.y_id, 274 params.x_width, params.y_width, params.l_width, 275 1, 276 params.nb_procs, 277 1, 1, 278 true, 279 false, 280 false); 281 282 ////////////// INT ROUTER(S) 283 std::ostringstream s_int_router_cmd; 284 s_int_router_cmd << "router_cmd_" << params.x_id << "_" << params.y_id; 285 int_router_cmd = new VirtualDspinRouter<dspin_int_cmd_width>( 286 s_int_router_cmd.str().c_str(), 287 params.x_id,params.y_id, 288 params.x_width, params.y_width, 289 3, 290 4,4); 291 292 std::ostringstream s_int_router_rsp; 293 s_int_router_rsp << "router_rsp_" << params.x_id << "_" << params.y_id; 294 int_router_rsp = new VirtualDspinRouter<dspin_int_rsp_width>( 295 s_int_router_rsp.str().c_str(), 296 params.x_id,params.y_id, 297 params.x_width, params.y_width, 298 2, 299 4,4); 300 301 ////////////// XRAM 302 std::ostringstream s_xram; 303 s_xram << "xram_" << params.x_id << "_" << params.y_id; 304 xram = new VciSimpleRam<vci_param_ext>( 305 s_xram.str().c_str(), 306 IntTab(cluster_id, params.ext_xram_tgtid), 307 params.mt_ext, 308 params.loader, 309 params.xram_latency); 310 311 std::ostringstream s_wt_xram; 312 s_wt_xram << "xram_wt_" << params.x_id << "_" << params.y_id; 313 xram_ram_wt = new VciExtDspinTargetWrapperType( 314 s_wt_xram.str().c_str(), 315 params.x_width + params.y_width + params.l_width); 316 317 ///////////// RAM ROUTER(S) 318 std::ostringstream s_ram_router_cmd; 319 s_ram_router_cmd << "ram_router_cmd_" << params.x_id << "_" << params.y_id; 320 size_t is_iob0 = (params.x_id == 0) and (params.y_id == 0); 321 size_t is_iob1 = (params.x_id == (params.x_size-1)) and 322 (params.y_id == (params.y_size-1)); 323 ram_router_cmd = new DspinRouterTsar<dspin_ram_cmd_width>( 324 s_ram_router_cmd.str().c_str(), 325 params.x_id, params.y_id, 326 params.x_width, 327 params.y_width, 328 4, 4, 329 is_iob0, 330 is_iob1, 331 false, 332 params.l_width); 333 334 std::ostringstream s_ram_router_rsp; 335 s_ram_router_rsp << "ram_router_rsp_" << params.x_id << "_" << params.y_id; 336 ram_router_rsp = new DspinRouterTsar<dspin_ram_rsp_width>( 337 s_ram_router_rsp.str().c_str(), 338 params.x_id, params.y_id, 339 params.x_width, 340 params.y_width, 341 4, 4, 342 is_iob0, 343 is_iob1, 344 true, 345 params.l_width); 346 347 ////////////////////// I/O CLUSTER ONLY /////////////////////// 348 if ((cluster_id == cluster_iob0) or (cluster_id == cluster_iob1)) 349 { 350 /////////// IO_BRIDGE 351 size_t iox_local_id; 352 size_t global_id; 353 bool has_irqs; 354 if (cluster_id == cluster_iob0 ) 355 { 356 iox_local_id = 0; 357 global_id = cluster_iob0; 358 has_irqs = true; 359 } 360 else 361 { 362 iox_local_id = 1; 363 global_id = cluster_iob1; 364 has_irqs = false; 365 } 366 367 std::ostringstream s_iob; 368 s_iob << "iob_" << params.x_id << "_" << params.y_id; 369 iob = new VciIoBridge<vci_param_int, vci_param_ext>( 370 s_iob.str().c_str(), 371 params.mt_ext, 372 params.mt_int, 373 params.mt_iox, 374 IntTab( global_id, params.int_iobx_tgtid), 375 IntTab( global_id, params.int_iobx_srcid), 376 IntTab( global_id, iox_local_id ), 377 has_irqs, 378 16, 379 8, 380 8, 381 params.debug_start_cycle, 382 params.iob_debug_ok ); 383 384 std::ostringstream s_iob_int_wi; 385 s_iob_int_wi << "iob_int_wi_" << params.x_id << "_" << params.y_id; 386 iob_int_wi = new VciIntDspinInitiatorWrapperType( 387 s_iob_int_wi.str().c_str(), 388 params.x_width + params.y_width + params.l_width); 389 390 std::ostringstream s_iob_int_wt; 391 s_iob_int_wt << "iob_int_wt_" << params.x_id << "_" << params.y_id; 392 iob_int_wt = new VciIntDspinTargetWrapperType( 393 s_iob_int_wt.str().c_str(), 394 params.x_width + params.y_width + params.l_width); 395 396 std::ostringstream s_iob_ram_wi; 397 s_iob_ram_wi << "iob_ram_wi_" << params.x_id << "_" << params.y_id; 398 iob_ram_wi = new VciExtDspinInitiatorWrapperType( 399 s_iob_ram_wi.str().c_str(), 400 params.x_width + params.y_width + params.l_width); 401 } 402 else 403 { 404 iob = NULL; 405 iob_int_wi = NULL; 406 iob_int_wt = NULL; 407 iob_ram_wi = NULL; 408 } 409 410 //////////////////////////////////// 411 // Connections are defined here 412 //////////////////////////////////// 413 414 // on coherence network : local srcid[proc] in [0...nb_procs-1] 415 // : local srcid[memc] = nb_procs 416 // In cluster_iob0, 32 HWI interrupts from external peripherals 417 // are connected to the XICU ports p_hwi[0:31] 418 // In other clusters, no HWI interrupts are connected to XICU 419 420 //////////////////////// internal CMD & RSP routers 421 int_router_cmd->p_clk (this->p_clk); 422 int_router_cmd->p_resetn (this->p_resetn); 423 int_router_rsp->p_clk (this->p_clk); 424 int_router_rsp->p_resetn (this->p_resetn); 425 426 for (int i = 0; i < 4; i++) 427 { 428 for(int k = 0; k < 3; k++) 429 { 430 int_router_cmd->p_out[i][k] (this->p_dspin_int_cmd_out[i][k]); 431 int_router_cmd->p_in[i][k] (this->p_dspin_int_cmd_in[i][k]); 432 } 433 434 for(int k = 0; k < 2; k++) 435 { 436 int_router_rsp->p_out[i][k] (this->p_dspin_int_rsp_out[i][k]); 437 int_router_rsp->p_in[i][k] (this->p_dspin_int_rsp_in[i][k]); 438 } 439 } 440 441 // local ports 442 int_router_cmd->p_out[4][0] (signal_int_dspin_cmd_g2l_d); 443 int_router_cmd->p_out[4][1] (signal_int_dspin_m2p_g2l_c); 444 int_router_cmd->p_out[4][2] (signal_int_dspin_clack_g2l_c); 445 int_router_cmd->p_in[4][0] (signal_int_dspin_cmd_l2g_d); 446 int_router_cmd->p_in[4][1] (signal_int_dspin_m2p_l2g_c); 447 int_router_cmd->p_in[4][2] (signal_int_dspin_clack_l2g_c); 448 449 int_router_rsp->p_out[4][0] (signal_int_dspin_rsp_g2l_d); 450 int_router_rsp->p_out[4][1] (signal_int_dspin_p2m_g2l_c); 451 int_router_rsp->p_in[4][0] (signal_int_dspin_rsp_l2g_d); 452 int_router_rsp->p_in[4][1] (signal_int_dspin_p2m_l2g_c); 453 454 ///////////////////// CMD DSPIN local crossbar direct 455 int_xbar_cmd_d->p_clk (this->p_clk); 456 int_xbar_cmd_d->p_resetn (this->p_resetn); 457 int_xbar_cmd_d->p_global_out (signal_int_dspin_cmd_l2g_d); 458 int_xbar_cmd_d->p_global_in (signal_int_dspin_cmd_g2l_d); 459 460 int_xbar_cmd_d->p_local_out[params.int_memc_tgtid]( 461 signal_int_dspin_cmd_memc_t); 462 int_xbar_cmd_d->p_local_out[params.int_xicu_tgtid]( 463 signal_int_dspin_cmd_xicu_t); 464 int_xbar_cmd_d->p_local_out[params.int_mdma_tgtid]( 465 signal_int_dspin_cmd_mdma_t); 466 int_xbar_cmd_d->p_local_in[params.int_mdma_srcid]( 467 signal_int_dspin_cmd_mdma_i); 468 469 for (size_t p = 0; p < params.nb_procs; p++) { 470 int_xbar_cmd_d->p_local_in[params.int_proc_srcid + p]( 471 signal_int_dspin_cmd_proc_i[p]); 472 } 473 474 if ((cluster_id == cluster_iob0) or (cluster_id == cluster_iob1)) 475 { 476 int_xbar_cmd_d->p_local_out[params.int_iobx_tgtid]( 477 signal_int_dspin_cmd_iobx_t); 478 int_xbar_cmd_d->p_local_in[params.int_iobx_srcid]( 479 signal_int_dspin_cmd_iobx_i); 480 } 481 482 //////////////////////// RSP DSPIN local crossbar direct 483 int_xbar_rsp_d->p_clk (this->p_clk); 484 int_xbar_rsp_d->p_resetn (this->p_resetn); 485 int_xbar_rsp_d->p_global_out (signal_int_dspin_rsp_l2g_d); 486 int_xbar_rsp_d->p_global_in (signal_int_dspin_rsp_g2l_d); 487 488 int_xbar_rsp_d->p_local_in[params.int_memc_tgtid]( 489 signal_int_dspin_rsp_memc_t); 490 int_xbar_rsp_d->p_local_in[params.int_xicu_tgtid]( 491 signal_int_dspin_rsp_xicu_t); 492 int_xbar_rsp_d->p_local_in[params.int_mdma_tgtid]( 493 signal_int_dspin_rsp_mdma_t); 494 495 int_xbar_rsp_d->p_local_out[params.int_mdma_srcid]( 496 signal_int_dspin_rsp_mdma_i); 497 for (size_t p = 0; p < params.nb_procs; p++) 498 int_xbar_rsp_d->p_local_out[params.int_proc_srcid + p]( 499 signal_int_dspin_rsp_proc_i[p]); 500 501 if ((cluster_id == cluster_iob0) or (cluster_id == cluster_iob1)) 502 { 503 int_xbar_rsp_d->p_local_in[params.int_iobx_tgtid]( 504 signal_int_dspin_rsp_iobx_t); 505 int_xbar_rsp_d->p_local_out[params.int_iobx_srcid]( 506 signal_int_dspin_rsp_iobx_i); 507 } 508 509 ////////////////////// M2P DSPIN local crossbar coherence 510 int_xbar_m2p_c->p_clk (this->p_clk); 511 int_xbar_m2p_c->p_resetn (this->p_resetn); 512 int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c); 513 int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c); 514 int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc); 515 for (size_t p = 0; p < params.nb_procs; p++) 516 { 517 int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]); 518 } 519 520 ////////////////////////// P2M DSPIN local crossbar coherence 521 int_xbar_p2m_c->p_clk (this->p_clk); 522 int_xbar_p2m_c->p_resetn (this->p_resetn); 523 int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c); 524 int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c); 525 int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc); 526 for (size_t p = 0; p < params.nb_procs; p++) 527 { 528 int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]); 529 } 530 531 ////////////////////// CLACK DSPIN local crossbar coherence 532 int_xbar_clack_c->p_clk (this->p_clk); 533 int_xbar_clack_c->p_resetn (this->p_resetn); 534 int_xbar_clack_c->p_global_out (signal_int_dspin_clack_l2g_c); 535 int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c); 536 int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc); 537 for (size_t p = 0; p < params.nb_procs; p++) 538 { 539 int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]); 540 } 541 542 //////////////////////////////////// Processors 543 for (size_t p = 0; p < params.nb_procs; p++) 544 { 545 proc[p]->p_clk (this->p_clk); 546 proc[p]->p_resetn (this->p_resetn); 547 proc[p]->p_vci (signal_int_vci_ini_proc[p]); 548 proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]); 549 proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]); 550 proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]); 551 proc[p]->p_irq[0] (signal_proc_it[p]); 552 for ( size_t j = 1 ; j < 6 ; j++) 553 { 554 proc[p]->p_irq[j] (signal_false); 555 } 556 557 proc_wi[p]->p_clk (this->p_clk); 558 proc_wi[p]->p_resetn (this->p_resetn); 559 proc_wi[p]->p_dspin_cmd (signal_int_dspin_cmd_proc_i[p]); 560 proc_wi[p]->p_dspin_rsp (signal_int_dspin_rsp_proc_i[p]); 561 proc_wi[p]->p_vci (signal_int_vci_ini_proc[p]); 562 } 563 564 ///////////////////////////////////// XICU 565 xicu->p_clk (this->p_clk); 566 xicu->p_resetn (this->p_resetn); 567 xicu->p_vci (signal_int_vci_tgt_xicu); 568 for ( size_t p = 0 ; p < params.nb_procs ; p++) 569 { 570 xicu->p_irq[p] (signal_proc_it[p]); 571 } 572 for ( size_t i=0 ; i<32 ; i++) 573 { 574 if (cluster_id == cluster_iob0) 575 xicu->p_hwi[i] (*(this->p_irq[i])); 576 else 577 xicu->p_hwi[i] (signal_false); 578 } 579 580 // wrapper XICU 581 xicu_int_wt->p_clk (this->p_clk); 582 xicu_int_wt->p_resetn (this->p_resetn); 583 xicu_int_wt->p_dspin_cmd (signal_int_dspin_cmd_xicu_t); 584 xicu_int_wt->p_dspin_rsp (signal_int_dspin_rsp_xicu_t); 585 xicu_int_wt->p_vci (signal_int_vci_tgt_xicu); 586 587 ///////////////////////////////////// MEMC 588 memc->p_clk (this->p_clk); 589 memc->p_resetn (this->p_resetn); 590 memc->p_vci_ixr (signal_ram_vci_ini_memc); 591 memc->p_vci_tgt (signal_int_vci_tgt_memc); 592 memc->p_dspin_p2m (signal_int_dspin_p2m_memc); 593 memc->p_dspin_m2p (signal_int_dspin_m2p_memc); 594 memc->p_dspin_clack (signal_int_dspin_clack_memc); 595 memc->p_irq (signal_irq_memc); 596 597 // wrapper to INT network 598 memc_int_wt->p_clk (this->p_clk); 599 memc_int_wt->p_resetn (this->p_resetn); 600 memc_int_wt->p_dspin_cmd (signal_int_dspin_cmd_memc_t); 601 memc_int_wt->p_dspin_rsp (signal_int_dspin_rsp_memc_t); 602 memc_int_wt->p_vci (signal_int_vci_tgt_memc); 603 604 // wrapper to RAM network 605 memc_ram_wi->p_clk (this->p_clk); 606 memc_ram_wi->p_resetn (this->p_resetn); 607 memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i); 608 memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i); 609 memc_ram_wi->p_vci (signal_ram_vci_ini_memc); 610 611 //////////////////////////////////// XRAM 612 xram->p_clk (this->p_clk); 613 xram->p_resetn (this->p_resetn); 614 xram->p_vci (signal_ram_vci_tgt_xram); 615 616 // wrapper to RAM network 617 xram_ram_wt->p_clk (this->p_clk); 618 xram_ram_wt->p_resetn (this->p_resetn); 619 xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t); 620 xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t); 621 xram_ram_wt->p_vci (signal_ram_vci_tgt_xram); 622 623 /////////////////////////////////// MDMA 624 mdma->p_clk (this->p_clk); 625 mdma->p_resetn (this->p_resetn); 626 mdma->p_vci_target (signal_int_vci_tgt_mdma); 627 mdma->p_vci_initiator (signal_int_vci_ini_mdma); 628 for (size_t i = 0 ; i < params.nb_dmas ; i++) 629 mdma->p_irq[i] (signal_irq_mdma[i]); 630 631 // target wrapper 632 mdma_int_wt->p_clk (this->p_clk); 633 mdma_int_wt->p_resetn (this->p_resetn); 634 mdma_int_wt->p_dspin_cmd (signal_int_dspin_cmd_mdma_t); 635 mdma_int_wt->p_dspin_rsp (signal_int_dspin_rsp_mdma_t); 636 mdma_int_wt->p_vci (signal_int_vci_tgt_mdma); 637 638 // initiator wrapper 639 mdma_int_wi->p_clk (this->p_clk); 640 mdma_int_wi->p_resetn (this->p_resetn); 641 mdma_int_wi->p_dspin_cmd (signal_int_dspin_cmd_mdma_i); 642 mdma_int_wi->p_dspin_rsp (signal_int_dspin_rsp_mdma_i); 643 mdma_int_wi->p_vci (signal_int_vci_ini_mdma); 644 645 //////////////////////////// RAM network CMD & RSP routers 646 ram_router_cmd->p_clk (this->p_clk); 647 ram_router_cmd->p_resetn (this->p_resetn); 648 ram_router_rsp->p_clk (this->p_clk); 649 ram_router_rsp->p_resetn (this->p_resetn); 650 for( size_t n=0 ; n<4 ; n++) 651 { 652 ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]); 653 ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]); 654 ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]); 655 ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]); 656 } 657 ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t); 658 ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i); 659 ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i); 660 ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t); 661 662 ///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1. 663 if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) 664 { 665 // IO bridge 666 iob->p_clk (this->p_clk); 667 iob->p_resetn (this->p_resetn); 668 iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini)); 669 iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt)); 670 iob->p_vci_tgt_int (signal_int_vci_tgt_iobx); 671 iob->p_vci_ini_int (signal_int_vci_ini_iobx); 672 iob->p_vci_ini_ram (signal_ram_vci_ini_iobx); 673 674 if ( cluster_id == cluster_iob0 ) 675 for ( size_t n = 0 ; n < 32 ; n++ ) 676 (*iob->p_irq[n]) (*(this->p_irq[n])); 677 678 // initiator wrapper to RAM network 679 iob_ram_wi->p_clk (this->p_clk); 680 iob_ram_wi->p_resetn (this->p_resetn); 681 iob_ram_wi->p_dspin_cmd (*(this->p_dspin_iob_cmd_out)); 682 iob_ram_wi->p_dspin_rsp (*(this->p_dspin_iob_rsp_in)); 683 iob_ram_wi->p_vci (signal_ram_vci_ini_iobx); 684 685 // initiator wrapper to INT network 686 iob_int_wi->p_clk (this->p_clk); 687 iob_int_wi->p_resetn (this->p_resetn); 688 iob_int_wi->p_dspin_cmd (signal_int_dspin_cmd_iobx_i); 689 iob_int_wi->p_dspin_rsp (signal_int_dspin_rsp_iobx_i); 690 iob_int_wi->p_vci (signal_int_vci_ini_iobx); 691 692 // target wrapper to INT network 693 iob_int_wt->p_clk (this->p_clk); 694 iob_int_wt->p_resetn (this->p_resetn); 695 iob_int_wt->p_dspin_cmd (signal_int_dspin_cmd_iobx_t); 696 iob_int_wt->p_dspin_rsp (signal_int_dspin_rsp_iobx_t); 697 iob_int_wt->p_vci (signal_int_vci_tgt_iobx); 698 } 728 699 } // end constructor 700 701 tmpl(/**/)::~TsarIobCluster() 702 { 703 if (p_vci_iob_iox_ini) delete p_vci_iob_iox_ini; 704 if (p_vci_iob_iox_tgt) delete p_vci_iob_iox_tgt; 705 if (p_dspin_iob_cmd_out) delete p_dspin_iob_cmd_out; 706 if (p_dspin_iob_rsp_in) delete p_dspin_iob_rsp_in; 707 if (iob) delete iob; 708 if (iob_int_wi) delete iob_int_wi; 709 if (iob_int_wt) delete iob_int_wt; 710 if (iob_ram_wi) delete iob_ram_wi; 711 712 for (size_t n = 0 ; n < 32 ; n++) 713 { 714 if (p_irq[n]) delete p_irq[n]; 715 } 716 717 for (size_t p = 0; p < m_procs; p++) 718 { 719 delete proc[p]; 720 delete proc_wi[p]; 721 } 722 723 delete memc; 724 delete memc_int_wt; 725 delete memc_ram_wi; 726 delete xicu; 727 delete xicu_int_wt; 728 delete mdma; 729 delete mdma_int_wt; 730 delete mdma_int_wi; 731 delete int_xbar_cmd_d; 732 delete int_xbar_rsp_d; 733 delete int_xbar_m2p_c; 734 delete int_xbar_p2m_c; 735 delete int_xbar_clack_c; 736 delete int_router_cmd; 737 delete int_router_rsp; 738 delete xram; 739 delete xram_ram_wt; 740 delete ram_router_cmd; 741 delete ram_router_rsp; 742 } 729 743 730 744 }} … … 740 754 // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 741 755 742 743
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