Changeset 656 for branches/fault_tolerance/module/internal_component/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h

Timestamp:

Mar 7, 2014, 10:24:17 AM (10 years ago)

Author:

cfuguet

Message:

TSAR FAULT TOLERANCE BRANCH

vci_simple_rom:

• Introducing ROM component which can discard most significant bits when calling the load function of the loader. This allows us to replicate some code in several cluster as we can mask the cluster ID bits of the address.

vci_cc_vcache_wrapper:

• Introducing a INST_PADDR_EXT register. This register allows to access addresses further than 4Gbytes when MMU is de-activated.

• Introducing a way to initialize the INST_PADDR_EXT and DATA_ PADDR_EXT registers during reset.

File:

• branches/fault_tolerance/module/internal_component/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (modified) (4 diffs)

branches/fault_tolerance/module/internal_component/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h

@@ -113 +113 @@
         DCACHE_XTN_IC_FLUSH,
         DCACHE_XTN_IC_INVAL_PA,
+        DCACHE_XTN_IC_PADDR_EXT,
         DCACHE_XTN_IT_INVAL,
         DCACHE_XTN_DC_FLUSH,
@@ -322 +323 @@
     bool                                m_debug_ok;
 
+    uint32_t                            m_dcache_paddr_ext_reset;
+    uint32_t                            m_icache_paddr_ext_reset;
+
     ////////////////////////////////////////
     // Communication with processor ISS
@@ -399 +403 @@
     sc_signal<size_t>       r_icache_cc_send_way;           // ICACHE cc_send way
     sc_signal<size_t>       r_icache_cc_send_updt_tab_idx;  // ICACHE cc_send update table index
+
+    // Physical address extension for data access
+    sc_signal<uint32_t>     r_icache_paddr_ext;             // CP2 register (if vci_address > 32)
 
     ///////////////////////////////
@@ -747 +754 @@
     }
 
+    /////////////////////////////////////////////////////////////
+    // Set the m_dcache_paddr_ext_reset attribute
+    //
+    // The r_dcache_paddr_ext register will be initialized after
+    // reset with the m_dcache_paddr_ext_reset value
+    /////////////////////////////////////////////////////////////
+    inline void set_dcache_paddr_ext_reset(uint32_t v)
+    {
+        m_dcache_paddr_ext_reset = v;
+    }
+
+    /////////////////////////////////////////////////////////////
+    // Set the m_icache_paddr_ext_reset attribute
+    //
+    // The r_icache_paddr_ext register will be initialized after
+    // reset with the m_icache_paddr_ext_reset value
+    /////////////////////////////////////////////////////////////
+    inline void set_icache_paddr_ext_reset(uint32_t v)
+    {
+        m_icache_paddr_ext_reset = v;
+    }
+
 private:
     void transition();