Index: trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp
===================================================================
--- trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp	(revision 62)
+++ trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp	(revision 68)
@@ -85,5 +85,4 @@
 	"DCACHE_SC_DIRTY_WAIT",
         "DCACHE_WRITE_UPDT", 
-        "DCACHE_WRITE_DIRTY",
         "DCACHE_WRITE_REQ",  
         "DCACHE_MISS_WAIT",  
@@ -3057,5 +3056,9 @@
 		else
 		{
-	            r_dcache_fsm = DCACHE_WRITE_DIRTY; 
+	            /*
+		     * SC succeeded, but has updated the cache and
+		     * invalidated the TLB entry. Redo the translation
+		     */
+		    r_dcache_fsm = DCACHE_IDLE;
 		}
 	    }
@@ -4482,39 +4485,4 @@
         break;
     }
-    ////////////////////////
-    case DCACHE_WRITE_DIRTY:
-    {
-	m_cost_data_tlb_update_dirty_frz++;
-
-        // external cache invalidate request
-        if ( r_tgt_dcache_req ) 
-        {
-            r_dcache_fsm = DCACHE_CC_CHECK;
-            r_dcache_fsm_save = r_dcache_fsm;
-            break;
-        }
-
-        if ( r_dcache_inval_tlb_rsp ) // Miss read response and tlb invalidation
-        {
-            r_dcache_fsm = DCACHE_IDLE;
-            r_dcache_inval_tlb_rsp = false;
-	    break;
-        }
-
-	if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
-	{
-            r_dcache_fsm = DCACHE_IDLE; 
-            r_dcache_inval_rsp = false;
-	    break;	    
-	}
-
-	m_cpt_dcache_data_write++; 
-        r_dcache.write(r_dcache_tlb_paddr, r_dcache_pte_update);
-        dcache_tlb.setdirty(r_dcache_tlb_way_save, r_dcache_tlb_set_save);
-        r_dcache_fsm = DCACHE_WRITE_REQ;
-        drsp.valid = true;
-        drsp.rdata = 0;
-        break;
-    }
     /////////////////
     case DCACHE_ERROR:
@@ -4758,5 +4726,5 @@
         }
 
-	// DCACHE_TLB1_LL_WAIT  DCACHE_TLB1_SC_WAIT  DCACHE_LL_DIRTY_WAIT  DCACHE_WRITE_DIRTY DCACHE_ITLB_LL_WAIT  DCACHE_ITLB_SC_WAIT
+	// DCACHE_TLB1_LL_WAIT  DCACHE_TLB1_SC_WAIT  DCACHE_LL_DIRTY_WAIT  DCACHE_ITLB_LL_WAIT  DCACHE_ITLB_SC_WAIT
 	// DCACHE_TLB2_LL_WAIT  DCACHE_TLB2_SC_WAIT  DCACHE_SC_DIRTY_WAIT
         if((( /*( r_dcache_fsm_save == DCACHE_UNC_WAIT ) ||*/
@@ -4768,6 +4736,5 @@
 	     ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )   || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT )   ||
 	     ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )   || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT )   ||
-	     ( r_dcache_fsm_save == DCACHE_LL_DIRTY_WAIT )  || ( r_dcache_fsm_save == DCACHE_SC_DIRTY_WAIT )  ||
-	     ( r_dcache_fsm_save == DCACHE_WRITE_DIRTY )*/ ) && 
+	     ( r_dcache_fsm_save == DCACHE_LL_DIRTY_WAIT )  || ( r_dcache_fsm_save == DCACHE_SC_DIRTY_WAIT )  */ ) && 
            ( (r_dcache_tlb_paddr.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1))) ) 
         || (( ( r_dcache_fsm_save == DCACHE_ITLB_READ ) || ( r_dcache_fsm_save == DCACHE_ITLB_UPDT ) /*||
@@ -4775,4 +4742,10 @@
            ( (r_icache_paddr_save.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1))) ) ) 
         {
+	    data_t dcache_rdata = 0;
+	    size_t way = 0;
+	    size_t set = 0;
+	    bool dcache_hit = r_dcache.read(r_tgt_addr.read(), &dcache_rdata, way, &set);;
+	    assert(!dcache_hit && "ignored update req should not be in dcache");
+
             r_dcache_inval_rsp = true;
             r_tgt_dcache_req = false;
@@ -4941,6 +4914,5 @@
              ( r_dcache_fsm_save == DCACHE_TLB1_UPDT )        || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )        ||
              ( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) || ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) ||
-             ( r_dcache_fsm_save == DCACHE_LL_DIRTY_WAIT )    || ( r_dcache_fsm_save == DCACHE_SC_DIRTY_WAIT )    ||
-	     ( r_dcache_fsm_save == DCACHE_WRITE_DIRTY )) && 
+             ( r_dcache_fsm_save == DCACHE_LL_DIRTY_WAIT )    || ( r_dcache_fsm_save == DCACHE_SC_DIRTY_WAIT ) ) && 
             (((r_dcache_tlb_paddr.read() & ~((m_dcache_words<<2)-1)) >> (uint32_log2(m_dcache_words) + 2)) == r_dcache_dtlb_inval_line.read()) ) 
         {
