Index: branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
===================================================================
--- branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 682)
+++ branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 686)
@@ -371,5 +371,5 @@
     sc_signal<paddr_t>      r_icache_vci_paddr;      	// physical address
     sc_signal<uint32_t>     r_icache_vaddr_save;        // virtual address from processor
-
+    sc_signal<bool>         r_icache_read_state;
     // icache miss handling
     sc_signal<size_t>       r_icache_miss_way;		    // selected way for cache update
@@ -420,8 +420,6 @@
     sc_signal<int>          r_dcache_fsm_scan_save;     // return state for tlb scan op
     // registers written in P0 stage (used in P1 stage)
-    sc_signal<bool>         r_dcache_wbuf_req;          // WBUF must be written in P1 stage
-    sc_signal<bool>         r_dcache_updt_req;          // DCACHE must be updated in P1 stage
+    sc_signal<uint32_t>     r_dcache_save_wdata;        // write data (from proc)
     sc_signal<uint32_t>     r_dcache_save_vaddr;        // virtual address (from proc)
-    sc_signal<uint32_t>     r_dcache_save_wdata;        // write data (from proc)
     sc_signal<uint32_t>     r_dcache_save_be;           // byte enable (from proc)
     sc_signal<paddr_t>      r_dcache_save_paddr;        // physical address
@@ -549,5 +547,4 @@
     sc_signal<bool>         r_dcache_updt_data_req;             
     sc_signal<bool>         r_dcache_updt_dir_req;             
-    sc_signal<bool>         r_dcache_rsp_state;             
     sc_signal<bool>         r_dcache_cas_islocal;            // cas is done locally 
     
@@ -561,8 +558,7 @@
 
     //MESI
-    sc_signal<bool>         r_icache_read_state;
     sc_signal<bool>         r_dcache_read_state;
     sc_signal<bool>         r_dcache_read_for_modify;     // a command intent to write
-    sc_signal<bool>         r_dcache_read_hit;            // a command intent to write hit in L1
+    sc_signal<bool>         r_dcache_rsp_state;             
    
      ///////////////////////////////////
Index: branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
===================================================================
--- branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 682)
+++ branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 686)
@@ -270,4 +270,5 @@
       r_icache_vci_paddr("r_icache_vci_paddr"),
       r_icache_vaddr_save("r_icache_vaddr_save"),
+      r_icache_read_state("r_icache_read_state"),
 
       r_icache_miss_way("r_icache_miss_way"),
@@ -304,9 +305,7 @@
       r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"),
 
-      r_dcache_wbuf_req("r_dcache_wbuf_req"),
-      r_dcache_updt_data_req("r_dcache_updt_data_req"),
-      r_dcache_updt_dir_req("r_dcache_updt_dir_req"),
+      r_dcache_save_wdata("r_dcache_save_wdata"),
+
       r_dcache_save_vaddr("r_dcache_save_vaddr"),
-      r_dcache_save_wdata("r_dcache_save_wdata"),
       r_dcache_save_be("r_dcache_save_be"),
       r_dcache_save_paddr("r_dcache_save_paddr"),
@@ -332,4 +331,6 @@
       r_dcache_vci_sc_data("r_dcache_vci_sc_data"),
 
+
+
       r_dcache_xtn_way("r_dcache_xtn_way"),
       r_dcache_xtn_set("r_dcache_xtn_set"),
@@ -354,7 +355,4 @@
       r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
       r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
-//     r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
-//     r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
-//     r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
       r_dcache_tlb_way("r_dcache_tlb_way"),
       r_dcache_tlb_set("r_dcache_tlb_set"),
@@ -374,4 +372,8 @@
       r_dcache_cc_send_way("r_dcache_cc_send_way"),
       r_dcache_cc_send_updt_tab_idx("r_dcache_cc_send_updt_tab_idx"),
+      r_dcache_updt_data_req("r_dcache_updt_data_req"),
+      r_dcache_updt_dir_req("r_dcache_updt_dir_req"),
+      r_dcache_read_for_modify("r_dcache_read_for_modify"),
+      r_dcache_rsp_state("r_dcache_rsp_state"),
 
       r_vci_cmd_fsm("r_vci_cmd_fsm"),
@@ -387,5 +389,4 @@
       r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2),	// 2 words depth
       r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 16),	// 2 words depth
-//      r_vci_rsp_fifo_rpktid("r_vci_rsp_fifo_rpktid", 2),    // 2 words depth
       r_cc_send_data_fifo("r_cc_send_data_fifo", 2),
 
@@ -409,8 +410,7 @@
       r_cc_receive_dcache_updt_tab_idx("r_cc_receive_dcache_updt_tab_idx"),
       r_cc_receive_dcache_nline("r_cc_receive_dcache_nline"),
+
+
       r_cc_receive_dcache_srcid("r_cc_receive_dcache_srcid"),
-
-      r_icache_read_state("r_icache_read_state"),
-      r_dcache_rsp_state("r_dcache_rsp_state"),
 
       r_iss(this->name(), proc_id),
@@ -519,5 +519,4 @@
               << " | MMU = " << r_mmu_mode.read();
     if (r_dcache_updt_data_req.read() ) std::cout << " | P1_UPDT";
-    if (r_dcache_wbuf_req.read() ) std::cout << " | P1_WBUF";
     std::cout << std::endl;
 
@@ -814,7 +813,4 @@
         r_icache_clack_req         = false;
 
-        // No pending write in pipeline
-        r_dcache_wbuf_req          = false;
-
         // No request from DCACHE_FSM to CMD_FSM
         r_dcache_vci_miss_req      = false;
@@ -1010,7 +1006,4 @@
     bool       vci_rsp_fifo_dcache_put   = false;
     uint32_t   vci_rsp_fifo_dcache_data  = 0;
-    bool       vci_rsp_fifo_rpktid_get   = false;
-    bool       vci_rsp_fifo_rpktid_put   = false;
-    bool       vci_rsp_fifo_rpktid       = false;
 
     // FIFO for cleanup data updt
@@ -1018,11 +1011,4 @@
     bool       cleanup_data_updt_fifo_dcache_put   = false;
     uint32_t   cleanup_data_updt_fifo_dcache_data  = 0;
-
-    // updt fifo
-    bool       cc_receive_updt_fifo_get  = false;
-    bool       cc_receive_updt_fifo_put  = false;
-    uint32_t   cc_receive_updt_fifo_be   = 0;
-    uint32_t   cc_receive_updt_fifo_data = 0;
-    bool       cc_receive_updt_fifo_eop  = false;
 
 #ifdef INSTRUMENTATION
@@ -2283,9 +2269,6 @@
 
         bool        tlb_inval_required = false;     // request TLB inval after cache update
-        bool        wbuf_write_miss    = false;     // miss a WBUF write request
         bool        updt_data_request  = false;     // request DCACHE update in P1 stage
         bool        updt_dir_request   = false;     // request DCACHE update in P1 stage
-        bool        wbuf_request       = false;     // request WBUF write in P1 stage
-
 
         // physical address computation : systematic DTLB access (if activated)
@@ -2293,11 +2276,11 @@
         {
 
-//#if 1
-//            // @@@ DO NOT COMMIT: ALMOS KILLING SIMU PURPOSE
-//            if (m_dreq.addr == 0x0 && m_dreq.wdata == 0xDEADDEAD) {
-//                std::cout << "*** Ecriture Ã  l'adresse 0 pour fin de simulation ***" << std::endl;
-//                raise(SIGINT);
-//            }
-//#endif
+#if 0
+            // @@@ DO NOT COMMIT: ALMOS KILLING SIMU PURPOSE
+            if (m_dreq.addr == 0x0 && m_dreq.wdata == 0xDEADDEAD) {
+                std::cout << "*** Ecriture Ã  l'adresse 0 pour fin de simulation ***" << std::endl;
+                raise(SIGINT);
+            }
+#endif
 
             if ( r_mmu_mode.read() & DATA_TLB_MASK )  // DTLB activated
@@ -2938,5 +2921,4 @@
                             r_dcache_vci_miss_req    = true;
                             r_dcache_read_for_modify = true;
-                            r_dcache_read_hit        = true;
                             r_dcache_miss_type       = PROC_MISS;
                             r_dcache_fsm             = DCACHE_MISS_WAIT;
@@ -2965,5 +2947,4 @@
                             r_dcache_fsm             = DCACHE_MISS_SELECT;
                             r_dcache_read_for_modify = true; 
-                            r_dcache_read_hit        = false;
                         }
                         else
@@ -3727,4 +3708,7 @@
 }
 #endif
+        // checking llsc reservation buffer
+        if ( r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read() )
+             r_dcache_llsc_valid = false;
 
         if (r_cas_cache_state.read() == CACHE_SLOT_STATE_EXCLUSIVE or 
@@ -3776,9 +3760,4 @@
             // r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set
             r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
-
-            // checking llsc reservation buffer
-            if ( r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read() )
-                r_dcache_llsc_valid = false;
-
             // request a CAS CMD and go to DCACHE_TLB_LR_WAIT state
             r_dcache_vci_cas_req = true;
@@ -4706,8 +4685,4 @@
             vci_rsp_fifo_dcache_get = true;
 
-           // r_dcache_rsp_state = !r_vci_rsp_fifo_rpktid.read();//deduce the state (CC or NCC) from msb of pktid
-            vci_rsp_fifo_rpktid_get = true;
-
-
             r_dcache_miss_word = r_dcache_miss_word.read() + 1;
 
@@ -4789,5 +4764,5 @@
 #endif
 
-                    r_dcache_fsm                = DCACHE_MISS_BACKOFF;
+                    //r_dcache_fsm                = DCACHE_MISS_BACKOFF;
                     r_dcache_count_backoff      = r_dcache_count_backoff.read() + 1;
                     r_dcache_count_begin        = 0;                    
@@ -4805,6 +4780,5 @@
 #endif
                 r_dcache_count_backoff  = 0;
-                size_t way = r_dcache_miss_way.read();
-                size_t set = r_dcache_miss_set.read();
+
                 if ( r_dcache_rsp_state.read())
                 {
@@ -4831,9 +4805,9 @@
           << " / SET = "   << r_dcache_miss_set.read() << std::endl;
 #endif
-                // reset directory extension
-               if      (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
-               else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
-               else                                           r_dcache_fsm = DCACHE_IDLE;
-            }
+            }
+            // reset directory extension
+            if      (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
+            else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
+            else     r_dcache_fsm = DCACHE_IDLE;
         }
         break;
@@ -5290,5 +5264,5 @@
             else if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
             {
-                assert((state == CACHE_SLOT_STATE_INVALID) or (state == CACHE_SLOT_STATE_ZOMBI) && " CC_UPDT WITH A NO INVALID STATE");
+                assert(((state == CACHE_SLOT_STATE_INVALID) or (state == CACHE_SLOT_STATE_ZOMBI)) && " CC_UPDT WITH A NO INVALID STATE");
                 
                 r_dcache_cc_send_multi_ack_miss = true;
@@ -5304,42 +5278,4 @@
             // signaling matching
   
-        //    if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
-        //    {
-        //        if(r_dcache_read_for_modify.read() and (r_dcache_miss_type == PROC_MISS))
-        //        {
-        //            r_dcache_miss_inval = false;
-        //            r_dcache_miss_updt = true;
-        //            r_dcache_fsm       = r_dcache_fsm_cc_save.read();
-        //        }
-        //        else
-        //        {
-        //           // r_dcache_cc_send_multi_ack_miss = true;
-        //            r_dcache_cc_send_multi_ack_miss = false;
-        //            r_dcache_miss_inval             = false;
-        //            r_dcache_cc_state               = CACHE_SLOT_STATE_INVALID;
-        //            r_dcache_fsm                    = DCACHE_CC_UPDT;
-        //        }
-        //    }
-        //    else
-        //    {
-        //        if(r_cc_receive_dcache_srcid.read() == m_srcid and r_cc_receive_brdcast.read() and (r_dcache_miss_type == PROC_MISS))
-        //        {
-        //            assert(r_dcache_read_for_modify.read() && "miss inval for a miss getm in type of brdcast, this is impossible!!");
-        //            r_dcache_miss_inval      = false;
-        //            r_cc_receive_dcache_req = false;
-        //        }
-        //        else if(not r_cc_receive_brdcast.read() and r_dcache_read_for_modify.read() and (r_dcache_miss_type == PROC_MISS))
-        //        {
-        //            r_dcache_miss_inval = false;
-        //            r_dcache_miss_updt  = true;
-        //        }
-        //        else 
-        //        {
-        //            r_cc_receive_dcache_req = false;
-        //            r_dcache_miss_inval = true;
-        //        }
-        //        r_dcache_fsm            = r_dcache_fsm_cc_save.read();
-        //    }
-
 #if DEBUG_DCACHE
 if ( m_debug_activated )
@@ -5360,7 +5296,4 @@
 
         // CC request handler
-       
-
-
 #ifdef INSTRUMENTATION
 m_cpt_dcache_dir_read++;
@@ -5542,5 +5475,4 @@
                                 // after possible invalidation of copies in TLBs
     {
-        size_t word         = r_dcache_cc_word.read();
         size_t way          = r_dcache_cc_way.read();
         size_t set          = r_dcache_cc_set.read();
@@ -6523,9 +6455,5 @@
                                  vci_rsp_fifo_dcache_put,
                                  vci_rsp_fifo_dcache_data);
-    //BUG pktid
-//    r_vci_rsp_fifo_rpktid.update(vci_rsp_fifo_rpktid_get,
-//                                 vci_rsp_fifo_rpktid_put,
-//                                 vci_rsp_fifo_rpktid);
-//
+
     r_cc_send_data_fifo.update(cleanup_data_updt_fifo_dcache_get,
                                cleanup_data_updt_fifo_dcache_put,
@@ -6614,7 +6542,5 @@
         p_vci.be      = 0xF;
         p_vci.trdid   = 0;
-        if(r_dcache_read_for_modify.read() and r_dcache_read_hit.read())
-            p_vci.pktid   = TYPE_WRITE + 0x8;
-        else if(r_dcache_read_for_modify.read() and not r_dcache_read_hit.read())
+        if(r_dcache_read_for_modify.read())
             p_vci.pktid   = TYPE_WRITE;
         else
