Changeset 695 for branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp
- Timestamp:
- May 18, 2014, 8:33:04 PM (10 years ago)
- File:
-
- 1 edited
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branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp
r658 r695 33 33 ////////////////////////////////////////////////////////////////////////// 34 34 tmpl(/**/)::TsarIobCluster(struct ClusterParams& params) : 35 soclib::caba::BaseModule(params.insname), p_clk("clk"), p_resetn("resetn") 36 { 37 assert((params.x_id < params.x_size) and (params.y_id < params.y_size)); 38 39 this->m_procs = params.nb_procs; 40 size_t cluster_id = (params.x_id << 4) + params.y_id; 41 42 size_t cluster_iob0 = 0; 43 size_t cluster_iob1 = ((params.x_size - 1) << 4) + params.y_size - 1; 35 soclib::caba::BaseModule(params.insname), 36 p_clk("clk"), 37 p_resetn("resetn") { 38 39 assert((params.x_id < X_MAX) && (params.y_id < Y_MAX)); 40 41 size_t cid = this->clusterId(params.x_id, params.y_id); 42 size_t cluster_iob0 = this->clusterId(0, 0); 43 size_t cluster_iob1 = this->clusterId(X_SIZE - 1, Y_SIZE - 1); 44 size_t is_iob0 = (cid == cluster_iob0); 45 size_t is_iob1 = (cid == cluster_iob1); 46 bool is_io_cluster = is_iob0 || is_iob1; 47 48 size_t l_width = vci_param_int::S - X_WIDTH - Y_WIDTH; 44 49 45 50 // Vectors of DSPIN ports for inter-cluster communications … … 63 68 64 69 // ports in cluster_iob0 and cluster_iob1 only 65 if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) 66 { 70 p_vci_iob_iox_ini = NULL; 71 p_vci_iob_iox_tgt = NULL; 72 p_dspin_iob_cmd_out = NULL; 73 p_dspin_iob_rsp_in = NULL; 74 if ( is_io_cluster ) { 67 75 // VCI ports from IOB to IOX network 68 76 p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>; … … 70 78 71 79 // DSPIN ports from IOB to RAM network 72 p_dspin_iob_cmd_out = 73 new soclib::caba::DspinOutput<dspin_ram_cmd_width>; 74 p_dspin_iob_rsp_in = 75 new soclib::caba::DspinInput<dspin_ram_rsp_width>; 76 } 77 else 78 { 79 p_vci_iob_iox_ini = NULL; 80 p_vci_iob_iox_tgt = NULL; 81 p_dspin_iob_cmd_out = NULL; 82 p_dspin_iob_rsp_in = NULL; 80 p_dspin_iob_cmd_out = new soclib::caba::DspinOutput<dspin_ram_cmd_width>; 81 p_dspin_iob_rsp_in = new soclib::caba::DspinInput<dspin_ram_rsp_width>; 83 82 } 84 83 85 84 // IRQ ports in cluster_iob0 only 86 for ( size_t n = 0 ; n < 32 ; n++ ) 87 { 88 if ( cluster_id == cluster_iob0 ) 89 { 90 p_irq[n] = new sc_in<bool>; 91 } 92 else 93 { 94 p_irq[n] = NULL; 95 } 85 for ( size_t n = 0 ; n < 32 ; n++ ) { 86 p_irq[n] = ( is_iob0 ) ? new sc_in<bool> : NULL; 96 87 } 97 88 … … 101 92 102 93 //////////// PROCS 103 for (size_t p = 0; p < params.nb_procs; p++) 104 { 94 for (size_t p = 0; p < NB_PROCS; p++) { 105 95 std::ostringstream s_proc; 106 96 s_proc << "proc_" << params.x_id << "_" << params.y_id << "_" << p; 107 97 proc[p] = new VciCcVCacheWrapperType ( 108 98 s_proc.str().c_str(), 109 c luster_id * params.nb_procs+ p,99 cid * NB_PROCS + p, 110 100 params.mt_int, 111 IntTab(c luster_id,p),112 (c luster_id << params.l_width) + p,101 IntTab(cid,p), 102 (cid << l_width) + p, 113 103 8, 8, 114 104 8, 8, … … 116 106 params.l1_d_ways, params.l1_d_sets, 16, 117 107 4, 4, 118 params.x_width, params.y_width,108 X_WIDTH, Y_WIDTH, 119 109 params.frozen_cycles, 120 110 params.debug_start_cycle, params.proc_debug_ok); 121 111 112 proc[p]->set_dcache_paddr_ext_reset(cid); 113 proc[p]->set_icache_paddr_ext_reset(cid); 114 122 115 std::ostringstream s_wi_proc; 123 s_wi_proc << "proc_wi_" << params.x_id << "_" << params.y_id << "_" 124 << p; 116 s_wi_proc << "proc_wi_" << params.x_id << "_" << params.y_id << "_" << p; 125 117 proc_wi[p] = new VciIntDspinInitiatorWrapperType( 126 118 s_wi_proc.str().c_str(), 127 params.x_width + params.y_width + params.l_width);119 vci_param_int::S); 128 120 } 129 121 … … 135 127 params.mt_int, 136 128 params.mt_ext, 137 IntTab(c luster_id, params.ext_memc_srcid),138 IntTab(c luster_id, params.int_memc_tgtid),139 params.x_width,140 params.y_width,129 IntTab(cid, RAM_MEMC_INI_ID), 130 IntTab(cid, INT_MEMC_TGT_ID), 131 X_WIDTH, 132 Y_WIDTH, 141 133 params.memc_ways, params.memc_sets, 16, 142 134 3, 143 135 4096, 144 8, 145 8, 146 8, 136 8, 8, 8, 147 137 params.debug_start_cycle, 148 138 params.memc_debug_ok); … … 152 142 memc_int_wt = new VciIntDspinTargetWrapperType ( 153 143 s_wt_memc.str().c_str(), 154 params.x_width + params.y_width + params.l_width);144 vci_param_int::S); 155 145 156 146 std::ostringstream s_wi_memc; … … 158 148 memc_ram_wi = new VciExtDspinInitiatorWrapperType ( 159 149 s_wi_memc.str().c_str(), 160 params.x_width + params.y_width + params.l_width);150 vci_param_int::S); 161 151 162 152 /////////// LOCAL ROM 153 std::ostringstream s_brom; 154 s_brom << "brom_" << params.x_id << "_" << params.y_id; 163 155 brom = new VciSimpleRom<vci_param_int>( 164 "brom",165 IntTab(c luster_id, params.int_brom_tgtid),156 s_brom.str().c_str(), 157 IntTab(cid, INT_BROM_TGT_ID), 166 158 params.mt_int, 167 159 params.loader, 168 params.x_width + params.y_width);160 X_WIDTH + Y_WIDTH); 169 161 170 162 std::ostringstream s_wt_brom; … … 172 164 brom_int_wt = new VciIntDspinTargetWrapperType ( 173 165 s_wt_brom.str().c_str(), 174 params.x_width + params.y_width + params.l_width); 166 vci_param_int::S); 167 168 // Multi-TTY controller 169 mtty = NULL; 170 mtty_int_wt = NULL; 171 if (NB_DEBUG_TTY_CHANNELS) { 172 assert(NB_DEBUG_TTY_CHANNELS < 8); 173 174 std::ostringstream s_mtty; 175 s_mtty << "mtty_" << params.x_id << "_" << params.y_id; 176 std::vector<std::string> vect_names; 177 for( size_t tid = 0 ; tid < NB_DEBUG_TTY_CHANNELS ; tid++ ) { 178 std::ostringstream term_name; 179 term_name << s_mtty.str() << "_" << tid; 180 vect_names.push_back(term_name.str().c_str()); 181 } 182 mtty = new VciMultiTty<vci_param_int>( 183 s_mtty.str().c_str(), 184 IntTab(cid, INT_MTTY_TGT_ID), 185 params.mt_int, 186 vect_names); 187 188 std::ostringstream s_wt_mtty; 189 s_wt_mtty << "mtty_wt_" << params.x_id << "_" << params.y_id; 190 mtty_int_wt = new VciIntDspinTargetWrapperType ( 191 s_wt_mtty.str().c_str(), 192 vci_param_int::S); 193 } 175 194 176 195 /////////// XICU … … 180 199 s_xicu.str().c_str(), 181 200 params.mt_int, 182 IntTab(c luster_id,params.int_xicu_tgtid),201 IntTab(cid, INT_XICU_TGT_ID), 183 202 32, 32, 32, 184 params.nb_procs);203 NB_PROCS); 185 204 186 205 std::ostringstream s_wt_xicu; … … 188 207 xicu_int_wt = new VciIntDspinTargetWrapperType ( 189 208 s_wt_xicu.str().c_str(), 190 params.x_width + params.y_width + params.l_width);209 vci_param_int::S); 191 210 192 211 //////////// MDMA … … 196 215 s_mdma.str().c_str(), 197 216 params.mt_int, 198 IntTab(c luster_id, params.nb_procs),199 IntTab(c luster_id, params.int_mdma_tgtid),217 IntTab(cid, NB_PROCS), 218 IntTab(cid, INT_MDMA_TGT_ID), 200 219 64, 201 params.nb_dmas);220 NB_DMA_CHANNELS); 202 221 203 222 std::ostringstream s_wt_mdma; … … 205 224 mdma_int_wt = new VciIntDspinTargetWrapperType( 206 225 s_wt_mdma.str().c_str(), 207 params.x_width + params.y_width + params.l_width);226 vci_param_int::S); 208 227 209 228 std::ostringstream s_wi_mdma; … … 211 230 mdma_int_wi = new VciIntDspinInitiatorWrapperType( 212 231 s_wi_mdma.str().c_str(), 213 params.x_width + params.y_width + params.l_width);232 vci_param_int::S); 214 233 215 234 /////////// Direct LOCAL_XBAR(S) 216 size_t nb_direct_initiators = params.nb_procs+ 1;235 size_t nb_direct_initiators = NB_PROCS + 1; 217 236 size_t nb_direct_targets = 4; 218 if ((cluster_id == cluster_iob0) or (cluster_id == cluster_iob1)) 219 { 220 nb_direct_initiators = params.nb_procs + 2; 221 nb_direct_targets = 5; 237 if (NB_DEBUG_TTY_CHANNELS) { 238 nb_direct_targets++; 239 } 240 if ( is_io_cluster ) { 241 nb_direct_initiators++; 242 nb_direct_targets++; 222 243 } 223 244 … … 228 249 params.mt_int, 229 250 params.x_id, params.y_id, 230 params.x_width, params.y_width, params.l_width,251 X_WIDTH, Y_WIDTH, l_width, 231 252 nb_direct_initiators, 232 253 nb_direct_targets, … … 242 263 params.mt_int, 243 264 params.x_id, params.y_id, 244 params.x_width, params.y_width, params.l_width,265 X_WIDTH, Y_WIDTH, l_width, 245 266 nb_direct_targets, 246 267 nb_direct_initiators, … … 257 278 params.mt_int, 258 279 params.x_id, params.y_id, 259 params.x_width, params.y_width, params.l_width,280 X_WIDTH, Y_WIDTH, l_width, 260 281 1, 261 params.nb_procs,282 NB_PROCS, 262 283 2, 2, 263 284 true, … … 271 292 params.mt_int, 272 293 params.x_id, params.y_id, 273 params.x_width, params.y_width, 0,274 params.nb_procs,294 X_WIDTH, Y_WIDTH, 0, 295 NB_PROCS, 275 296 1, 276 297 2, 2, … … 281 302 std::ostringstream s_int_xbar_clack_c; 282 303 s_int_xbar_clack_c << "int_xbar_clack_c_" << params.x_id << "_" 283 << params.y_id;304 << params.y_id; 284 305 int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>( 285 306 s_int_xbar_clack_c.str().c_str(), 286 307 params.mt_int, 287 308 params.x_id, params.y_id, 288 params.x_width, params.y_width, params.l_width,309 X_WIDTH, Y_WIDTH, l_width, 289 310 1, 290 params.nb_procs,311 NB_PROCS, 291 312 1, 1, 292 313 true, … … 299 320 int_router_cmd = new VirtualDspinRouter<dspin_int_cmd_width>( 300 321 s_int_router_cmd.str().c_str(), 301 params.x_id, params.y_id,302 params.x_width, params.y_width,322 params.x_id, params.y_id, 323 X_WIDTH, Y_WIDTH, 303 324 3, 304 325 4,4); … … 308 329 int_router_rsp = new VirtualDspinRouter<dspin_int_rsp_width>( 309 330 s_int_router_rsp.str().c_str(), 310 params.x_id, params.y_id,311 params.x_width, params.y_width,331 params.x_id, params.y_id, 332 X_WIDTH, Y_WIDTH, 312 333 2, 313 334 4,4); … … 318 339 xram = new VciSimpleRam<vci_param_ext>( 319 340 s_xram.str().c_str(), 320 IntTab(c luster_id, params.ext_xram_tgtid),341 IntTab(cid, RAM_XRAM_TGT_ID), 321 342 params.mt_ext, 322 343 params.loader, … … 327 348 xram_ram_wt = new VciExtDspinTargetWrapperType( 328 349 s_wt_xram.str().c_str(), 329 params.x_width + params.y_width + params.l_width);350 vci_param_int::S); 330 351 331 352 ///////////// RAM ROUTER(S) 332 353 std::ostringstream s_ram_router_cmd; 333 354 s_ram_router_cmd << "ram_router_cmd_" << params.x_id << "_" << params.y_id; 334 size_t is_iob0 = (params.x_id == 0) and (params.y_id == 0);335 size_t is_iob1 = (params.x_id == (params.x_size-1)) and336 (params.y_id == (params.y_size-1));337 355 ram_router_cmd = new DspinRouterTsar<dspin_ram_cmd_width>( 338 356 s_ram_router_cmd.str().c_str(), 339 357 params.x_id, params.y_id, 340 params.x_width, 341 params.y_width, 358 X_WIDTH, Y_WIDTH, 342 359 4, 4, 343 is_iob0, 344 is_iob1, 360 is_iob0, is_iob1, 345 361 false, 346 params.l_width);362 l_width); 347 363 348 364 std::ostringstream s_ram_router_rsp; … … 351 367 s_ram_router_rsp.str().c_str(), 352 368 params.x_id, params.y_id, 353 params.x_width, 354 params.y_width, 369 X_WIDTH, Y_WIDTH, 355 370 4, 4, 356 is_iob0, 357 is_iob1, 371 is_iob0, is_iob1, 358 372 true, 359 params.l_width);373 l_width); 360 374 361 375 ////////////////////// I/O CLUSTER ONLY /////////////////////// 362 if ((cluster_id == cluster_iob0) or (cluster_id == cluster_iob1)) 363 { 376 iob = NULL; 377 iob_int_wi = NULL; 378 iob_int_wt = NULL; 379 iob_ram_wi = NULL; 380 if ( is_io_cluster ) { 364 381 /////////// IO_BRIDGE 365 382 size_t iox_local_id; 366 size_t global_id;367 383 bool has_irqs; 368 if (cluster_id == cluster_iob0 ) 369 { 384 if ( is_iob0 ) { 370 385 iox_local_id = 0; 371 global_id = cluster_iob0;372 386 has_irqs = true; 373 387 } 374 else 375 { 388 else { 376 389 iox_local_id = 1; 377 global_id = cluster_iob1;378 390 has_irqs = false; 379 391 } … … 386 398 params.mt_int, 387 399 params.mt_iox, 388 IntTab( global_id, params.int_iobx_tgtid),389 IntTab( global_id, params.int_iobx_srcid),390 IntTab( global_id, iox_local_id ),400 IntTab(cid, INT_IOBX_TGT_ID), 401 IntTab(cid, INT_IOBX_INI_ID), 402 IntTab(cid, iox_local_id ), 391 403 has_irqs, 392 404 16, … … 400 412 iob_int_wi = new VciIntDspinInitiatorWrapperType( 401 413 s_iob_int_wi.str().c_str(), 402 params.x_width + params.y_width + params.l_width);414 vci_param_int::S); 403 415 404 416 std::ostringstream s_iob_int_wt; … … 406 418 iob_int_wt = new VciIntDspinTargetWrapperType( 407 419 s_iob_int_wt.str().c_str(), 408 params.x_width + params.y_width + params.l_width);420 vci_param_int::S); 409 421 410 422 std::ostringstream s_iob_ram_wi; … … 412 424 iob_ram_wi = new VciExtDspinInitiatorWrapperType( 413 425 s_iob_ram_wi.str().c_str(), 414 params.x_width + params.y_width + params.l_width); 415 } 416 else 417 { 418 iob = NULL; 419 iob_int_wi = NULL; 420 iob_int_wt = NULL; 421 iob_ram_wi = NULL; 426 vci_param_int::S); 422 427 } 423 428 … … 426 431 //////////////////////////////////// 427 432 428 // on coherence network : local srcid[proc] in [0... nb_procs-1]429 // : local srcid[memc] = nb_procs433 // on coherence network : local srcid[proc] in [0...NB_PROCS-1] 434 // : local srcid[memc] = NB_PROCS 430 435 // In cluster_iob0, 32 HWI interrupts from external peripherals 431 436 // are connected to the XICU ports p_hwi[0:31] … … 438 443 int_router_rsp->p_resetn (this->p_resetn); 439 444 440 for (int i = 0; i < 4; i++) 441 { 442 for(int k = 0; k < 3; k++) 443 { 445 for (int i = 0; i < 4; i++) { 446 for(int k = 0; k < 3; k++) { 444 447 int_router_cmd->p_out[i][k] (this->p_dspin_int_cmd_out[i][k]); 445 448 int_router_cmd->p_in[i][k] (this->p_dspin_int_cmd_in[i][k]); 446 449 } 447 448 for(int k = 0; k < 2; k++) 449 { 450 for(int k = 0; k < 2; k++) { 450 451 int_router_rsp->p_out[i][k] (this->p_dspin_int_rsp_out[i][k]); 451 452 int_router_rsp->p_in[i][k] (this->p_dspin_int_rsp_in[i][k]); … … 472 473 int_xbar_cmd_d->p_global_in (signal_int_dspin_cmd_g2l_d); 473 474 474 int_xbar_cmd_d->p_local_out[params.int_memc_tgtid]( 475 signal_int_dspin_cmd_memc_t); 476 int_xbar_cmd_d->p_local_out[params.int_xicu_tgtid]( 477 signal_int_dspin_cmd_xicu_t); 478 int_xbar_cmd_d->p_local_out[params.int_brom_tgtid]( 479 signal_int_dspin_cmd_brom_t); 480 int_xbar_cmd_d->p_local_out[params.int_mdma_tgtid]( 481 signal_int_dspin_cmd_mdma_t); 482 int_xbar_cmd_d->p_local_in[params.int_mdma_srcid]( 483 signal_int_dspin_cmd_mdma_i); 484 485 for (size_t p = 0; p < params.nb_procs; p++) { 486 int_xbar_cmd_d->p_local_in[params.int_proc_srcid + p]( 475 int_xbar_cmd_d->p_local_out[INT_MEMC_TGT_ID] (signal_int_dspin_cmd_memc_t); 476 int_xbar_cmd_d->p_local_out[INT_XICU_TGT_ID] (signal_int_dspin_cmd_xicu_t); 477 int_xbar_cmd_d->p_local_out[INT_BROM_TGT_ID] (signal_int_dspin_cmd_brom_t); 478 int_xbar_cmd_d->p_local_out[INT_MDMA_TGT_ID] (signal_int_dspin_cmd_mdma_t); 479 if (NB_DEBUG_TTY_CHANNELS) { 480 int_xbar_cmd_d->p_local_out[INT_MTTY_TGT_ID] (signal_int_dspin_cmd_mtty_t); 481 } 482 int_xbar_cmd_d->p_local_in[INT_MDMA_INI_ID] (signal_int_dspin_cmd_mdma_i); 483 484 for (size_t p = 0; p < NB_PROCS; p++) { 485 int_xbar_cmd_d->p_local_in[INT_PROC_INI_ID + p]( 487 486 signal_int_dspin_cmd_proc_i[p]); 488 487 } 489 488 490 if ((cluster_id == cluster_iob0) or (cluster_id == cluster_iob1)) 491 { 492 int_xbar_cmd_d->p_local_out[params.int_iobx_tgtid]( 489 if ( is_io_cluster ) { 490 int_xbar_cmd_d->p_local_out[INT_IOBX_TGT_ID]( 493 491 signal_int_dspin_cmd_iobx_t); 494 int_xbar_cmd_d->p_local_in[ params.int_iobx_srcid](492 int_xbar_cmd_d->p_local_in[INT_IOBX_INI_ID]( 495 493 signal_int_dspin_cmd_iobx_i); 496 494 } … … 502 500 int_xbar_rsp_d->p_global_in (signal_int_dspin_rsp_g2l_d); 503 501 504 int_xbar_rsp_d->p_local_in[params.int_memc_tgtid]( 505 signal_int_dspin_rsp_memc_t); 506 int_xbar_rsp_d->p_local_in[params.int_xicu_tgtid]( 507 signal_int_dspin_rsp_xicu_t); 508 int_xbar_rsp_d->p_local_in[params.int_brom_tgtid]( 509 signal_int_dspin_rsp_brom_t); 510 int_xbar_rsp_d->p_local_in[params.int_mdma_tgtid]( 511 signal_int_dspin_rsp_mdma_t); 512 513 int_xbar_rsp_d->p_local_out[params.int_mdma_srcid]( 514 signal_int_dspin_rsp_mdma_i); 515 for (size_t p = 0; p < params.nb_procs; p++) 516 int_xbar_rsp_d->p_local_out[params.int_proc_srcid + p]( 502 int_xbar_rsp_d->p_local_in[INT_MEMC_TGT_ID] (signal_int_dspin_rsp_memc_t); 503 int_xbar_rsp_d->p_local_in[INT_XICU_TGT_ID] (signal_int_dspin_rsp_xicu_t); 504 int_xbar_rsp_d->p_local_in[INT_BROM_TGT_ID] (signal_int_dspin_rsp_brom_t); 505 if (NB_DEBUG_TTY_CHANNELS) { 506 int_xbar_rsp_d->p_local_in[INT_MTTY_TGT_ID] (signal_int_dspin_rsp_mtty_t); 507 } 508 int_xbar_rsp_d->p_local_in[INT_MDMA_TGT_ID] (signal_int_dspin_rsp_mdma_t); 509 510 int_xbar_rsp_d->p_local_out[INT_MDMA_INI_ID](signal_int_dspin_rsp_mdma_i); 511 for (size_t p = 0; p < NB_PROCS; p++) 512 int_xbar_rsp_d->p_local_out[INT_PROC_INI_ID + p]( 517 513 signal_int_dspin_rsp_proc_i[p]); 518 514 519 if ((cluster_id == cluster_iob0) or (cluster_id == cluster_iob1)) 520 { 521 int_xbar_rsp_d->p_local_in[params.int_iobx_tgtid]( 515 if ( is_io_cluster ) { 516 int_xbar_rsp_d->p_local_in[INT_IOBX_TGT_ID]( 522 517 signal_int_dspin_rsp_iobx_t); 523 int_xbar_rsp_d->p_local_out[ params.int_iobx_srcid](518 int_xbar_rsp_d->p_local_out[INT_IOBX_INI_ID]( 524 519 signal_int_dspin_rsp_iobx_i); 525 520 } … … 531 526 int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c); 532 527 int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc); 533 for (size_t p = 0; p < params.nb_procs; p++) 534 { 528 for (size_t p = 0; p < NB_PROCS; p++) { 535 529 int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]); 536 530 } … … 542 536 int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c); 543 537 int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc); 544 for (size_t p = 0; p < params.nb_procs; p++) 545 { 538 for (size_t p = 0; p < NB_PROCS; p++) { 546 539 int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]); 547 540 } … … 553 546 int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c); 554 547 int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc); 555 for (size_t p = 0; p < params.nb_procs; p++) 556 { 548 for (size_t p = 0; p < NB_PROCS; p++) { 557 549 int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]); 558 550 } 559 551 560 552 //////////////////////////////////// Processors 561 for (size_t p = 0; p < params.nb_procs; p++) 562 { 553 for (size_t p = 0; p < NB_PROCS; p++) { 563 554 proc[p]->p_clk (this->p_clk); 564 555 proc[p]->p_resetn (this->p_resetn); … … 568 559 proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]); 569 560 proc[p]->p_irq[0] (signal_proc_it[p]); 570 for ( size_t j = 1 ; j < 6 ; j++) 571 { 561 for ( size_t j = 1 ; j < 6 ; j++) { 572 562 proc[p]->p_irq[j] (signal_false); 573 563 } … … 584 574 xicu->p_resetn (this->p_resetn); 585 575 xicu->p_vci (signal_int_vci_tgt_xicu); 586 for ( size_t p = 0 ; p < params.nb_procs ; p++) 587 { 576 for ( size_t p = 0 ; p < NB_PROCS ; p++) { 588 577 xicu->p_irq[p] (signal_proc_it[p]); 589 578 } 590 for ( size_t i=0 ; i<32 ; i++) 591 { 592 if (cluster_id == cluster_iob0) 579 for ( size_t i=0 ; i<32 ; i++) { 580 if ( is_iob0 ) 593 581 xicu->p_hwi[i] (*(this->p_irq[i])); 594 582 else … … 639 627 brom_int_wt->p_vci (signal_int_vci_tgt_brom); 640 628 629 if (NB_DEBUG_TTY_CHANNELS) { 630 //////////////////////////////////// MTTY 631 mtty->p_clk (this->p_clk); 632 mtty->p_resetn (this->p_resetn); 633 mtty->p_vci (signal_int_vci_tgt_mtty); 634 635 for ( size_t i=0 ; i < NB_DEBUG_TTY_CHANNELS ; i++ ) { 636 mtty->p_irq[i] (signal_irq_mtty[i]); 637 } 638 639 //wrapper to INT network 640 mtty_int_wt->p_clk (this->p_clk); 641 mtty_int_wt->p_resetn (this->p_resetn); 642 mtty_int_wt->p_dspin_cmd (signal_int_dspin_cmd_mtty_t); 643 mtty_int_wt->p_dspin_rsp (signal_int_dspin_rsp_mtty_t); 644 mtty_int_wt->p_vci (signal_int_vci_tgt_mtty); 645 } 646 641 647 //////////////////////////////////// XRAM 642 648 xram->p_clk (this->p_clk); … … 656 662 mdma->p_vci_target (signal_int_vci_tgt_mdma); 657 663 mdma->p_vci_initiator (signal_int_vci_ini_mdma); 658 for (size_t i = 0 ; i < params.nb_dmas; i++)664 for (size_t i = 0 ; i < NB_DMA_CHANNELS ; i++) 659 665 mdma->p_irq[i] (signal_irq_mdma[i]); 660 666 … … 678 684 ram_router_rsp->p_clk (this->p_clk); 679 685 ram_router_rsp->p_resetn (this->p_resetn); 680 for( size_t n=0 ; n<4 ; n++) 681 { 686 for( size_t n=0 ; n<4 ; n++) { 682 687 ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]); 683 688 ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]); … … 691 696 692 697 ///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1. 693 if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) 694 { 698 if ( is_io_cluster ) { 695 699 // IO bridge 696 700 iob->p_clk (this->p_clk); … … 702 706 iob->p_vci_ini_ram (signal_ram_vci_ini_iobx); 703 707 704 if ( cluster_id == cluster_iob0 )708 if ( is_iob0 ) 705 709 for ( size_t n = 0 ; n < 32 ; n++ ) 706 710 (*iob->p_irq[n]) (*(this->p_irq[n])); … … 729 733 } // end constructor 730 734 731 tmpl(/**/)::~TsarIobCluster() 732 { 735 tmpl(/**/)::~TsarIobCluster() { 733 736 if (p_vci_iob_iox_ini) delete p_vci_iob_iox_ini; 734 737 if (p_vci_iob_iox_tgt) delete p_vci_iob_iox_tgt; … … 740 743 if (iob_ram_wi) delete iob_ram_wi; 741 744 742 for (size_t n = 0 ; n < 32 ; n++) 743 { 745 for (size_t n = 0 ; n < 32 ; n++) { 744 746 if (p_irq[n]) delete p_irq[n]; 745 747 } 746 748 747 for (size_t p = 0; p < m_procs; p++) 748 { 749 for (size_t p = 0; p < NB_PROCS; p++) { 749 750 delete proc[p]; 750 751 delete proc_wi[p]; … … 758 759 delete brom; 759 760 delete brom_int_wt; 761 delete mtty; 762 delete mtty_int_wt; 760 763 delete mdma; 761 764 delete mdma_int_wt;
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