Index: trunk/modules/vci_io_bridge/caba/source/include/vci_io_bridge.h
===================================================================
--- trunk/modules/vci_io_bridge/caba/source/include/vci_io_bridge.h	(revision 585)
+++ trunk/modules/vci_io_bridge/caba/source/include/vci_io_bridge.h	(revision 712)
@@ -37,10 +37,13 @@
 //                 configuration or data transactions to peripherals.
 //
-// Regarding DMA transactions initiated by external peripherals, it provides
+// It supports two types of transactions from peripherals:
+//   - DMA transactions to the RAM network,
+//   - WTI transactions to the INT network.
+// Regarding transactions initiated by external peripherals, it provides
 // an - optional - IOMMU service : the 32 bits virtual address is translated
 // to a (up to) 40 bits physical address by a standard SoCLib generic TLB.
 // In case of TLB MISS, the DMA transaction is stalled until the TLB is updated.
-// In case of page fault (illegal access), a VCI error is returned to the
-// faulty peripheral.
+// In case of page fault or read_only violation (illegal access), a VCI error 
+// is returned to the faulty peripheral, and a IOMMU WTI is sent.
 /////////////////////////////////////////////////////////////////////////////////
 //   General Constraints:
@@ -63,6 +66,4 @@
 // - Ne pas garder tous les champs WRITE CMD dans les FIFO a chaque flit
 //   (seulement 'data' et 'be')
-// - Traiter complÃªtement les codes d'erreur en rÃ©ponse Ã  une transaction
-//   WTI write
 ///////////////////////////////////////////////////////////////////////////////
 
@@ -94,9 +95,9 @@
     : public soclib::caba::BaseModule
 {
-    // Data and be fields have different widths on INT and EXT networks
+    // Data and be fields have different widths on INT and EXT/IOC networks
     typedef typename vci_param_ext::data_t          ext_data_t;
     typedef typename vci_param_int::data_t          int_data_t;
     typedef typename vci_param_ext::be_t            ext_be_t;
-    typedef typename vci_param_int::be_t            ext_in_t;
+    typedef typename vci_param_int::be_t            int_be_t;
 
     // Other fields must be equal   
@@ -130,15 +131,21 @@
     {  
         DMA_CMD_IDLE,
-        DMA_CMD_FIFO_PUT_CMD,
-        DMA_CMD_FIFO_PUT_RSP,
-        DMA_CMD_MISS_WAIT,
-        DMA_CMD_WAIT_EOP,
+        DMA_CMD_DMA_REQ,
+        DMA_CMD_WTI_IOX_REQ,
+        DMA_CMD_ERR_WAIT_EOP,
+        DMA_CMD_ERR_WTI_REQ,
+        DMA_CMD_ERR_RSP_REQ,
+        DMA_CMD_TLB_MISS_WAIT,
     };
    
-    // States for DMA_RSP FSM (from RAM to IOX)
+    // States for DMA_RSP FSM 
     enum dma_rsp_fsm_state 
     {  
-        DMA_RSP_IDLE,
-        DMA_RSP_FIFO_PUT, 
+        DMA_RSP_IDLE_DMA,
+        DMA_RSP_IDLE_WTI,
+        DMA_RSP_IDLE_ERR,
+        DMA_RSP_PUT_DMA,
+        DMA_RSP_PUT_WTI,
+        DMA_RSP_PUT_ERR,
     };
     
@@ -159,5 +166,5 @@
 	};
     
-    // States for CONFIG_CMD FSM (from INT to IOX)
+    // States for CONFIG_CMD FSM 
     enum config_cmd_fsm_state 
     {  
@@ -168,26 +175,22 @@
 	};
     
-    // states for CONFIG_RSP FSM (from IOX to INT)
+    // states for CONFIG_RSP FSM 
     enum config_rsp_fsm_state 
     {  
-        CONFIG_RSP_IDLE,
-        CONFIG_RSP_PUT_LO,
+        CONFIG_RSP_IDLE_IOX,
+        CONFIG_RSP_IDLE_LOC,
+        CONFIG_RSP_PUT_LOW,
         CONFIG_RSP_PUT_HI,
         CONFIG_RSP_PUT_UNC,
+        CONFIG_RSP_PUT_LOC,
+
     };
     
-    // States for MISS_WTI_CMD FSM (to INT network) 
-    enum miss_wti_cmd_state 
-    {  
-        MISS_WTI_CMD_IDLE,
-        MISS_WTI_CMD_WTI,
-        MISS_WTI_CMD_MISS,
-	};
-    
-    // States for MISS_WTI_RSP FSM (from INT network) 
+    // States for MISS_WTI_RSP FSM  
     enum miss_wti_rsp_state 
     {  
         MISS_WTI_RSP_IDLE,
-        MISS_WTI_RSP_WTI,
+        MISS_WTI_RSP_WTI_IOX,
+        MISS_WTI_RSP_WTI_MMU,
         MISS_WTI_RSP_MISS,
 	};
@@ -196,6 +199,7 @@
     enum pktid_values_e
     {
-        PKTID_READ  = 0x0,  // TSAR code for read data uncached
-        PKTID_WRITE = 0x4,  // TSAR code for write
+        PKTID_MISS    = 0x0,  // TSAR code for read data uncached
+        PKTID_WTI_IOX = 0x4,  // TSAR code for write
+        PKTID_WTI_MMU = 0xC,  // TSAR code for write
     };
    
@@ -210,5 +214,4 @@
     sc_in<bool>                               p_clk;
     sc_in<bool>                               p_resetn;
-    sc_in<bool>*                              p_irq[32];     // not always constructed
     
     soclib::caba::VciInitiator<vci_param_ext> p_vci_ini_ram; 
@@ -222,9 +225,8 @@
 private:
     const size_t  	                          m_words;
-    const bool                                m_has_irqs;
 
     // INT & IOX Networks
     std::list<soclib::common::Segment>        m_int_seglist;
-    const vci_srcid_t              	          m_int_srcid;  // local SRCID on INT network
+    const vci_srcid_t              	          m_int_srcid;      // SRCID on INT network
     std::list<soclib::common::Segment>        m_iox_seglist;
 
@@ -241,12 +243,15 @@
     // MEMORY MAPPED REGISTERS
     ///////////////////////////////
-    sc_signal<uint32_t>         r_iommu_ptpr;           // page table pointer register
+    sc_signal<uint32_t>         r_iommu_ptpr;           // page table pointer
     sc_signal<bool>             r_iommu_active;         // iotlb mode
-    sc_signal<uint32_t>         r_iommu_bvar;           // iommu bad virtual address
-    sc_signal<uint32_t>         r_iommu_etr;            // iommu error type
-    sc_signal<uint32_t>         r_iommu_bad_id;         // SRCID of faulty peripheral 
-    sc_signal<uint32_t>         r_iommu_wti_enable;     // enable WTI transactions  
-    sc_signal<vci_addr_t>       r_iommu_wti_paddr;      // address of IOMMU WTI 
-    sc_signal<vci_addr_t>*      r_iommu_peri_wti;       // array[32] WTI for peripherals 
+    sc_signal<uint32_t>         r_iommu_bvar;           // bad vaddr
+    sc_signal<uint32_t>         r_iommu_etr;            // error type
+    sc_signal<uint32_t>         r_iommu_bad_id;         // faulty srcid 
+    sc_signal<bool>             r_iommu_wti_enable;     // enable IOB WTI  
+    sc_signal<uint32_t>         r_iommu_wti_addr_lo;    // IOMMU WTI paddr (32 lsb)
+    sc_signal<uint32_t>         r_iommu_wti_addr_hi;    // IOMMU WTI paddr (32 msb)
+
+    sc_signal<uint32_t>         r_xicu_base;            // XICU paddr base (cluster 0)
+    sc_signal<uint32_t>         r_xicu_size;            // XIXU paddr size (cluster 0)
  
 	///////////////////////////////////
@@ -254,6 +259,23 @@
     ///////////////////////////////////
     sc_signal<int>              r_dma_cmd_fsm;		
-    sc_signal<uint32_t>         r_dma_cmd_vaddr;        // input virtual address 
-    sc_signal<vci_addr_t>       r_dma_cmd_paddr;        // output physical address
+    sc_signal<vci_addr_t>       r_dma_cmd_paddr;                // output paddr
+
+    sc_signal<bool>             r_dma_cmd_to_miss_wti_cmd_req;
+    sc_signal<vci_addr_t>       r_dma_cmd_to_miss_wti_cmd_addr;
+    sc_signal<vci_cmd_t>        r_dma_cmd_to_miss_wti_cmd_cmd;
+    sc_signal<vci_srcid_t>      r_dma_cmd_to_miss_wti_cmd_srcid;
+    sc_signal<vci_trdid_t>      r_dma_cmd_to_miss_wti_cmd_trdid;
+    sc_signal<vci_trdid_t>      r_dma_cmd_to_miss_wti_cmd_pktid;
+    sc_signal<int_data_t>       r_dma_cmd_to_miss_wti_cmd_wdata;
+
+    sc_signal<bool>             r_dma_cmd_to_dma_rsp_req;
+    sc_signal<vci_srcid_t>      r_dma_cmd_to_dma_rsp_rsrcid;
+    sc_signal<vci_trdid_t>      r_dma_cmd_to_dma_rsp_rtrdid;
+    sc_signal<vci_pktid_t>      r_dma_cmd_to_dma_rsp_rpktid;
+    sc_signal<vci_rerror_t>     r_dma_cmd_to_dma_rsp_rerror;
+    sc_signal<ext_data_t>       r_dma_cmd_to_dma_rsp_rdata;
+     
+    sc_signal<bool>             r_dma_cmd_to_tlb_req;
+    sc_signal<uint32_t>         r_dma_cmd_to_tlb_vaddr;         // input vaddr 
 
     ///////////////////////////////////
@@ -266,7 +288,11 @@
     ///////////////////////////////////
     sc_signal<int>              r_config_cmd_fsm;
-    sc_signal<uint32_t>         r_config_cmd_rdata;
-    sc_signal<bool>             r_config_cmd_error;
-    sc_signal<uint32_t>         r_config_cmd_inval_vaddr;
+
+    sc_signal<bool>             r_config_cmd_to_tlb_req;
+    sc_signal<uint32_t>         r_config_cmd_to_tlb_vaddr;
+
+    sc_signal<bool>             r_config_cmd_to_config_rsp_req;
+    sc_signal<bool>             r_config_cmd_to_config_rsp_rerror;
+    sc_signal<uint32_t>         r_config_cmd_to_config_rsp_rdata;
 
     sc_signal<ext_data_t>       r_config_cmd_wdata;
@@ -293,26 +319,22 @@
     // TLB FSM REGISTERS
     ///////////////////////////////////
-    sc_signal<int>              r_tlb_fsm;		        // state register 
-    sc_signal<bool>             r_waiting_transaction;  // Flag for returning from
+    sc_signal<int>              r_tlb_fsm;		            // state register 
+    sc_signal<bool>             r_waiting_transaction;      // Flag for returning from
     sc_signal<int>              r_tlb_miss_type;
 	sc_signal<bool>             r_tlb_miss_error; 
 
-    sc_signal<vci_addr_t>       r_tlb_paddr;		    // physical address of pte
-    sc_signal<uint32_t>         r_tlb_pte_flags;	    // pte1 or first word of pte2
-    sc_signal<uint32_t>         r_tlb_pte_ppn;	        // second word of pte2
-    sc_signal<size_t>           r_tlb_way;		        // selected way in tlb    
-    sc_signal<size_t>           r_tlb_set;		        // selected set in tlb    
-
-    uint32_t*                   r_tlb_buf_data;         // prefetch buffer for PTEs
-    sc_signal<bool>             r_tlb_buf_valid;        // one valit flag for all PTEs
-    sc_signal<vci_addr_t>       r_tlb_buf_tag;          // cache line number  
-    sc_signal<vci_addr_t>       r_tlb_buf_vaddr;        // virtual address first PTE  
-    sc_signal<bool>             r_tlb_buf_big_page;     // ???
-
-    ///////////////////////////////////
-    // MISS_WTI_CMD FSM REGISTERS
-    ///////////////////////////////////
-    sc_signal<int>              r_miss_wti_cmd_fsm;
-    sc_signal<size_t>	        r_miss_wti_cmd_index;
+    sc_signal<vci_addr_t>       r_tlb_paddr;		        // physical address of pte
+    sc_signal<uint32_t>         r_tlb_pte_flags;	        // pte1 or first word of pte2
+    sc_signal<uint32_t>         r_tlb_pte_ppn;	            // second word of pte2
+    sc_signal<size_t>           r_tlb_way;		            // selected way in tlb    
+    sc_signal<size_t>           r_tlb_set;		            // selected set in tlb    
+
+    uint32_t*                   r_tlb_buf_data;             // prefetch buffer for PTEs
+    sc_signal<bool>             r_tlb_buf_valid;            // one valit flag for all PTEs
+    sc_signal<vci_addr_t>       r_tlb_buf_tag;              // cache line number  
+    sc_signal<vci_addr_t>       r_tlb_buf_vaddr;            // vaddr for first PTE  
+    sc_signal<bool>             r_tlb_buf_big_page;         // ???
+
+    sc_signal<bool>             r_tlb_to_miss_wti_cmd_req;
 
     ///////////////////////////////////
@@ -320,6 +342,14 @@
     ///////////////////////////////////
     sc_signal<int>              r_miss_wti_rsp_fsm;
-    sc_signal<bool>             r_miss_wti_rsp_error; 
-    sc_signal<size_t>           r_miss_wti_rsp_count; 
+    sc_signal<bool>             r_miss_wti_rsp_error_wti;   // VCI error on WTI
+    sc_signal<bool>             r_miss_wti_rsp_error_miss;  // VCI error on MISS
+    sc_signal<size_t>           r_miss_wti_rsp_count;       // flits counter
+
+    sc_signal<bool>             r_miss_wti_rsp_to_dma_rsp_req;
+    sc_signal<vci_rerror_t>     r_miss_wti_rsp_to_dma_rsp_rerror;
+    sc_signal<vci_srcid_t>      r_miss_wti_rsp_to_dma_rsp_rsrcid;
+    sc_signal<vci_trdid_t>      r_miss_wti_rsp_to_dma_rsp_rtrdid;
+    sc_signal<vci_pktid_t>      r_miss_wti_rsp_to_dma_rsp_rpktid;
+
     
     /////////////////////////////////////////////////////
@@ -327,11 +357,5 @@
     /////////////////////////////////////////////////////
     sc_signal<bool>             r_alloc_fifo_config_rsp_local;  
-    sc_signal<bool>             r_alloc_fifo_dma_rsp_local;  
-
-    //////////////////////////////////
-    // IRQ FSM registers
-    //////////////////////////////////
-	sc_signal<bool>*            r_irq_pending;  // array[32]
-	sc_signal<bool>*            r_irq_request;  // array[32]
+
    
     //////////////////////////////////////////////////////////////////
@@ -340,16 +364,4 @@
     GenericTlb<vci_addr_t>      r_iotlb;
 	
-    //////////////////////////////////////////////////////////////////
-    // Inter-FSM communications
-    //////////////////////////////////////////////////////////////////
-    
-    // between DMA_CMD and TLB FSM 
-    sc_signal<bool>             r_dma_tlb_req;
-
-    // between CONFIG_CMD FSM and TLB FSM
-    sc_signal<bool>             r_config_tlb_req;
-    
-    // between TLB FSM and MISS_WTI FSM 
-    sc_signal<bool>             r_tlb_miss_req;
     
     /////////////////////////
@@ -405,5 +417,20 @@
     GenericFifo<vci_rerror_t>   m_config_rsp_rerror_fifo;
 	
-   
+    // output FIFO to VCI_INI port on INT network (VCI command)
+    GenericFifo<vci_addr_t>     m_miss_wti_cmd_addr_fifo;
+    GenericFifo<vci_srcid_t>    m_miss_wti_cmd_srcid_fifo;
+    GenericFifo<vci_trdid_t>    m_miss_wti_cmd_trdid_fifo;
+    GenericFifo<vci_pktid_t>    m_miss_wti_cmd_pktid_fifo;
+    GenericFifo<int_be_t>       m_miss_wti_cmd_be_fifo;
+    GenericFifo<vci_cmd_t>      m_miss_wti_cmd_cmd_fifo;
+    GenericFifo<vci_contig_t>   m_miss_wti_cmd_contig_fifo;
+    GenericFifo<int_data_t>     m_miss_wti_cmd_data_fifo;
+    GenericFifo<vci_eop_t>      m_miss_wti_cmd_eop_fifo;
+    GenericFifo<vci_cons_t>     m_miss_wti_cmd_cons_fifo;
+    GenericFifo<vci_plen_t>     m_miss_wti_cmd_plen_fifo;
+    GenericFifo<vci_wrap_t>     m_miss_wti_cmd_wrap_fifo;
+    GenericFifo<vci_cfixed_t>   m_miss_wti_cmd_cfixed_fifo;
+    GenericFifo<vci_clen_t>     m_miss_wti_cmd_clen_fifo;
+    
     ////////////////////////////////
     // Activity counters
@@ -432,11 +459,12 @@
     uint32_t m_cpt_fsm_config_cmd       [32]; 
     uint32_t m_cpt_fsm_config_rsp       [32]; 
-    uint32_t m_cpt_fsm_miss_wti_cmd     [32]; 
     uint32_t m_cpt_fsm_miss_wti_rsp     [32];
  
 protected:
+
     SC_HAS_PROCESS(VciIoBridge);
 
 public:
+
     VciIoBridge(
         sc_module_name insname,
@@ -447,5 +475,4 @@
         const    soclib::common::IntTab        &int_srcid,   // INT network SRCID
         const    soclib::common::IntTab        &iox_tgtid,   // IOX network TGTID
-        const    bool                          has_irqs,     // component has irq ports
         const    size_t                        dcache_words,
         const    size_t                        iotlb_ways,
@@ -462,4 +489,6 @@
 
 private:
+
+    bool is_wti( vci_addr_t paddr );
     void transition();
     void genMoore();
