- Timestamp:
- Jun 23, 2014, 3:43:33 PM (10 years ago)
- File:
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- 1 edited
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trunk/modules/vci_io_bridge/caba/source/include/vci_io_bridge.h
r712 r715 6 6 * 7 7 * SOCLIB_LGPL_HEADER_BEGIN 8 * 8 * 9 9 * This file is part of SoCLib, GNU LGPLv2.1. 10 * 10 * 11 11 * SoCLib is free software; you can redistribute it and/or modify it 12 12 * under the terms of the GNU Lesser General Public License as published 13 13 * by the Free Software Foundation; version 2.1 of the License. 14 * 14 * 15 15 * SoCLib is distributed in the hope that it will be useful, but 16 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 18 * Lesser General Public License for more details. 19 * 19 * 20 20 * You should have received a copy of the GNU Lesser General Public 21 21 * License along with SoCLib; if not, write to the Free Software 22 22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 23 23 * 02110-1301 USA 24 * 24 * 25 25 * SOCLIB_LGPL_HEADER_END 26 26 */ … … 44 44 // to a (up to) 40 bits physical address by a standard SoCLib generic TLB. 45 45 // In case of TLB MISS, the DMA transaction is stalled until the TLB is updated. 46 // In case of page fault or read_only violation (illegal access), a VCI error 46 // In case of page fault or read_only violation (illegal access), a VCI error 47 47 // is returned to the faulty peripheral, and a IOMMU WTI is sent. 48 48 ///////////////////////////////////////////////////////////////////////////////// … … 62 62 //////////////////////////////////////////////////////////////////////////////// 63 63 64 64 65 65 ///////TODO List/////////////////////////////////////////////////////////////// 66 66 // - Ne pas garder tous les champs WRITE CMD dans les FIFO a chaque flit … … 77 77 #include "generic_tlb.h" 78 78 #include "mapping_table.h" 79 #include "address_decoding_table.h" 79 #include "address_decoding_table.h" 80 #include "address_masking_table.h" 80 81 #include "static_assert.h" 81 82 #include "vci_initiator.h" 82 83 #include "vci_target.h" 84 #include "transaction_tab_io.h" 83 85 #include "../../../include/soclib/io_bridge.h" 84 86 … … 101 103 typedef typename vci_param_int::be_t int_be_t; 102 104 103 // Other fields must be equal 104 typedef typename vci_param_int::fast_addr_t vci_addr_t; 105 typedef typename vci_param_int::srcid_t vci_srcid_t; 105 // Other fields must be equal 106 typedef typename vci_param_int::fast_addr_t vci_addr_t; 107 typedef typename vci_param_int::srcid_t vci_srcid_t; 106 108 typedef typename vci_param_int::trdid_t vci_trdid_t; 107 109 typedef typename vci_param_int::pktid_t vci_pktid_t; … … 116 118 typedef typename vci_param_int::rerror_t vci_rerror_t; 117 119 118 enum 119 { 120 CACHE_LINE_MASK = 0xFFFFFFFFC0LL, 121 PPN1_MASK = 0x0007FFFF, 122 PPN2_MASK = 0x0FFFFFFF, 123 K_PAGE_OFFSET_MASK = 0x00000FFF, 120 enum 121 { 122 CACHE_LINE_MASK = 0xFFFFFFFFC0LL, 123 PPN1_MASK = 0x0007FFFF, 124 PPN2_MASK = 0x0FFFFFFF, 125 K_PAGE_OFFSET_MASK = 0x00000FFF, 124 126 M_PAGE_OFFSET_MASK = 0x001FFFFF, 125 127 PTE2_LINE_OFFSET = 0x00007000, // bits 12,13,14. 126 PTE1_LINE_OFFSET = 0x01E00000, // bits 21,22,23,24 127 }; 128 128 PTE1_LINE_OFFSET = 0x01E00000, // bits 21,22,23,24 129 }; 130 129 131 // States for DMA_CMD FSM (from IOX to RAM) 130 enum dma_cmd_fsm_state 131 { 132 enum dma_cmd_fsm_state 133 { 132 134 DMA_CMD_IDLE, 133 135 DMA_CMD_DMA_REQ, … … 138 140 DMA_CMD_TLB_MISS_WAIT, 139 141 }; 140 141 // States for DMA_RSP FSM 142 enum dma_rsp_fsm_state 143 { 142 143 // States for DMA_RSP FSM 144 enum dma_rsp_fsm_state 145 { 144 146 DMA_RSP_IDLE_DMA, 145 147 DMA_RSP_IDLE_WTI, … … 149 151 DMA_RSP_PUT_ERR, 150 152 }; 151 153 152 154 // States for TLB_MISS FSM 153 enum dma_tlb_fsm_state 154 { 155 enum dma_tlb_fsm_state 156 { 155 157 TLB_IDLE, 156 158 TLB_MISS, … … 158 160 TLB_PTE1_SELECT, 159 161 TLB_PTE1_UPDT, 160 TLB_PTE2_GET, 162 TLB_PTE2_GET, 161 163 TLB_PTE2_SELECT, 162 164 TLB_PTE2_UPDT, … … 164 166 TLB_RETURN, 165 167 TLB_INVAL_CHECK, 166 167 168 // States for CONFIG_CMD FSM 169 enum config_cmd_fsm_state 170 { 168 }; 169 170 // States for CONFIG_CMD FSM 171 enum config_cmd_fsm_state 172 { 171 173 CONFIG_CMD_IDLE, 172 CONFIG_CMD_NEXT, 174 CONFIG_CMD_WAIT, 175 CONFIG_CMD_HI, 176 CONFIG_CMD_LO, 173 177 CONFIG_CMD_PUT, 174 178 CONFIG_CMD_RSP, 175 176 177 // states for CONFIG_RSP FSM 178 enum config_rsp_fsm_state 179 { 179 }; 180 181 // states for CONFIG_RSP FSM 182 enum config_rsp_fsm_state 183 { 180 184 CONFIG_RSP_IDLE_IOX, 181 185 CONFIG_RSP_IDLE_LOC, 182 CONFIG_RSP_PUT_LO W,186 CONFIG_RSP_PUT_LO, 183 187 CONFIG_RSP_PUT_HI, 184 188 CONFIG_RSP_PUT_UNC, … … 186 190 187 191 }; 188 189 // States for MISS_WTI_RSP FSM 190 enum miss_wti_rsp_state 191 { 192 193 // States for MISS_WTI_RSP FSM 194 enum miss_wti_rsp_state 195 { 192 196 MISS_WTI_RSP_IDLE, 193 197 MISS_WTI_RSP_WTI_IOX, 194 198 MISS_WTI_RSP_WTI_MMU, 195 199 MISS_WTI_RSP_MISS, 196 200 }; 197 201 198 202 // PKTID values for TLB MISS and WTI transactions … … 203 207 PKTID_WTI_MMU = 0xC, // TSAR code for write 204 208 }; 205 209 206 210 // Miss types for iotlb 207 211 enum tlb_miss_type_e 208 212 { 209 PTE1_MISS, 213 PTE1_MISS, 210 214 PTE2_MISS, 211 212 215 }; 216 213 217 public: 214 218 sc_in<bool> p_clk; 215 219 sc_in<bool> p_resetn; 216 217 soclib::caba::VciInitiator<vci_param_ext> p_vci_ini_ram; 220 221 soclib::caba::VciInitiator<vci_param_ext> p_vci_ini_ram; 218 222 219 223 soclib::caba::VciTarget<vci_param_ext> p_vci_tgt_iox; … … 224 228 225 229 private: 226 const size_t 230 const size_t m_words; 227 231 228 232 // INT & IOX Networks 229 233 std::list<soclib::common::Segment> m_int_seglist; 230 const vci_srcid_t 234 const vci_srcid_t m_int_srcid; // SRCID on INT network 231 235 std::list<soclib::common::Segment> m_iox_seglist; 236 const vci_srcid_t m_iox_srcid; // SRCID on IOX network 237 238 // INT & RAM srcid masking table 239 const AddressMaskingTable<uint32_t> m_srcid_gid_mask; 240 const AddressMaskingTable<uint32_t> m_srcid_lid_mask; 232 241 233 242 // TLB parameters 234 const size_t 235 const size_t 236 237 // debug variables 243 const size_t m_iotlb_ways; 244 const size_t m_iotlb_sets; 245 246 // debug variables 238 247 uint32_t m_debug_start_cycle; 239 248 bool m_debug_ok; … … 247 256 sc_signal<uint32_t> r_iommu_bvar; // bad vaddr 248 257 sc_signal<uint32_t> r_iommu_etr; // error type 249 sc_signal<uint32_t> r_iommu_bad_id; // faulty srcid 250 sc_signal<bool> r_iommu_wti_enable; // enable IOB WTI 258 sc_signal<uint32_t> r_iommu_bad_id; // faulty srcid 259 sc_signal<bool> r_iommu_wti_enable; // enable IOB WTI 251 260 sc_signal<uint32_t> r_iommu_wti_addr_lo; // IOMMU WTI paddr (32 lsb) 252 261 sc_signal<uint32_t> r_iommu_wti_addr_hi; // IOMMU WTI paddr (32 msb) 253 262 254 sc_signal<uint32_t> r_xicu_base; // XICU paddr base (cluster 0) 255 sc_signal<uint32_t> r_xicu_size; // XIXU paddr size (cluster 0) 256 257 /////////////////////////////////// 263 /////////////////////////////////// 258 264 // DMA_CMD FSM REGISTERS 259 265 /////////////////////////////////// 260 sc_signal<int> r_dma_cmd_fsm; 266 sc_signal<int> r_dma_cmd_fsm; 261 267 sc_signal<vci_addr_t> r_dma_cmd_paddr; // output paddr 262 268 … … 275 281 sc_signal<vci_rerror_t> r_dma_cmd_to_dma_rsp_rerror; 276 282 sc_signal<ext_data_t> r_dma_cmd_to_dma_rsp_rdata; 277 283 278 284 sc_signal<bool> r_dma_cmd_to_tlb_req; 279 sc_signal<uint32_t> r_dma_cmd_to_tlb_vaddr; // input vaddr 285 sc_signal<uint32_t> r_dma_cmd_to_tlb_vaddr; // input vaddr 280 286 281 287 /////////////////////////////////// … … 283 289 /////////////////////////////////// 284 290 sc_signal<int> r_dma_rsp_fsm; 285 291 286 292 /////////////////////////////////// 287 293 // CONFIG_CMD FSM REGISTERS … … 294 300 sc_signal<bool> r_config_cmd_to_config_rsp_req; 295 301 sc_signal<bool> r_config_cmd_to_config_rsp_rerror; 296 sc_signal<uint32_t> r_config_cmd_to_config_rsp_rdata; 302 sc_signal<int_data_t> r_config_cmd_to_config_rsp_rdata; 303 sc_signal<vci_srcid_t> r_config_cmd_to_config_rsp_rsrcid; 304 sc_signal<vci_trdid_t> r_config_cmd_to_config_rsp_rtrdid; 305 sc_signal<vci_pktid_t> r_config_cmd_to_config_rsp_rpktid; 297 306 298 307 sc_signal<ext_data_t> r_config_cmd_wdata; … … 301 310 sc_signal<vci_addr_t> r_config_cmd_address; 302 311 sc_signal<vci_srcid_t> r_config_cmd_srcid; 312 sc_signal<vci_trdid_t> r_config_cmd_trdid; 303 313 sc_signal<vci_pktid_t> r_config_cmd_pktid; 304 sc_signal<vci_trdid_t> r_config_cmd_trdid;305 314 sc_signal<vci_plen_t> r_config_cmd_plen; 306 315 sc_signal<vci_clen_t> r_config_cmd_clen; … … 311 320 sc_signal<vci_eop_t> r_config_cmd_eop; 312 321 322 TransactionTabIO m_iox_transaction_tab; 323 313 324 /////////////////////////////////// 314 325 // CONFIG_RSP FSM REGISTERS 315 326 /////////////////////////////////// 316 327 sc_signal<int> r_config_rsp_fsm; 328 sc_signal<vci_srcid_t> r_config_rsp_rsrcid; 329 sc_signal<vci_trdid_t> r_config_rsp_rtrdid; 317 330 318 331 /////////////////////////////////// 319 332 // TLB FSM REGISTERS 320 333 /////////////////////////////////// 321 sc_signal<int> r_tlb_fsm; // state register334 sc_signal<int> r_tlb_fsm; // state register 322 335 sc_signal<bool> r_waiting_transaction; // Flag for returning from 323 336 sc_signal<int> r_tlb_miss_type; 324 sc_signal<bool> r_tlb_miss_error; 325 326 sc_signal<vci_addr_t> r_tlb_paddr; 327 sc_signal<uint32_t> r_tlb_pte_flags; 328 sc_signal<uint32_t> r_tlb_pte_ppn; 329 sc_signal<size_t> r_tlb_way; // selected way in tlb330 sc_signal<size_t> r_tlb_set; // selected set in tlb337 sc_signal<bool> r_tlb_miss_error; 338 339 sc_signal<vci_addr_t> r_tlb_paddr; // physical address of pte 340 sc_signal<uint32_t> r_tlb_pte_flags; // pte1 or first word of pte2 341 sc_signal<uint32_t> r_tlb_pte_ppn; // second word of pte2 342 sc_signal<size_t> r_tlb_way; // selected way in tlb 343 sc_signal<size_t> r_tlb_set; // selected set in tlb 331 344 332 345 uint32_t* r_tlb_buf_data; // prefetch buffer for PTEs 333 346 sc_signal<bool> r_tlb_buf_valid; // one valit flag for all PTEs 334 sc_signal<vci_addr_t> r_tlb_buf_tag; // cache line number 335 sc_signal<vci_addr_t> r_tlb_buf_vaddr; // vaddr for first PTE 347 sc_signal<vci_addr_t> r_tlb_buf_tag; // cache line number 348 sc_signal<vci_addr_t> r_tlb_buf_vaddr; // vaddr for first PTE 336 349 sc_signal<bool> r_tlb_buf_big_page; // ??? 337 350 … … 352 365 sc_signal<vci_pktid_t> r_miss_wti_rsp_to_dma_rsp_rpktid; 353 366 354 367 355 368 ///////////////////////////////////////////////////// 356 369 // ALLOCATORS for CONFIG_RSP fifo & DMA_RSP fifo 357 370 ///////////////////////////////////////////////////// 358 sc_signal<bool> r_alloc_fifo_config_rsp_local; 359 360 371 sc_signal<bool> r_alloc_fifo_config_rsp_local; 372 373 361 374 ////////////////////////////////////////////////////////////////// 362 // IOTLB 375 // IOTLB 363 376 ////////////////////////////////////////////////////////////////// 364 377 GenericTlb<vci_addr_t> r_iotlb; 365 366 378 379 367 380 ///////////////////////// 368 381 // FIFOs … … 392 405 GenericFifo<vci_eop_t> m_dma_rsp_reop_fifo; 393 406 GenericFifo<vci_rerror_t> m_dma_rsp_rerror_fifo; 394 407 395 408 // output FIFO to VCI INI port on IOX network (VCI command) 396 409 GenericFifo<vci_addr_t> m_config_cmd_addr_fifo; … … 408 421 GenericFifo<vci_cfixed_t> m_config_cmd_cfixed_fifo; 409 422 GenericFifo<vci_clen_t> m_config_cmd_clen_fifo; 410 411 // output FIFO to VCI TGT port on INT network (VCI response) 423 424 // output FIFO to VCI TGT port on INT network (VCI response) 412 425 GenericFifo<int_data_t> m_config_rsp_data_fifo; 413 426 GenericFifo<vci_srcid_t> m_config_rsp_rsrcid_fifo; … … 416 429 GenericFifo<vci_eop_t> m_config_rsp_reop_fifo; 417 430 GenericFifo<vci_rerror_t> m_config_rsp_rerror_fifo; 418 431 419 432 // output FIFO to VCI_INI port on INT network (VCI command) 420 433 GenericFifo<vci_addr_t> m_miss_wti_cmd_addr_fifo; … … 432 445 GenericFifo<vci_cfixed_t> m_miss_wti_cmd_cfixed_fifo; 433 446 GenericFifo<vci_clen_t> m_miss_wti_cmd_clen_fifo; 434 447 435 448 //////////////////////////////// 436 449 // Activity counters 437 450 //////////////////////////////// 438 451 439 452 uint32_t m_cpt_total_cycles; // total number of cycles 440 453 441 454 // TLB activity counters 442 455 uint32_t m_cpt_iotlb_read; // number of iotlb read 443 456 uint32_t m_cpt_iotlb_miss; // number of iotlb miss 444 457 uint32_t m_cost_iotlb_miss; // number of wait cycles (not treatment itself) 445 uint32_t m_cpt_iotlbmiss_transaction; // number of tlb miss transactions 458 uint32_t m_cpt_iotlbmiss_transaction; // number of tlb miss transactions 446 459 uint32_t m_cost_iotlbmiss_transaction; // cumulated duration tlb miss transactions 447 460 … … 454 467 // FSM activity counters 455 468 // unused on print_stats 456 uint32_t m_cpt_fsm_dma_cmd [32]; 457 uint32_t m_cpt_fsm_dma_rsp [32]; 458 uint32_t m_cpt_fsm_tlb [32]; 459 uint32_t m_cpt_fsm_config_cmd [32]; 460 uint32_t m_cpt_fsm_config_rsp [32]; 469 uint32_t m_cpt_fsm_dma_cmd [32]; 470 uint32_t m_cpt_fsm_dma_rsp [32]; 471 uint32_t m_cpt_fsm_tlb [32]; 472 uint32_t m_cpt_fsm_config_cmd [32]; 473 uint32_t m_cpt_fsm_config_rsp [32]; 461 474 uint32_t m_cpt_fsm_miss_wti_rsp [32]; 462 475 463 476 protected: 464 477 … … 468 481 469 482 VciIoBridge( 470 sc_module_name insname, 471 const soclib::common::MappingTable &mt_ext, // external network 472 const soclib::common::MappingTable &mt_int, // internal network 473 const soclib::common::MappingTable &mt_iox, // iox network 474 const soclib::common::IntTab &int_tgtid, // INT network TGTID 475 const soclib::common::IntTab &int_srcid, // INT network SRCID 476 const soclib::common::IntTab &iox_tgtid, // IOX network TGTID 477 const size_t dcache_words, 478 const size_t iotlb_ways, 479 const size_t iotlb_sets, 480 const uint32_t debug_start_cycle, 481 const bool debug_ok ); 483 sc_module_name insname, 484 const soclib::common::MappingTable &mt_ext, // external network 485 const soclib::common::MappingTable &mt_int, // internal network 486 const soclib::common::MappingTable &mt_iox, // iox network 487 const soclib::common::IntTab &int_tgtid, // INT network TGTID 488 const soclib::common::IntTab &int_srcid, // INT network SRCID 489 const soclib::common::IntTab &iox_tgtid, // IOX network TGTID 490 const soclib::common::IntTab &iox_srcid, // IOX network SRCID 491 const size_t dcache_words, 492 const size_t iotlb_ways, 493 const size_t iotlb_sets, 494 const uint32_t debug_start_cycle, 495 const bool debug_ok ); 482 496 483 497 ~VciIoBridge(); … … 486 500 void clear_stats(); 487 501 void print_trace(size_t mode = 0); 488 502 489 503 490 504 private:
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