Changeset 717 for branches


Ignore:
Timestamp:
Jun 23, 2014, 4:02:53 PM (10 years ago)
Author:
cfuguet
Message:

fault_tolerance/tsar_generic_iob:

  • introducing the vci_iopic component on the IOX interconnect.


  • the input hardware interrupts on cluster(0,0) from the external peripherals have been removed because they are connected to the vci_iopic component.


  • Replacing "ad-hoc" dspin_tsar router by standard dspin_router on the RAM interconnect. To do so, in IO clusters (clusters with IOB) two crossbars are implemented:

+ One for commands which interconnects MEMC and IOB to the

local interface of RAM CMD dspin_router.

+ One for responses which interconnects local interface of RAM

RSP dspin_router to MEMC and IOB.

  • Considering case of mono cluster platform: Only one IOB must be instantiated.
  • Modifying IOX memory segments used by IOX network for routing:


+ bugfix: all segments of IOX interconnect must have

global id = 0.

+ Adding XICU segments with special attribute. This

attribute is used by IOB to determine if a command coming
from external DMA peripheral should be routed
through INT or RAM networks.

+ Using bit 32 of physical address to determine if an

external DMA command should be routed through IOB0
or IOB1.


Location:
branches/fault_tolerance/platform/tsar_generic_iob
Files:
7 edited

Legend:

Unmodified
Added
Removed
  • branches/fault_tolerance/platform/tsar_generic_iob/Makefile

    r658 r717  
    1 SOCLIB_CC := soclib-cc
    2 RM        := rm -rf
    3 CP        := cp -f
    4 MAKE      := make
    5 TARGET    := simul.x
    6 ARGS      ?=
     1ARGS           ?=
     2SOCLIB_CC      := soclib-cc
     3RM             := rm -rf
     4CP             := cp -f
     5MAKE           := make
     6CONFIG_DIR     := $(PWD)/conf
    77
    8 all: $(TARGET) preloader tags
     8TARGET         := simul.x
     9
     10all: $(TARGET) tags
    911
    1012# create simulator
     
    1315SRCS += tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp
    1416INCS := tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h
     17INCS += $(CONFIG_DIR)/hard_config.h
    1518INCS += top.desc
    1619INCS += soclib.conf
    1720
    18 $(TARGET): $(SRCS) $(INCS)
     21$(TARGET): $(SRCS) $(INCS) soclib.conf
    1922        $(SOCLIB_CC) -P -p top.desc -I. -o simul.x
    2023
    2124# create preloader
    2225
    23 MESHSIZE       := 4c1p
    24 PRELOADER_CONF := $(PWD)/conf/preloader_$(MESHSIZE)
    2526PRELOADER_PATH := $(TSARPATH)/trunk/softs/tsar_boot
    26 PRELOADER_ARGS := "PLATFORM_DIR=$(PRELOADER_CONF) USE_DT=0 SOCLIB=1"
     27PRELOADER_ARGS := "PLATFORM_DIR=$(CONFIG_DIR) USE_DT=0 SOCLIB=1"
    2728PRELOADER_NAME ?= soft/soft.elf
    2829
     
    3536# run simulator
    3637
    37 SIMULATOR_ARGS  = -SOFT $(PRELOADER_NAME)
    38 SIMULATOR_ARGS += -DISK soft/disk.dmg
    39 SIMULATOR_ARGS += -XSIZE 2 -YSIZE 2 -NPROCS 1
     38SOFT           ?= $(PRELOADER_NAME)
     39DISK           ?= /dev/null
     40
     41SIMULATOR_ARGS  = -SOFT $(SOFT)
     42SIMULATOR_ARGS += -DISK $(DISK)
    4043SIMULATOR_ARGS += $(ARGS)
    4144
    42 run: $(TARGET) $(PRELOADER_NAME)
     45run: $(TARGET) $(SOFT)
    4346        ./$< $(SIMULATOR_ARGS)
    4447
    45 # create tags file with ctags
     48# create tags file with cscope
     49tags: cscope.out
    4650
    47 tags:
    48         $(SOCLIB_CC) -p top.desc --tags --tags-type=ctags --tags-output=$@
     51cscope.out:
     52        $(SOCLIB_CC) -p top.desc --tags --tags-type=cscope --tags-output=$@
    4953
    5054# clean targets
    5155
    5256clean:
     57        $(SOCLIB_CC) -X
    5358        $(SOCLIB_CC) -x -p top.desc -I.
    54         $(RM) *.o *.x tty* term*
     59        $(RM) *.o *.x mtty_*
    5560
    5661clean-soft:
    57         $(RM) $(PRELOADER_NAME)
     62        $(RM) $(SOFT)
    5863
    5964clean-tags:
     
    6671
    6772
    68 .PHONY: tags preloader clean clean-soft clean-preloader
     73.PHONY: tags simul.x preloader clean clean-soft clean-preloader
    6974
  • branches/fault_tolerance/platform/tsar_generic_iob/soclib.conf

    r652 r717  
     1cflags = config.default.toolchain.cflags \
     2         + ['-Iconf'] \
     3         + ['-DUSE_OPENMP=0'] \
     4#        + ['-ggdb']
     5
    16config.default.toolchain.set(
    2         "cflags", config.default.toolchain.cflags
    3 #       "cflags", config.default.toolchain.cflags + ['-ggdb']
     7    "cflags", cflags
    48)
    59
    610import os
    711tsar_path = os.environ['TSARPATH']
     12config.addDescPath(tsar_path + "/trunk/lib")
     13config.addDescPath(tsar_path + "/trunk/communication")
     14config.addDescPath(tsar_path + "/trunk/modules/dspin_router_tsar")
     15config.addDescPath(tsar_path + "/trunk/modules/vci_io_bridge")
     16config.addDescPath(tsar_path + "/trunk/modules/vci_iox_network")
     17config.addDescPath(tsar_path + "/trunk/modules/vci_block_device_tsar")
    818config.addDescPath(tsar_path + "/branches/fault_tolerance/module")
    919config.addDescPath(tsar_path + "/branches/fault_tolerance/lib")
    10 
  • branches/fault_tolerance/platform/tsar_generic_iob/top.cpp

    r695 r717  
    3838//    (VCI ADDDRESS = 40 bits / VCI DATA width = 64 bits)
    3939//
    40 // The external peripherals IRQs are connected to the XICU component
    41 // in cluster(0,0): therefore, the number of channels for the external
    42 // peripherals (MTTY, MNIC, CDMA) is limited by the number of IRQ ports...
    43 //
    44 // In cluster(0,0), the XICU HWI input ports are connected as follow:
    45 // - IRQ_IN[0]  to IRQ_IN[7]  grounded (reserved for PTI or SWI)
    46 // - IRQ_IN[8]  to IRQ_IN[9]  are connected to 2 NIC_RX channels.
    47 // - IRQ_IN[10] to IRQ_IN[11] are connected to 2 NIC_TX channels.
    48 // - IRQ_IN[12] to IRQ_IN[15] are connected to 4 CDMA channels
    49 // - IRQ_IN[16] to IRQ_IN[30] are connected to 15 TTY channels
    50 // - IRQ_IN[31]               is connected to BDEV
    51 // In other clusters, the XICU HWI input ports are grounded.
     40// The external peripherals IRQs are connected to the XPIC component
     41// in IOX interconnect.
    5242//
    5343// All clusters are identical, but cluster(0,0) and cluster(XMAX-1,YMAX-1)
     
    5949// - It uses two dspin_local_crossbar per cluster to implement the
    6050//   local interconnect correponding to the INT network.
    61 // - It uses two dspin_local_crossbar per cluster to implement the
     51// - It uses three dspin_local_crossbar per cluster to implement the
    6252//   local interconnect correponding to the coherence INT network.
    6353// - It uses two virtual_dspin_router per cluster to implement
     
    6858// - It contains one vci_xicu and one vci_multi_dma per cluster.
    6959// - It contains one vci_simple ram per cluster to model the L3 cache.
    70 //
    71 // The TsarIobCluster component is defined in files
    72 // tsar_iob_cluster.* (with * = cpp, h, sd)
    73 //
    74 // The main hardware parameters must be defined in the hard_config.h file :
    75 // - XMAX        : number of clusters in a row (power of 2)
    76 // - YMAX        : number of clusters in a column (power of 2)
    77 // - CLUSTER_SIZE     : size of the segment allocated to a cluster
    78 // - NB_PROCS_MAX     : number of processors per cluster (power of 2)
    79 // - NB_DMA_CHANNELS  : number of DMA channels per cluster (< 9)
    80 // - NB_TTY_CHANNELS  : number of TTY channels in I/O network (< 16)
    81 // - NB_NIC_CHANNELS  : number of NIC channels in I/O network (< 9)
    82 //
    83 // Some secondary hardware parameters must be defined in this top.cpp file:
    84 // - XRAM_LATENCY     : external ram latency
    85 // - MEMC_WAYS        : L2 cache number of ways
    86 // - MEMC_SETS        : L2 cache number of sets
    87 // - L1_IWAYS
    88 // - L1_ISETS
    89 // - L1_DWAYS
    90 // - L1_DSETS
    91 // - FBUF_X_SIZE      : width of frame buffer (pixels)
    92 // - FBUF_Y_SIZE      : heigth of frame buffer (lines)
    93 // - BDEV_SECTOR_SIZE : block size for block drvice
    94 // - BDEV_IMAGE_NAME  : file pathname for block device
    95 // - NIC_RX_NAME      : file pathname for NIC received packets
    96 // - NIC_TX_NAME      : file pathname for NIC transmited packets
    97 // - NIC_TIMEOUT      : max number of cycles before closing a container
     60// - It contains one vci_simple_rom per cluster which can be used for a
     61//   distributed boot.
     62// - It contains one vci_multi_tty per cluster for debug purposes (number
     63//   of channels can be 0). This TTY is mostly useful when using distributed
     64//   boot.
    9865//
    9966// General policy for 40 bits physical address decoding:
    10067// All physical segments base addresses are multiple of 1 Mbytes
    10168// (=> the 24 LSB bits = 0, and the 16 MSB bits define the target)
    102 // The (x_width + y_width) MSB bits (left aligned) define
    103 // the cluster index, and the LADR bits define the local index:
     69// The (x_width + y_width) MSB bits define the cluster index, and the
     70// LADR bits define the local index:
    10471//      | X_ID  | Y_ID  |---| LADR |     OFFSET          |
    10572//      |x_width|y_width|---|  8   |       24            |
     
    12996#include "vci_block_device_tsar.h"
    13097#include "vci_framebuffer.h"
     98#include "vci_iopic.h"
    13199#include "vci_iox_network.h"
    132100
     
    215183// All initiators are in the same indexing space (14 bits).
    216184// The SRCID is structured in two fields:
    217 // - The 10 MSB bits define the cluster index (left aligned)
     185// - The 10 MSB bits define the cluster index
    218186// - The 4  LSB bits define the local index.
    219187// Two different initiators cannot have the same SRCID, but a given
     
    234202#define MDMA_LOCAL_SRCID 0x8
    235203#define IOBX_LOCAL_SRCID 0x9
    236 #define MEMC_LOCAL_SRCID 0xA
    237 #define CDMA_LOCAL_SRCID 0xE // hard-coded in dspin_tsar
    238 #define BDEV_LOCAL_SRCID 0xF // hard-coded in dspin_tsar
     204#define CDMA_LOCAL_SRCID 0xA
     205#define BDEV_LOCAL_SRCID 0xB
     206#define XPIC_LOCAL_SRCID 0xC
    239207
    240208///////////////////////////////////////////////////////////////////////
    241 //     TGT_ID and INI_ID port indexing for I0X local interconnect
     209//     TGT_ID and INI_ID port indexing for IOX local interconnect
    242210///////////////////////////////////////////////////////////////////////
    243211
    244 #define IOX_IOB0_TGT_ID 0 // don't change this value
    245 #define IOX_IOB1_TGT_ID 1 // don't change this value
    246 #define IOX_FBUF_TGT_ID 2
    247 #define IOX_BDEV_TGT_ID 3
    248 #define IOX_MNIC_TGT_ID 4
    249 #define IOX_CDMA_TGT_ID 5
    250 #define IOX_MTTY_TGT_ID 6
    251 
    252 #define IOX_IOB0_INI_ID 0 // Don't change this value
    253 #define IOX_IOB1_INI_ID 1 // Don't change this value
    254 #define IOX_BDEV_INI_ID 2
    255 #define IOX_CDMA_INI_ID 3
     212#define IOX_FBUF_TGT_ID 0
     213#define IOX_BDEV_TGT_ID 1
     214#define IOX_MNIC_TGT_ID 2
     215#define IOX_CDMA_TGT_ID 3
     216#define IOX_MTTY_TGT_ID 4
     217#define IOX_XPIC_TGT_ID 5
     218#define IOX_IOB0_TGT_ID 6
     219#define IOX_IOB1_TGT_ID 7
     220
     221#define IOX_BDEV_INI_ID 0
     222#define IOX_CDMA_INI_ID 1
     223#define IOX_XPIC_INI_ID 2
     224#define IOX_IOB0_INI_ID 3
     225#define IOX_IOB1_INI_ID 4
    256226
    257227////////////////////////////////////////////////////////////////////////
     
    267237   char     nic_tx_name[256] = NIC_TX_NAME;       // path: tx packets file
    268238   ssize_t  threads_nr       = 1;                 // simulator's threads
    269    bool     debug_ok         = false;             // trace activated
     239   bool     debug_ok         = false;
    270240   size_t   debug_period     = 1;                 // trace period
    271241   size_t   debug_memc_id    = 0xFFFFFFFF;        // idx of traced memc
     
    274244   uint32_t debug_from       = 0;                 // trace start cycle
    275245   uint32_t frozen_cycles    = MAX_FROZEN_CYCLES; // monitoring frozen procs
     246   bool     distboot         = false;             // distributed boot
    276247   const size_t block_size   = BDEV_SECTOR_SIZE;  // disk block size
    277248   const size_t x_size       = X_SIZE;
     
    296267         }
    297268         if ((strcmp(argv[n],"-DEBUG") == 0) && ((n+1) < argc) ) {
    298             debug_ok   = true;
     269            debug_ok = true;
    299270            debug_from = strtol(argv[n+1], NULL, 0);
    300271            continue;
     
    334305            continue;
    335306         }
    336 
    337          std::cout << "   Arguments are (key,value) couples.\n"
    338             << "   The order is not important.\n"
    339             << "   Accepted arguments are :\n\n"
    340             << "     -NCYCLES number of simulated_cycles\n"
    341             << "     -SOFT    pathname for embedded soft\n"
    342             << "     -DISK    pathname for disk image\n"
    343             << "     -DEBUG   debug start cycle\n"
    344             << "     -MEMCID  index of memc to trace\n"
    345             << "     -IOB     debug IOBs if non_zero_value\n\n"
    346             << "     -PROCID  index of proc to trace\n"
    347             << "     -THREADS simulator's threads number\n"
    348             << "     -FROZEN  max number of frozen cycles\n"
    349             << "     -PERIOD  number of cycles between trace\n\n";
     307         if ((strcmp(argv[n], "-DISTBOOT") == 0)) {
     308            distboot = true;
     309            continue;
     310         }
     311
     312         std::cout
     313            << "\nArguments are (key,value) couples."
     314            << "\nThe order is not important."
     315            << "\nAccepted arguments are :\n"
     316            << "\n    -NCYCLES   number of simulated_cycles"
     317            << "\n    -SOFT      pathname for embedded soft"
     318            << "\n    -DISK      pathname for disk image"
     319            << "\n    -DEBUG     debug start cycle"
     320            << "\n    -MEMCID    index of memc to trace"
     321            << "\n    -IOB       debug IOBs if non_zero_value"
     322            << "\n    -PROCID    index of proc to trace"
     323            << "\n    -THREADS   simulator's threads number"
     324            << "\n    -FROZEN    max number of frozen cycles"
     325            << "\n    -PERIOD    number of cycles between trace"
     326            << "\n    -DISTBOOT  use distributed boot ROM"
     327            << "\n               (processors physical address extention is"
     328            << "\n               initialized with local cluster id)"
     329            << std::endl;
     330
    350331         exit(0);
    351332      }
     
    358339         "The NB_NIC_CHANNELS parameter must be 1" );
    359340
    360    std::cout << std::endl;
    361    std::cout << " - X_SIZE          = " << x_size          << std::endl;
    362    std::cout << " - Y_SIZE          = " << y_size          << std::endl;
    363    std::cout << " - NB_PROCS        = " << NB_PROCS        << std::endl;
    364    std::cout << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl;
    365    std::cout << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl;
    366    std::cout << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl;
    367    std::cout << " - MEMC_WAYS       = " << MEMC_WAYS       << std::endl;
    368    std::cout << " - MEMC_SETS       = " << MEMC_SETS       << std::endl;
    369    std::cout << " - RAM_LATENCY     = " << XRAM_LATENCY    << std::endl;
    370    std::cout << " - MAX_FROZEN      = " << frozen_cycles   << std::endl;
     341   assert( (x_size > 0) and (y_size > 0) and
     342         "Number of clusters on X and Y must be at least 1" );
     343
     344   std::cout << "\n- X_SIZE          = " << x_size
     345             << "\n- Y_SIZE          = " << y_size
     346             << "\n- NB_PROCS        = " << NB_PROCS
     347             << "\n- NB_DMA_CHANNELS = " << NB_DMA_CHANNELS
     348             << "\n- NB_TTY_CHANNELS = " << NB_TTY_CHANNELS
     349             << "\n- NB_NIC_CHANNELS = " << NB_NIC_CHANNELS
     350             << "\n- MEMC_WAYS       = " << MEMC_WAYS
     351             << "\n- MEMC_SETS       = " << MEMC_SETS
     352             << "\n- RAM_LATENCY     = " << XRAM_LATENCY
     353             << "\n- MAX_FROZEN      = " << frozen_cycles
     354             << "\n- DISTBOOT        = " << distboot
     355             << std::endl;
    371356
    372357   std::cout << std::endl;
     
    409394   size_t cluster_iob0 = cluster(0, 0);
    410395   size_t cluster_iob1 = cluster(x_size - 1, y_size - 1);
     396
     397   // using mono cluster configuration (only one IO bridge) ?
     398   bool is_mono_cluster = ((x_size == 1) && (y_size == 1));
    411399
    412400   /////////////////////////////////////////////////////////////////////
     
    507495                     IntTab(cluster(x,y), INT_IOBX_TGT_ID),
    508496                     not cacheable));
     497
     498            std::ostringstream spic;
     499            sdma << "int_seg_xpic_" << x << "_" << y;
     500            maptab_int.add(Segment(spic.str(), XPIC_BASE+offset, XPIC_SIZE,
     501                     IntTab(cluster(x,y), INT_IOBX_TGT_ID),
     502                     not cacheable));
    509503         }
    510504
     
    515509               IntTab(cluster(x,y), INT_MDMA_INI_ID));
    516510         maptab_int.srcid_map(IntTab(cluster(x,y), IOBX_LOCAL_SRCID),
     511               IntTab(cluster(x,y), INT_IOBX_INI_ID));
     512         maptab_int.srcid_map(IntTab(cluster(x,y), XPIC_LOCAL_SRCID),
    517513               IntTab(cluster(x,y), INT_IOBX_INI_ID));
    518514
     
    535531   MappingTable maptab_ram(
    536532         vci_address_width,
    537          IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH),
     533         IntTab(X_WIDTH + Y_WIDTH, 0),
    538534         IntTab(X_WIDTH + Y_WIDTH, vci_param_int::S - X_WIDTH - Y_WIDTH),
    539535         0x00FF000000);
     
    547543         sxram << "ext_seg_xram_" << x << "_" << y;
    548544         maptab_ram.add(Segment(sxram.str(), XRAM_BASE+offset, XRAM_SIZE,
    549                   IntTab(cluster(x,y), 0), false));
     545                  IntTab(cluster(x,y), RAM_XRAM_TGT_ID), false));
    550546      }
    551547   }
     
    557553   maptab_ram.srcid_map(IntTab(cluster_iob0, CDMA_LOCAL_SRCID),
    558554         IntTab(cluster_iob0, RAM_IOBX_INI_ID));
    559    maptab_ram.srcid_map(IntTab(cluster_iob1, CDMA_LOCAL_SRCID),
    560          IntTab(cluster_iob1, RAM_IOBX_INI_ID));
    561555   maptab_ram.srcid_map(IntTab(cluster_iob0, BDEV_LOCAL_SRCID),
    562556         IntTab(cluster_iob0, RAM_IOBX_INI_ID));
    563    maptab_ram.srcid_map(IntTab(cluster_iob1, BDEV_LOCAL_SRCID),
    564          IntTab(cluster_iob1, RAM_IOBX_INI_ID));
    565    maptab_ram.srcid_map(IntTab(cluster_iob1, MEMC_LOCAL_SRCID),
    566          IntTab(cluster_iob1, RAM_MEMC_INI_ID));
     557   maptab_ram.srcid_map(IntTab(cluster_iob0, XPIC_LOCAL_SRCID),
     558         IntTab(cluster_iob0, RAM_IOBX_INI_ID));
     559   maptab_ram.srcid_map(IntTab(cluster_iob0, RAM_MEMC_INI_ID),
     560         IntTab(cluster_iob0, RAM_MEMC_INI_ID));
     561
     562   if (not is_mono_cluster) {
     563      maptab_ram.srcid_map(IntTab(cluster_iob1, CDMA_LOCAL_SRCID),
     564            IntTab(cluster_iob1, RAM_IOBX_INI_ID));
     565      maptab_ram.srcid_map(IntTab(cluster_iob1, BDEV_LOCAL_SRCID),
     566            IntTab(cluster_iob1, RAM_IOBX_INI_ID));
     567      maptab_ram.srcid_map(IntTab(cluster_iob1, XPIC_LOCAL_SRCID),
     568            IntTab(cluster_iob1, RAM_IOBX_INI_ID));
     569      maptab_ram.srcid_map(IntTab(cluster_iob1, RAM_MEMC_INI_ID),
     570            IntTab(cluster_iob1, RAM_MEMC_INI_ID));
     571   }
    567572
    568573   std::cout << "RAM network " << maptab_ram << std::endl;
     
    575580   // - 8 targets (IOB0, IOB1, BDEV, CDMA, MTTY, FBUF, BROM, MNIC)
    576581   ///////////////////////////////////////////////////////////////////////
     582   
     583   const size_t iox_addr_drop_bits = X_WIDTH + Y_WIDTH - 1;
     584   const size_t iox_addr_decd_bits = 16 - X_WIDTH - Y_WIDTH + 1;
    577585   MappingTable maptab_iox(
    578586         vci_address_width,
    579          IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH),
    580          IntTab(X_WIDTH + Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH),
     587         IntTab(iox_addr_drop_bits, iox_addr_decd_bits),
     588         IntTab(X_WIDTH + Y_WIDTH , vci_param_ext::S - X_WIDTH - Y_WIDTH),
    581589         0x00FF000000);
    582590
    583    // compute base addresses for cluster_iob0 and cluster_iob1
     591
     592   // Each peripheral can be accessed through two segments,
     593   // depending on the used IOB (IOB0 or IOB1).
     594
    584595   uint64_t iob0_base = ((uint64_t)cluster_iob0)
    585596      << (vci_address_width - X_WIDTH - Y_WIDTH);
    586    uint64_t iob1_base = ((uint64_t)cluster_iob1)
    587       << (vci_address_width - X_WIDTH - Y_WIDTH);
    588 
    589    // Each peripheral can be accessed through two segments,
    590    // depending on the used IOB (IOB0 or IOB1).
     597
    591598   maptab_iox.add(Segment("iox_seg_mtty_0", XTTY_BASE + iob0_base, XTTY_SIZE,
    592             IntTab(cluster_iob0, IOX_MTTY_TGT_ID), false));
    593    maptab_iox.add(Segment("iox_seg_mtty_1", XTTY_BASE + iob1_base, XTTY_SIZE,
    594             IntTab(cluster_iob1, IOX_MTTY_TGT_ID), false));
     599            IntTab(0, IOX_MTTY_TGT_ID), false));
    595600   maptab_iox.add(Segment("iox_seg_fbuf_0", FBUF_BASE + iob0_base, FBUF_SIZE,
    596             IntTab(cluster_iob0, IOX_FBUF_TGT_ID), false));
    597    maptab_iox.add(Segment("iox_seg_fbuf_1", FBUF_BASE + iob1_base, FBUF_SIZE,
    598             IntTab(cluster_iob1, IOX_FBUF_TGT_ID), false));
     601            IntTab(0, IOX_FBUF_TGT_ID), false));
    599602   maptab_iox.add(Segment("iox_seg_bdev_0", BDEV_BASE + iob0_base, BDEV_SIZE,
    600             IntTab(cluster_iob0, IOX_BDEV_TGT_ID), false));
    601    maptab_iox.add(Segment("iox_seg_bdev_1", BDEV_BASE + iob1_base, BDEV_SIZE,
    602             IntTab(cluster_iob1, IOX_BDEV_TGT_ID), false));
     603            IntTab(0, IOX_BDEV_TGT_ID), false));
    603604   maptab_iox.add(Segment("iox_seg_mnic_0", MNIC_BASE + iob0_base, MNIC_SIZE,
    604             IntTab(cluster_iob0, IOX_MNIC_TGT_ID), false));
    605    maptab_iox.add(Segment("iox_seg_mnic_1", MNIC_BASE + iob1_base, MNIC_SIZE,
    606             IntTab(cluster_iob1, IOX_MNIC_TGT_ID), false));
     605            IntTab(0, IOX_MNIC_TGT_ID), false));
    607606   maptab_iox.add(Segment("iox_seg_cdma_0", CDMA_BASE + iob0_base, CDMA_SIZE,
    608             IntTab(cluster_iob0, IOX_CDMA_TGT_ID), false));
    609    maptab_iox.add(Segment("iox_seg_cdma_1", CDMA_BASE + iob1_base, CDMA_SIZE,
    610             IntTab(cluster_iob1, IOX_CDMA_TGT_ID), false));
    611 
    612    // Each physical RAM can be accessed through IOB0, or through IOB1.
    613    // if IOMMU is not activated, addresses are 40 bits (physical addresses),
    614    // and the choice depends on on address bit A[39].
    615    // if IOMMU is activated the addresses use only 32 bits (virtual
    616    // addresses), and the choice depends on address bit A[31].
     607            IntTab(0, IOX_CDMA_TGT_ID), false));
     608   maptab_iox.add(Segment("iox_seg_xpic_0", XPIC_BASE + iob0_base, XPIC_SIZE,
     609            IntTab(0, IOX_XPIC_TGT_ID), false));
     610
     611   if (not is_mono_cluster) {
     612      uint64_t iob1_base = ((uint64_t)cluster_iob1)
     613         << (vci_address_width - X_WIDTH - Y_WIDTH);
     614
     615      maptab_iox.add(Segment("iox_seg_mtty_1", XTTY_BASE + iob1_base,
     616               XTTY_SIZE, IntTab(0, IOX_MTTY_TGT_ID), false));
     617      maptab_iox.add(Segment("iox_seg_fbuf_1", FBUF_BASE + iob1_base,
     618               FBUF_SIZE, IntTab(0, IOX_FBUF_TGT_ID), false));
     619      maptab_iox.add(Segment("iox_seg_bdev_1", BDEV_BASE + iob1_base,
     620               BDEV_SIZE, IntTab(0, IOX_BDEV_TGT_ID), false));
     621      maptab_iox.add(Segment("iox_seg_mnic_1", MNIC_BASE + iob1_base,
     622               MNIC_SIZE, IntTab(0, IOX_MNIC_TGT_ID), false));
     623      maptab_iox.add(Segment("iox_seg_cdma_1", CDMA_BASE + iob1_base,
     624               CDMA_SIZE, IntTab(0, IOX_CDMA_TGT_ID), false));
     625      maptab_iox.add(Segment("iox_seg_xpic_1", XPIC_BASE + iob1_base,
     626               XPIC_SIZE, IntTab(0, IOX_XPIC_TGT_ID), false));
     627   }
     628
     629   ///////////////////////////////////////////////////////////////////////////
     630   // - For external DMA peripherals, each physical RAM and replicated
     631   //   XICU can be accessed through IOB0, or through IOB1 depending on address
     632   //   bit A[32] (0 => IOB0, 1 => IOB1).
     633   //
     634   // NOTE: the special attribute in the XICU segments is used by the IOB to
     635   //       route commands through the INT network. The commands on not special
     636   //       segments (RAM) are routed by the IOB through the RAM network
     637   //
     638   // NOTE: The IOX interconnect is implemented as a local interconnect because
     639   //       the global bits need to be dropped, but no locality check is
     640   //       performed
     641   ///////////////////////////////////////////////////////////////////////////
     642
    617643   for (size_t x = 0; x < x_size; x++) {
    618644      for (size_t y = 0; y < y_size ; y++) {
    619          uint64_t offset = static_cast<uint64_t>(cluster(x,y))
     645         const bool special   = true;
     646         const bool cacheable = true;
     647
     648         const uint64_t offset = static_cast<uint64_t>(cluster(x,y))
    620649            << (vci_address_width - X_WIDTH - Y_WIDTH);
    621650
    622          // send command to XRAM through IOB0
    623          if ( x < (x_size/2) ) {
    624             std::ostringstream siob0;
    625             siob0 << "iox_seg_xram_" << x << "_" << y;
    626             maptab_iox.add(Segment(siob0.str(),
    627                      XRAM_BASE + offset, XRAM_SIZE,
    628                      IntTab(cluster_iob0,IOX_IOB0_TGT_ID),
    629                      false));
    630          }
    631          // send command to XRAM through IOB1
    632          else {
    633             std::ostringstream siob1;
    634             siob1 << "iox_seg_xram_" << x << "_" << y;
    635             maptab_iox.add(Segment(siob1.str(),
    636                      XRAM_BASE + offset, XRAM_SIZE,
    637                      IntTab(cluster_iob1,IOX_IOB1_TGT_ID),
    638                      false));
     651         const uint64_t xicu_base = XICU_BASE + offset;
     652         if ( (y & 0x1) == 0 ) {
     653            // segments mapped to IOB0
     654            std::ostringstream sxcu0;
     655            sxcu0 << "iox_seg_xcu0_" << x << "_" << y;
     656            maptab_iox.add(Segment(sxcu0.str(), xicu_base, XICU_SIZE,
     657                           IntTab(0, IOX_IOB0_TGT_ID), not cacheable, special));
     658
     659            std::ostringstream sram0;
     660            sram0 << "iox_seg_ram0_" << x << "_" << y;
     661            maptab_iox.add(Segment(sram0.str(), offset, XICU_BASE,
     662                           IntTab(0, IOX_IOB0_TGT_ID), not cacheable, not special));
     663         } else {
     664            // segments mapped to IOB1
     665            std::ostringstream sxcu1;
     666            sxcu1 << "iox_seg_xcu1_" << x << "_" << y;
     667            maptab_iox.add(Segment(sxcu1.str(), xicu_base | (1ULL<<32), XICU_SIZE,
     668                           IntTab(0, IOX_IOB1_TGT_ID), not cacheable, special));
     669
     670            std::ostringstream sram1;
     671            sram1 << "iox_seg_ram1_" << x << "_" << y;
     672            maptab_iox.add(Segment(sram1.str(), offset | (1ULL<<32), XICU_BASE,
     673                           IntTab(0, IOX_IOB1_TGT_ID), not cacheable, not special));
    639674         }
    640675      }
    641676   }
    642    // useful when IOMMU activated
    643    //maptab_iox.add(Segment("iox_seg_xram", 0xc0000000, 0x40000000,
    644    //                       IntTab(cluster_iob1,IOX_IOB1_TGT_ID), false));
    645677
    646678   // This define the mapping between the initiators (identified by the SRCID)
    647679   // and the port index on the IOX local interconnect.
    648    // External initiator have two alias SRCID (iob0 / iob1 access)
    649 
    650    maptab_iox.srcid_map(IntTab(cluster_iob0, CDMA_LOCAL_SRCID),
    651          IntTab(cluster_iob0, IOX_CDMA_INI_ID));
    652    maptab_iox.srcid_map(IntTab(cluster_iob1, CDMA_LOCAL_SRCID),
    653          IntTab(cluster_iob1, IOX_CDMA_INI_ID));
    654    maptab_iox.srcid_map(IntTab(cluster_iob0, BDEV_LOCAL_SRCID),
    655          IntTab(cluster_iob0, IOX_BDEV_INI_ID));
    656    maptab_iox.srcid_map(IntTab(cluster_iob1, BDEV_LOCAL_SRCID),
    657          IntTab(cluster_iob0, IOX_BDEV_INI_ID));
    658 
    659    for (size_t x = 0; x < x_size; x++) {
    660       for (size_t y = 0; y < y_size ; y++) {
    661          size_t iob = (x < (x_size / 2)) ? IOX_IOB0_INI_ID : IOX_IOB1_INI_ID;
    662 
    663          for (size_t p = 0 ; p < NB_PROCS ; p++) {
    664             maptab_iox.srcid_map(IntTab(cluster(x,y), PROC_LOCAL_SRCID + p),
    665                   IntTab(cluster(x,y), iob));
    666          }
    667          maptab_iox.srcid_map(IntTab( cluster(x,y), MDMA_LOCAL_SRCID),
    668                IntTab( cluster(x,y), IOX_IOB0_INI_ID));
    669       }
     680
     681   maptab_iox.srcid_map(IntTab(0, CDMA_LOCAL_SRCID),
     682                        IntTab(0, IOX_CDMA_INI_ID));
     683   maptab_iox.srcid_map(IntTab(0, BDEV_LOCAL_SRCID),
     684                        IntTab(0, IOX_BDEV_INI_ID));
     685   maptab_iox.srcid_map(IntTab(0, XPIC_LOCAL_SRCID),
     686                        IntTab(0, IOX_XPIC_INI_ID));
     687   maptab_iox.srcid_map(IntTab(0, IOX_IOB0_INI_ID),
     688                        IntTab(0, IOX_IOB0_INI_ID));
     689
     690   if (not is_mono_cluster) {
     691      maptab_iox.srcid_map(IntTab(0, IOX_IOB1_INI_ID),
     692                           IntTab(0, IOX_IOB1_INI_ID));
    670693   }
    671694
     
    697720   VciSignals<vci_param_ext> signal_vci_ini_bdev("signal_vci_ini_bdev");
    698721   VciSignals<vci_param_ext> signal_vci_ini_cdma("signal_vci_ini_cdma");
     722   VciSignals<vci_param_ext> signal_vci_ini_xpic("signal_vci_ini_xpic");
    699723
    700724   VciSignals<vci_param_ext> signal_vci_tgt_iob0("signal_vci_tgt_iob0");
     
    705729   VciSignals<vci_param_ext> signal_vci_tgt_bdev("signal_vci_tgt_bdev");
    706730   VciSignals<vci_param_ext> signal_vci_tgt_cdma("signal_vci_tgt_cdma");
     731   VciSignals<vci_param_ext> signal_vci_tgt_xpic("signal_vci_tgt_xpic");
    707732
    708733   // Horizontal inter-clusters INT network DSPIN
     
    807832      << std::endl;
    808833
     834   const size_t nb_iox_initiators = (not is_mono_cluster) ? 5 : 4;
     835   const size_t nb_iox_targets = (not is_mono_cluster) ? 8 : 7;
     836
    809837   // IOX network
    810838   VciIoxNetwork<vci_param_ext>* iox_network;
    811839   iox_network = new VciIoxNetwork<vci_param_ext>("iox_network",
    812840         maptab_iox,
    813          7,   // number of targets
    814          4 ); // number of initiators
     841         nb_iox_targets,      // number of targets
     842         nb_iox_initiators ); // number of initiators
    815843
    816844   // Network Controller
     
    853881         IntTab(0, IOX_CDMA_TGT_ID),
    854882         64,  // burst size (bytes)
    855          2 * NB_NIC_CHANNELS);
     883         NB_CMA_CHANNELS);
     884
    856885   // Multi-TTY controller
    857886   std::vector<std::string> vect_names;
     
    868897         vect_names);
    869898
     899   // IOPIC
     900   VciIopic<vci_param_ext>* xpic;
     901   xpic = new VciIopic<vci_param_ext>( "xpic",
     902                                       maptab_iox,
     903                                       IntTab(0, XPIC_LOCAL_SRCID),
     904                                       IntTab(0, IOX_XPIC_TGT_ID),
     905                                       32 );        // number of input HWI
     906
     907
    870908   TsarIobClusterType* clusters[x_size][y_size];
    871909
     
    891929            sc << "cluster_" << x << "_" << y;
    892930
    893             bool memc_debug =
    894                debug_ok && (cluster(x,y) == debug_memc_id);
    895             bool proc_debug =
    896                debug_ok && (cluster(x,y) == (debug_proc_id / NB_PROCS));
     931            bool memc_debug = (cluster(x,y) == debug_memc_id);
     932            bool proc_debug = (cluster(x,y) == (debug_proc_id / NB_PROCS));
     933
     934            bool is_io0 = (cluster(x,y) == cluster_iob0);
     935            bool is_io1 = (cluster(x,y) == cluster_iob1);
     936            bool is_io = is_io0 || is_io1;
     937
     938            IntTab iox_iob_tgtid =
     939               IntTab(0, is_io0 ? IOX_IOB0_TGT_ID : IOX_IOB1_TGT_ID);
     940            IntTab iox_iob_srcid =
     941               IntTab(0, is_io0 ? IOX_IOB0_INI_ID : IOX_IOB1_INI_ID);
    897942
    898943            TsarIobClusterType::ClusterParams params = {
     
    905950               .mt_ext            = maptab_ram,
    906951               .mt_iox            = maptab_iox,
     952
     953               .is_io             = is_io,
     954               .iox_iob_tgtid     = iox_iob_tgtid,
     955               .iox_iob_srcid     = iox_iob_srcid,
    907956
    908957               .memc_ways         = MEMC_WAYS,
     
    916965               .loader            = loader,
    917966
     967               .distboot          = distboot,
     968
    918969               .frozen_cycles     = frozen_cycles,
    919970               .debug_start_cycle = debug_from,
    920                .memc_debug_ok     = memc_debug, 
    921                .proc_debug_ok     = proc_debug, 
    922                .iob_debug_ok      = debug_ok and debug_iob
     971               .memc_debug_ok     = memc_debug,
     972               .proc_debug_ok     = proc_debug,
     973               .iob_debug_ok      = debug_iob
    923974            };
    924975
     
    942993   iox_network->p_clk                     (signal_clk);
    943994   iox_network->p_resetn                  (signal_resetn);
    944    iox_network->p_to_ini[IOX_IOB0_INI_ID] (signal_vci_ini_iob0);
    945    iox_network->p_to_ini[IOX_IOB1_INI_ID] (signal_vci_ini_iob1);
    946995   iox_network->p_to_ini[IOX_BDEV_INI_ID] (signal_vci_ini_bdev);
    947996   iox_network->p_to_ini[IOX_CDMA_INI_ID] (signal_vci_ini_cdma);
    948    iox_network->p_to_tgt[IOX_IOB0_TGT_ID] (signal_vci_tgt_iob0);
    949    iox_network->p_to_tgt[IOX_IOB1_TGT_ID] (signal_vci_tgt_iob1);
     997   iox_network->p_to_ini[IOX_XPIC_INI_ID] (signal_vci_ini_xpic);
     998   iox_network->p_to_ini[IOX_IOB0_INI_ID] (signal_vci_ini_iob0);
    950999   iox_network->p_to_tgt[IOX_MTTY_TGT_ID] (signal_vci_tgt_mtty);
    9511000   iox_network->p_to_tgt[IOX_FBUF_TGT_ID] (signal_vci_tgt_fbuf);
     
    9531002   iox_network->p_to_tgt[IOX_BDEV_TGT_ID] (signal_vci_tgt_bdev);
    9541003   iox_network->p_to_tgt[IOX_CDMA_TGT_ID] (signal_vci_tgt_cdma);
     1004   iox_network->p_to_tgt[IOX_XPIC_TGT_ID] (signal_vci_tgt_xpic);
     1005   iox_network->p_to_tgt[IOX_IOB0_TGT_ID] (signal_vci_tgt_iob0);
     1006
     1007   if (not is_mono_cluster) {
     1008      iox_network->p_to_ini[IOX_IOB1_INI_ID] (signal_vci_ini_iob1);
     1009      iox_network->p_to_tgt[IOX_IOB1_TGT_ID] (signal_vci_tgt_iob1);
     1010   }
    9551011
    9561012   // BDEV connexion
    957    bdev->p_clk    (signal_clk);
    958    bdev->p_resetn (signal_resetn);
    959    bdev->p_irq    (signal_irq_bdev);
    960 
    961    // For AHCI
    962    // bdev->p_channel_irq[0]                             (signal_irq_bdev);
    963 
     1013   bdev->p_clk           (signal_clk);
     1014   bdev->p_resetn        (signal_resetn);
     1015   bdev->p_irq           (signal_irq_bdev);
    9641016   bdev->p_vci_target    (signal_vci_tgt_bdev);
    9651017   bdev->p_vci_initiator (signal_vci_ini_bdev);
     
    10011053   cdma->p_vci_target    (signal_vci_tgt_cdma);
    10021054   cdma->p_vci_initiator (signal_vci_ini_cdma);
    1003    for ( size_t i=0 ; i<(NB_NIC_CHANNELS*2) ; i++) {
     1055   for ( size_t i=0 ; i<NB_CMA_CHANNELS ; i++) {
    10041056      cdma->p_irq[i]    (signal_irq_cdma[i]);
    10051057   }
     
    10071059   std::cout << "  - CDMA connected" << std::endl;
    10081060
    1009    // IRQ connexions from external peripherals (cluster_iob0 only)
    1010    // IRQ_MNIC_RX  -> IRQ[08] to IRQ[09]
    1011    // IRQ_MNIC_TX  -> IRQ[10] to IRQ[11]
    1012    // IRQ_CDMA     -> IRQ[12] to IRQ[15]
    1013    // IRQ_MTTY     -> IRQ[16] to IRQ[30]
    1014    // IRQ_BDEV     -> IRQ[31]
    1015 
    1016    size_t mx = 16 + NB_TTY_CHANNELS;
    1017    for ( size_t n=0 ; n<32 ; n++ ) {
    1018       if      ( n < 8  ) (*clusters[0][0]->p_irq[n]) (signal_irq_false);
    1019       else if ( n < 10 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false);
    1020       else if ( n < 12 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false);
    1021       else if ( n < 16 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false);
    1022       else if ( n < mx ) (*clusters[0][0]->p_irq[n]) (signal_irq_mtty[n-16]);
    1023       else if ( n < 31 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false);
    1024       else               (*clusters[0][0]->p_irq[n]) (signal_irq_bdev);
    1025    }
     1061   // XPIC connexion
     1062   xpic->p_clk           (signal_clk);
     1063   xpic->p_resetn        (signal_resetn);
     1064   xpic->p_vci_target    (signal_vci_tgt_xpic);
     1065   xpic->p_vci_initiator (signal_vci_ini_xpic);
     1066   for ( size_t i=0 ; i<32 ; i++)
     1067   {
     1068      if      (i < NB_NIC_CHANNELS)   xpic->p_hwi[i] (signal_irq_mnic_rx[i]);
     1069      else if (i < 2)                 xpic->p_hwi[i] (signal_irq_false);
     1070      else if (i < 2+NB_NIC_CHANNELS) xpic->p_hwi[i] (signal_irq_mnic_tx[i-2]);
     1071      else if (i < 4)                 xpic->p_hwi[i] (signal_irq_false);
     1072      else if (i < 4+NB_CMA_CHANNELS) xpic->p_hwi[i] (signal_irq_cdma[i-4]);
     1073      else if (i < 8)                 xpic->p_hwi[i] (signal_irq_false);
     1074      else if (i < 9)                 xpic->p_hwi[i] (signal_irq_bdev);
     1075      else if (i < 9+NB_TTY_CHANNELS) xpic->p_hwi[i] (signal_irq_mtty[i-9]);
     1076      else                            xpic->p_hwi[i] (signal_irq_false);
     1077   }
     1078
     1079   std::cout << "  - XPIC connected" << std::endl;
    10261080
    10271081   // IOB0 cluster connexion to IOX network
     
    10301084
    10311085   // IOB1 cluster connexion to IOX network
    1032    (*clusters[x_size-1][y_size-1]->p_vci_iob_iox_ini) (signal_vci_ini_iob1);
    1033    (*clusters[x_size-1][y_size-1]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob1);
     1086   if (not is_mono_cluster) {
     1087      (*clusters[x_size-1][y_size-1]->p_vci_iob_iox_ini) (signal_vci_ini_iob1);
     1088      (*clusters[x_size-1][y_size-1]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob1);
     1089   }
    10341090
    10351091   // All clusters Clock & RESET connexions
     
    11451201   // East & West boundary cluster connections
    11461202   for (size_t y = 0; y < y_size; y++) {
     1203      // L1-L2 cmd network boundary connections
    11471204      for (size_t k = 0; k < 3; k++) {
    11481205         clusters[0][y]->p_dspin_int_cmd_in[WEST][k](
     
    11561213      }
    11571214
     1215      // L1-L2 rsp network boundary connections
    11581216      for (size_t k = 0; k < 2; k++) {
    11591217         clusters[0][y]->p_dspin_int_rsp_in[WEST][k](
     
    11671225      }
    11681226
    1169       // handling IOB to RAM network connection in cluster_iob0
    1170       if( y == 0 ) {
    1171          (*clusters[0][0]->p_dspin_iob_cmd_out)(
    1172                signal_dspin_cmd_iob0_loopback);
    1173          clusters[0][0]->p_dspin_ram_cmd_in[WEST](
    1174                signal_dspin_cmd_iob0_loopback);
    1175          clusters[0][0]->p_dspin_ram_cmd_out[WEST](
    1176                signal_dspin_false_ram_cmd_out[0][0][WEST]);
    1177          clusters[0][0]->p_dspin_ram_rsp_in[WEST](
    1178                signal_dspin_false_ram_rsp_in[0][0][WEST]);
    1179          clusters[0][0]->p_dspin_ram_rsp_out[WEST](
    1180                signal_dspin_rsp_iob0_loopback);
    1181          (*clusters[0][0]->p_dspin_iob_rsp_in)(
    1182                signal_dspin_rsp_iob0_loopback);
    1183       }
    1184       else {
    1185          clusters[0][y]->p_dspin_ram_cmd_in[WEST](
    1186                signal_dspin_false_ram_cmd_in[0][y][WEST]);
    1187          clusters[0][y]->p_dspin_ram_cmd_out[WEST](
    1188                signal_dspin_false_ram_cmd_out[0][y][WEST]);
    1189          clusters[0][y]->p_dspin_ram_rsp_in[WEST](
    1190                signal_dspin_false_ram_rsp_in[0][y][WEST]);
    1191          clusters[0][y]->p_dspin_ram_rsp_out[WEST](
    1192                signal_dspin_false_ram_rsp_out[0][y][WEST]);
    1193       }
    1194 
    1195       // handling IOB to RAM network connection in cluster_iob1
    1196       if( y == y_size-1 ) {
    1197          (*clusters[x_size-1][y_size-1]->p_dspin_iob_cmd_out)(
    1198                signal_dspin_cmd_iob1_loopback);
    1199          clusters[x_size-1][y_size-1]->p_dspin_ram_cmd_in[EAST](
    1200                signal_dspin_cmd_iob1_loopback);
    1201 
    1202          clusters[x_size-1][y_size-1]->p_dspin_ram_cmd_out[EAST](
    1203                signal_dspin_false_ram_cmd_out[x_size-1][y_size-1][EAST]);
    1204          clusters[x_size-1][y_size-1]->p_dspin_ram_rsp_in[EAST](
    1205                signal_dspin_false_ram_rsp_in[x_size-1][y_size-1][EAST]);
    1206 
    1207          clusters[x_size-1][y_size-1]->p_dspin_ram_rsp_out[EAST](
    1208                signal_dspin_rsp_iob1_loopback);
    1209          (*clusters[x_size-1][y_size-1]->p_dspin_iob_rsp_in)(
    1210                signal_dspin_rsp_iob1_loopback);
    1211       }
    1212       else {
    1213          clusters[x_size-1][y]->p_dspin_ram_cmd_in[EAST](
    1214                signal_dspin_false_ram_cmd_in[x_size-1][y][EAST]);
    1215          clusters[x_size-1][y]->p_dspin_ram_cmd_out[EAST](
    1216                signal_dspin_false_ram_cmd_out[x_size-1][y][EAST]);
    1217          clusters[x_size-1][y]->p_dspin_ram_rsp_in[EAST](
    1218                signal_dspin_false_ram_rsp_in[x_size-1][y][EAST]);
    1219          clusters[x_size-1][y]->p_dspin_ram_rsp_out[EAST](
    1220                signal_dspin_false_ram_rsp_out[x_size-1][y][EAST]);
    1221       }
     1227      // L2-XRAM cmd network boundary connections
     1228      clusters[0][y]->p_dspin_ram_cmd_in[WEST](
     1229            signal_dspin_false_ram_cmd_in[0][y][WEST]);
     1230      clusters[0][y]->p_dspin_ram_cmd_out[WEST](
     1231            signal_dspin_false_ram_cmd_out[0][y][WEST]);
     1232      clusters[x_size-1][y]->p_dspin_ram_cmd_in[EAST](
     1233            signal_dspin_false_ram_cmd_in[x_size-1][y][EAST]);
     1234      clusters[x_size-1][y]->p_dspin_ram_cmd_out[EAST](
     1235            signal_dspin_false_ram_cmd_out[x_size-1][y][EAST]);
     1236
     1237      // L2-XRAM rsp network boundary connections
     1238      clusters[0][y]->p_dspin_ram_rsp_in[WEST](
     1239            signal_dspin_false_ram_rsp_in[0][y][WEST]);
     1240      clusters[0][y]->p_dspin_ram_rsp_out[WEST](
     1241            signal_dspin_false_ram_rsp_out[0][y][WEST]);
     1242      clusters[x_size-1][y]->p_dspin_ram_rsp_in[EAST](
     1243            signal_dspin_false_ram_rsp_in[x_size-1][y][EAST]);
     1244      clusters[x_size-1][y]->p_dspin_ram_rsp_out[EAST](
     1245            signal_dspin_false_ram_rsp_out[x_size-1][y][EAST]);
    12221246   }
    12231247
     
    12771301
    12781302   signal_resetn = false;
    1279 
    12801303   signal_irq_false = false;
    12811304
     
    13681391         }
    13691392
     1393         // trace RAM xbar (between MEMC and IOB)
     1394         // clusters[0][0]->ram_xbar_cmd->print_trace();
     1395         // clusters[0][0]->ram_xbar_rsp->print_trace();
     1396         // clusters[x_size-1][y_size-1]->ram_xbar_cmd->print_trace();
     1397         // clusters[x_size-1][y_size-1]->ram_xbar_rsp->print_trace();
     1398
    13701399         // trace INT network
    1371          //          clusters[0][0]->int_xbar_d->print_trace();
    1372 
    1373          //          clusters[0][0]->signal_int_dspin_cmd_l2g_d.print_trace(
    1374          //             "[SIG] INT_CMD_L2G_D_0_0");
    1375          //          clusters[0][0]->signal_int_dspin_rsp_g2l_d.print_trace(
    1376          //             "[SIG] INT_RSP_G2L_D_0_0");
    1377 
    1378          //          clusters[0][0]->int_router_cmd->print_trace(0);
    1379          //          clusters[0][0]->int_router_rsp->print_trace(0);
     1400         // clusters[0][0]->int_xbar_d->print_trace();
     1401
     1402         // clusters[0][0]->signal_int_dspin_cmd_l2g_d.print_trace(
     1403         //    "[SIG] INT_CMD_L2G_D_0_0");
     1404         // clusters[0][0]->signal_int_dspin_rsp_g2l_d.print_trace(
     1405         //    "[SIG] INT_RSP_G2L_D_0_0");
     1406
     1407         // clusters[0][0]->int_router_cmd->print_trace(0);
     1408         // clusters[0][0]->int_router_rsp->print_trace(0);
    13801409
    13811410         // trace INT_CMD_D xbar and router in cluster 0_1
    1382          //          clusters[0][1]->int_router_cmd->print_trace(0);
    1383          //          clusters[0][1]->int_router_rsp->print_trace(0);
    1384 
    1385          //          clusters[0][1]->signal_int_dspin_cmd_g2l_d.print_trace(
    1386          //             "[SIG] INT_CMD_G2L_D_0_0");
    1387          //          clusters[0][1]->signal_int_dspin_rsp_l2g_d.print_trace(
    1388          //             "[SIG] INT_RSP_L2G_D_0_0");
    1389 
    1390          //          clusters[0][1]->int_xbar_cmd_d->print_trace();
     1411         // clusters[0][1]->int_router_cmd->print_trace(0);
     1412         // clusters[0][1]->int_router_rsp->print_trace(0);
     1413
     1414         // clusters[0][1]->signal_int_dspin_cmd_g2l_d.print_trace(
     1415         //    "[SIG] INT_CMD_G2L_D_0_0");
     1416         // clusters[0][1]->signal_int_dspin_rsp_l2g_d.print_trace(
     1417         //    "[SIG] INT_RSP_L2G_D_0_0");
     1418
     1419         // clusters[0][1]->int_xbar_cmd_d->print_trace();
    13911420
    13921421         // trace memc[debug_memc_id]
     
    14121441
    14131442         // trace iob, iox and external peripherals
    1414          if ( debug_iob ) {
    1415             clusters[0][0]->iob->print_trace();
    1416             clusters[0][0]->signal_int_vci_tgt_iobx.print_trace(
    1417                   "[SIG]IOB0_INT_TGT");
    1418             clusters[0][0]->signal_int_vci_ini_iobx.print_trace(
    1419                   "[SIG]IOB0_INT_INI");
    1420             clusters[0][0]->signal_ram_vci_ini_iobx.print_trace(
    1421                   "[SIG]IOB0_RAM_INI");
    1422 
    1423             signal_vci_ini_iob0.print_trace("[SIG]IOB0_IOX_INI");
    1424             signal_vci_tgt_iob0.print_trace("[SIG]IOB0_IOX_TGT");
    1425 
    1426             cdma->print_trace();
    1427             signal_vci_tgt_cdma.print_trace("[SIG]IOX_CDMA_TGT");
    1428             signal_vci_ini_cdma.print_trace("[SIG]IOX_CDMA_INI");
    1429 
    1430             iox_network->print_trace();
    1431 
    1432             // interrupts
    1433             if (signal_irq_bdev) std::cout << "### IRQ_BDEV ACTIVATED"
    1434                << std::endl;
    1435          }
     1443         //if ( debug_iob ) {
     1444         //   clusters[0][0]->iob->print_trace();
     1445         //   clusters[0][0]->signal_int_vci_tgt_iobx.print_trace(
     1446         //         "[SIG]IOB0_INT_TGT");
     1447         //   clusters[0][0]->signal_int_vci_ini_iobx.print_trace(
     1448         //         "[SIG]IOB0_INT_INI");
     1449         //   clusters[0][0]->signal_ram_vci_ini_iobx.print_trace(
     1450         //         "[SIG]IOB0_RAM_INI");
     1451
     1452         //   signal_vci_ini_iob0.print_trace("[SIG]IOB0_IOX_INI");
     1453         //   signal_vci_tgt_iob0.print_trace("[SIG]IOB0_IOX_TGT");
     1454
     1455         //   cdma->print_trace();
     1456         //   signal_vci_tgt_cdma.print_trace("[SIG]IOX_CDMA_TGT");
     1457         //   signal_vci_ini_cdma.print_trace("[SIG]IOX_CDMA_INI");
     1458
     1459         //   iox_network->print_trace();
     1460
     1461         //   // interrupts
     1462         //   if (signal_irq_bdev) std::cout << "### IRQ_BDEV ACTIVATED"
     1463         //      << std::endl;
     1464         //}
    14361465      }
    14371466      sc_start(sc_core::sc_time(1, SC_NS));
     
    14441473   delete cdma;
    14451474   delete mtty;
     1475   delete xpic;
    14461476
    14471477   for(size_t x = 0; x < x_size; x++) {
  • branches/fault_tolerance/platform/tsar_generic_iob/top.desc

    r699 r717  
    22# -*- python -*-
    33
    4 # VCI parameters 
     4# VCI parameters
    55vci_cell_size_int   = 4
    66vci_cell_size_ext   = 8
     
    1616vci_wrplen_size     = 1
    1717
    18 # internal DSPIN network parameters 
     18# internal DSPIN network parameters
    1919int_dspin_cmd_flit_size = 39
    2020int_dspin_rsp_flit_size = 32
     
    2727    uses = [
    2828            # cluster
    29             Uses('caba:tsar_iob_cluster', 
     29            Uses('caba:tsar_iob_cluster',
    3030                  vci_data_width_int  = vci_cell_size_int,
    31                   vci_data_width_ext  = vci_cell_size_ext, 
     31                  vci_data_width_ext  = vci_cell_size_ext,
    3232                  dspin_int_cmd_width = int_dspin_cmd_flit_size,
    3333                  dspin_int_rsp_width = int_dspin_rsp_flit_size,
    3434                  dspin_ram_cmd_width = ram_dspin_cmd_flit_size,
    3535                  dspin_ram_rsp_width = ram_dspin_rsp_flit_size),
    36                  
     36
    3737            # IOX Network
    38             Uses('caba:vci_iox_network', 
     38            Uses('caba:vci_iox_network',
    3939                  cell_size = vci_cell_size_ext),
    4040
    4141            # Frame Buffer
    42             Uses('caba:vci_framebuffer', 
     42            Uses('caba:vci_framebuffer',
    4343                  cell_size = vci_cell_size_ext),
    4444
    4545            # Block Device
    46             Uses('caba:vci_block_device_tsar', 
     46            Uses('caba:vci_block_device_tsar',
    4747                  cell_size = vci_cell_size_ext),
    4848
    49             # NIC 
    50             Uses('caba:vci_multi_nic', 
     49            # NIC
     50            Uses('caba:vci_multi_nic',
    5151                  cell_size = vci_cell_size_ext),
    5252
    5353            # Chained DMA
    54             Uses('caba:vci_chbuf_dma', 
     54            Uses('caba:vci_chbuf_dma',
    5555                  cell_size = vci_cell_size_ext),
    5656
    5757            # TTY
    58             Uses('caba:vci_multi_tty',
     58            Uses('caba:vci_multi_tty',
     59                  cell_size = vci_cell_size_ext),
     60
     61            # PIC
     62            Uses('caba:vci_iopic',
    5963                  cell_size = vci_cell_size_ext),
    6064
     
    6468
    6569    # default VCI parameters (global variables)
    66     cell_size   = vci_cell_size_int, 
     70    cell_size   = vci_cell_size_int,
    6771    plen_size   = vci_plen_size,
    6872    addr_size   = vci_addr_size,
  • branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd

    r699 r717  
    6666              flit_width         = parameter.Reference('dspin_int_rsp_width')),
    6767
     68        Uses('caba:dspin_local_crossbar',
     69              flit_width         = parameter.Reference('dspin_ram_cmd_width')),
     70
     71        Uses('caba:dspin_local_crossbar',
     72              flit_width         = parameter.Reference('dspin_ram_rsp_width')),
     73
    6874        Uses('caba:vci_dspin_initiator_wrapper',
    6975              cell_size          = parameter.Reference('vci_data_width_int'),
     
    9399              dspin_rsp_width    = parameter.Reference('dspin_ram_rsp_width')),
    94100
    95         Uses('caba:dspin_router_tsar',
     101        Uses('caba:dspin_router',
    96102              flit_width         = parameter.Reference('dspin_ram_cmd_width')),
    97103
    98         Uses('caba:dspin_router_tsar',
     104        Uses('caba:dspin_router',
    99105              flit_width         = parameter.Reference('dspin_ram_rsp_width')),
    100106
  • branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h

    r696 r717  
    2727#include "vci_dspin_initiator_wrapper.h"
    2828#include "vci_dspin_target_wrapper.h"
    29 #include "dspin_router_tsar.h"
     29#include "dspin_router.h"
    3030#include "virtual_dspin_router.h"
    3131#include "vci_multi_dma.h"
     
    8989      soclib::caba::VciTarget<vci_param_ext>*    p_vci_iob_iox_tgt;
    9090
    91       // These ports are used to connect IOB to RAM network in top cell
    92       soclib::caba::DspinOutput<dspin_ram_cmd_width>* p_dspin_iob_cmd_out;
    93       soclib::caba::DspinInput<dspin_ram_rsp_width>*  p_dspin_iob_rsp_in;
    94 
    95       // These ports are used to connect hard IRQ from external peripherals to
    96       // IOB0
    97       sc_in<bool>* p_irq[32];
    98 
    9991      // These arrays of ports are used to connect the INT & RAM networks in
    10092      // top cell
     
    111103      // interrupt signals
    112104      sc_signal<bool> signal_false;
    113       sc_signal<bool> signal_proc_it[8];
    114       sc_signal<bool> signal_irq_mdma[8];
    115       sc_signal<bool> signal_irq_mtty[8];
     105      sc_signal<bool> signal_proc_it[NB_PROCS*IRQ_PER_PROCESSOR];
     106      sc_signal<bool> signal_irq_mdma[NB_DMA_CHANNELS];
     107      sc_signal<bool> signal_irq_mtty[NB_DEBUG_TTY_CHANNELS];
    116108      sc_signal<bool> signal_irq_memc;
    117109
     
    130122
    131123      // INT network VCI signals between VCI components and VCI local crossbar
    132       VciSignals<vci_param_int> signal_int_vci_ini_proc[8];
     124      VciSignals<vci_param_int> signal_int_vci_ini_proc[NB_PROCS];
    133125      VciSignals<vci_param_int> signal_int_vci_ini_mdma;
    134126      VciSignals<vci_param_int> signal_int_vci_ini_iobx;
     
    149141      DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_memc;
    150142      DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_memc;
    151       DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_proc[8];
    152       DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_proc[8];
    153       DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_proc[8];
     143      DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_proc[NB_PROCS];
     144      DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_proc[NB_PROCS];
     145      DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_proc[NB_PROCS];
    154146
    155147      // RAM network VCI signals between VCI components and VCI/DSPIN wrappers
     
    161153      DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_xram_t;
    162154      DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_xram_t;
     155
    163156      DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_memc_i;
    164157      DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_memc_i;
     158
     159      DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_iob_i;
     160      DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_iob_i;
     161
     162      DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_xbar;
     163      DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_xbar;
     164
     165      DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_false;
     166      DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_false;
     167
    165168
    166169      //////////////////////////////////////
     
    213216      VciExtDspinTargetWrapperType* xram_ram_wt;
    214217
    215       DspinRouterTsar<dspin_ram_cmd_width>* ram_router_cmd;
    216       DspinRouterTsar<dspin_ram_rsp_width>* ram_router_rsp;
     218      DspinRouter<dspin_ram_cmd_width>* ram_router_cmd;
     219      DspinRouter<dspin_ram_rsp_width>* ram_router_rsp;
     220
     221      DspinLocalCrossbar<dspin_ram_cmd_width>* ram_xbar_cmd;
     222      DspinLocalCrossbar<dspin_ram_rsp_width>* ram_xbar_rsp;
    217223
    218224      // IO Network Components (not instanciated in all clusters)
     
    232238         const soclib::common::MappingTable &mt_ext;
    233239         const soclib::common::MappingTable &mt_iox;
     240
     241         const bool is_io;
     242         const soclib::common::IntTab iox_iob_tgtid;
     243         const soclib::common::IntTab iox_iob_srcid;
    234244
    235245         size_t memc_ways;
     
    243253         const Loader& loader;
    244254
     255         bool distboot;
     256
    245257         uint32_t frozen_cycles;
    246258         uint32_t debug_start_cycle;
     
    255267      };
    256268
     269
     270      SC_HAS_PROCESS(TsarIobCluster);
     271
     272      void init();
     273
    257274      // cluster constructor
    258275      TsarIobCluster(struct ClusterParams& params);
  • branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp

    r696 r717  
    99// Modified on: mars 2014
    1010//////////////////////////////////////////////////////////////////////////////
    11 // Cluster(0,0) & Cluster(xmax-1,ymax-1) contains the IOB0 & IOB1 components.
    12 // These two clusters contain 6 extra components:
    13 // - 1 vci_io_bridge (connected to the 3 networks.
     11// IO clusters contains the IOB component.
     12// These clusters contain 6 extra components:
     13// - 1 vci_io_bridge (connected to the 3 networks).
    1414// - 3 vci_dspin_wrapper for the IOB.
    1515// - 2 dspin_local_crossbar for commands and responses.
     
    3939   assert((params.x_id < X_MAX) && (params.y_id < Y_MAX));
    4040
    41    size_t cid           = this->clusterId(params.x_id, params.y_id);
    42    size_t cluster_iob0  = this->clusterId(0, 0);
    43    size_t cluster_iob1  = this->clusterId(X_SIZE - 1, Y_SIZE - 1);
    44    size_t is_iob0       = (cid == cluster_iob0);
    45    size_t is_iob1       = (cid == cluster_iob1);
    46    bool   is_io_cluster = is_iob0 || is_iob1;
    47 
     41   size_t cid     = this->clusterId(params.x_id, params.y_id);
    4842   size_t l_width = vci_param_int::S - X_WIDTH - Y_WIDTH;
    4943
     
    6761      alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4);
    6862
    69    // ports in cluster_iob0 and cluster_iob1 only
     63   // ports in IO clusters only
    7064   p_vci_iob_iox_ini   = NULL;
    7165   p_vci_iob_iox_tgt   = NULL;
    72    p_dspin_iob_cmd_out = NULL;
    73    p_dspin_iob_rsp_in  = NULL;
    74    if ( is_io_cluster ) {
     66   if ( params.is_io ) {
     67      std::cout << "   Creating signals for IOB" << std::endl;
     68
    7569      // VCI ports from IOB to IOX network
    7670      p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>;
    7771      p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>;
    78 
    79       // DSPIN ports from IOB to RAM network
    80       p_dspin_iob_cmd_out = new soclib::caba::DspinOutput<dspin_ram_cmd_width>;
    81       p_dspin_iob_rsp_in  = new soclib::caba::DspinInput<dspin_ram_rsp_width>;
    82    }
    83 
    84    // IRQ ports in cluster_iob0 only
    85    for ( size_t n = 0 ; n < 32 ; n++ ) {
    86       p_irq[n] = ( is_iob0 ) ? new sc_in<bool> : NULL;
    8772   }
    8873
     
    11095            params.debug_start_cycle, params.proc_debug_ok);
    11196
    112       proc[p]->set_dcache_paddr_ext_reset(cid);
    113       proc[p]->set_icache_paddr_ext_reset(cid);
     97      // Physical address extention register is initialized with local cluster
     98      // ID when distributed boot is activated.
     99      if (params.distboot) {
     100         proc[p]->set_dcache_paddr_ext_reset(cid);
     101         proc[p]->set_icache_paddr_ext_reset(cid);
     102      }
    114103   }
    115104
     
    149138
    150139   // Multi-TTY controller
    151    mtty        = NULL;
     140   mtty = NULL;
    152141   if (NB_DEBUG_TTY_CHANNELS) {
    153142      assert(NB_DEBUG_TTY_CHANNELS < 8);
     
    175164         params.mt_int,
    176165         IntTab(cid, INT_XICU_TGT_ID),
    177          32, 32, 32,
    178          NB_PROCS);
     166         32, 1, 32,
     167         NB_PROCS * IRQ_PER_PROCESSOR);
    179168
    180169   ////////////  MDMA
     
    195184      nb_direct_targets++;
    196185   }
    197    if ( is_io_cluster ) {
     186   if ( params.is_io ) {
    198187      nb_direct_initiators++;
    199188      nb_direct_targets++;
     
    306295   std::ostringstream s_ram_router_cmd;
    307296   s_ram_router_cmd << "ram_router_cmd_" << params.x_id << "_" << params.y_id;
    308    ram_router_cmd = new DspinRouterTsar<dspin_ram_cmd_width>(
     297   ram_router_cmd = new DspinRouter<dspin_ram_cmd_width>(
    309298         s_ram_router_cmd.str().c_str(),
    310299         params.x_id, params.y_id,
    311300         X_WIDTH, Y_WIDTH,
    312          4, 4,
    313          is_iob0, is_iob1,
    314          false,
    315          l_width);
     301         4, 4);
    316302
    317303   std::ostringstream s_ram_router_rsp;
    318304   s_ram_router_rsp << "ram_router_rsp_" << params.x_id << "_" << params.y_id;
    319    ram_router_rsp = new DspinRouterTsar<dspin_ram_rsp_width>(
     305   ram_router_rsp = new DspinRouter<dspin_ram_rsp_width>(
    320306         s_ram_router_rsp.str().c_str(),
    321307         params.x_id, params.y_id,
    322308         X_WIDTH, Y_WIDTH,
    323          4, 4,
    324          is_iob0, is_iob1,
    325          true,
    326          l_width);
     309         4, 4);
    327310
    328311   ////////////////////// I/O  CLUSTER ONLY ///////////////////////
    329312   iob        = NULL;
    330313   iob_ram_wi = NULL;
    331    if ( is_io_cluster ) {
     314   if ( params.is_io ) {
    332315      ///////////  IO_BRIDGE
    333       size_t iox_local_id;
    334       bool   has_irqs;
    335       if ( is_iob0 ) {
    336          iox_local_id = 0;
    337          has_irqs     = true;
    338       }
    339       else {
    340          iox_local_id = 1;
    341          has_irqs     = false;
    342       }
    343 
    344316      std::ostringstream s_iob;
    345317      s_iob << "iob_" << params.x_id << "_" << params.y_id;   
     
    351323            IntTab(cid, INT_IOBX_TGT_ID),
    352324            IntTab(cid, INT_IOBX_INI_ID),
    353             IntTab(cid, iox_local_id ),
    354             has_irqs,
     325            params.iox_iob_tgtid,
     326            params.iox_iob_srcid,
    355327            16,
    356328            8,
     
    364336            s_iob_ram_wi.str().c_str(),
    365337            vci_param_int::S);
     338
     339      std::ostringstream s_ram_xbar_cmd;
     340      s_ram_xbar_cmd << "s_ram_xbar_cmd_" << params.x_id << "_" << params.y_id;
     341      ram_xbar_cmd = new DspinLocalCrossbar<dspin_ram_cmd_width>(
     342            s_ram_xbar_cmd.str().c_str(), // name
     343            params.mt_ext,                // mapping table
     344            params.x_id, params.y_id,     // x, y
     345            X_WIDTH, Y_WIDTH, l_width,    // x_width, y_width, l_width
     346            2, 0,                         // local inputs, local outputs
     347            2, 2,                         // in fifo, out fifo depths
     348            true,                         // is cmd ?
     349            false,                        // use routing table ?
     350            false);                       // support broadcast ?
     351
     352      std::ostringstream s_ram_xbar_rsp;
     353      s_ram_xbar_rsp << "s_ram_xbar_rsp_" << params.x_id << "_" << params.y_id;
     354      ram_xbar_rsp = new DspinLocalCrossbar<dspin_ram_rsp_width>(
     355            s_ram_xbar_rsp.str().c_str(), // name
     356            params.mt_ext,                // mapping table
     357            params.x_id, params.y_id,     // x, y
     358            X_WIDTH, Y_WIDTH, l_width,    // x_width, y_width, l_width
     359            0, 2,                         // local inputs, local outputs
     360            2, 2,                         // in fifo, out fifo depths
     361            false,                        // is cmd ?
     362            true,                         // use routing table ?
     363            false);                       // support broadcast ?
    366364   }
    367365
     
    372370   // on coherence network : local srcid[proc] in [0...NB_PROCS-1]
    373371   //                      : local srcid[memc] = NB_PROCS
    374    // In cluster_iob0, 32 HWI interrupts from external peripherals
    375    // are connected to the XICU ports p_hwi[0:31]
    376    // In other clusters, no HWI interrupts are connected to XICU
    377372
    378373   //////////////////////// internal CMD & RSP routers
     
    425420   }
    426421
    427    if ( is_io_cluster ) {
     422   if ( params.is_io ) {
    428423      int_xbar_d->p_to_target[INT_IOBX_TGT_ID]    (signal_int_vci_tgt_iobx);
    429424      int_xbar_d->p_to_initiator[INT_IOBX_INI_ID] (signal_int_vci_ini_iobx);
     
    480475      proc[p]->p_dspin_p2m    (signal_int_dspin_p2m_proc[p]);
    481476      proc[p]->p_dspin_clack  (signal_int_dspin_clack_proc[p]);
    482       proc[p]->p_irq[0]       (signal_proc_it[p]);
    483       for ( size_t j = 1 ; j < 6 ; j++) {
    484          proc[p]->p_irq[j]    (signal_false);
     477      for ( size_t j = 0 ; j < 6 ; j++) {
     478         if ( j < IRQ_PER_PROCESSOR ) {
     479            proc[p]->p_irq[j] (signal_proc_it[IRQ_PER_PROCESSOR * p + j]);
     480         }
     481         else {
     482            proc[p]->p_irq[j] (signal_false);
     483         }
    485484      }
    486485   }
     
    490489   xicu->p_resetn (this->p_resetn);
    491490   xicu->p_vci    (signal_int_vci_tgt_xicu);
    492    for ( size_t p = 0 ; p < NB_PROCS ; p++) {
    493       xicu->p_irq[p] (signal_proc_it[p]);
    494    }
    495    for ( size_t i=0 ; i<32 ; i++) {
    496       if ( is_iob0 )
    497          xicu->p_hwi[i] (*(this->p_irq[i]));
    498       else 
    499          xicu->p_hwi[i] (signal_false);
    500    }                     
     491   for ( size_t irq = 0 ; irq < (IRQ_PER_PROCESSOR * NB_PROCS) ; irq++) {
     492      xicu->p_irq[irq] (signal_proc_it[irq]);
     493   }
     494   xicu->p_hwi[0] (signal_irq_memc);
    501495
    502496   ///////////////////////////////////// MEMC
     
    564558      ram_router_rsp->p_in[n]  (this->p_dspin_ram_rsp_in[n]);
    565559   }
    566    ram_router_cmd->p_out[4]    (signal_ram_dspin_cmd_xram_t);
    567    ram_router_cmd->p_in[4]     (signal_ram_dspin_cmd_memc_i);
    568    ram_router_rsp->p_out[4]    (signal_ram_dspin_rsp_memc_i);
    569    ram_router_rsp->p_in[4]     (signal_ram_dspin_rsp_xram_t);
    570 
    571    ///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1.
    572    if ( is_io_cluster ) {
     560
     561   ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t);
     562   if (params.is_io) ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_xbar);
     563   else              ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i);
     564
     565   ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t);
     566   if (params.is_io) ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_xbar);
     567   else              ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i);
     568
     569   ///////////////////////// IOB exists only in IO clusters.
     570   if ( params.is_io ) {
    573571      // IO bridge
    574572      iob->p_clk         (this->p_clk);
     
    580578      iob->p_vci_ini_ram (signal_ram_vci_ini_iobx);
    581579
    582       if ( is_iob0 ) {
    583          for ( size_t n = 0 ; n < 32 ; n++ ) {
    584             (*iob->p_irq[n]) (*(this->p_irq[n]));
    585          }
    586       }
    587 
    588580      // initiator wrapper to RAM network
    589       iob_ram_wi->p_clk       (this->p_clk);
    590       iob_ram_wi->p_resetn    (this->p_resetn);
    591       iob_ram_wi->p_dspin_cmd (*(this->p_dspin_iob_cmd_out));
    592       iob_ram_wi->p_dspin_rsp (*(this->p_dspin_iob_rsp_in));
    593       iob_ram_wi->p_vci       (signal_ram_vci_ini_iobx);
    594    }
     581      iob_ram_wi->p_clk            (this->p_clk);
     582      iob_ram_wi->p_resetn         (this->p_resetn);
     583      iob_ram_wi->p_dspin_cmd      (signal_ram_dspin_cmd_iob_i);
     584      iob_ram_wi->p_dspin_rsp      (signal_ram_dspin_rsp_iob_i);
     585      iob_ram_wi->p_vci            (signal_ram_vci_ini_iobx);
     586
     587      ram_xbar_cmd->p_clk          (this->p_clk);
     588      ram_xbar_cmd->p_resetn       (this->p_resetn);
     589      ram_xbar_cmd->p_global_out   (signal_ram_dspin_cmd_xbar);
     590      ram_xbar_cmd->p_global_in    (signal_ram_dspin_cmd_false);
     591      ram_xbar_cmd->p_local_in[0]  (signal_ram_dspin_cmd_memc_i);
     592      ram_xbar_cmd->p_local_in[1]  (signal_ram_dspin_cmd_iob_i);
     593
     594      ram_xbar_rsp->p_clk          (this->p_clk);
     595      ram_xbar_rsp->p_resetn       (this->p_resetn);
     596      ram_xbar_rsp->p_global_out   (signal_ram_dspin_rsp_false);
     597      ram_xbar_rsp->p_global_in    (signal_ram_dspin_rsp_xbar);
     598      ram_xbar_rsp->p_local_out[0] (signal_ram_dspin_rsp_memc_i);
     599      ram_xbar_rsp->p_local_out[1] (signal_ram_dspin_rsp_iob_i);
     600   }
     601
     602   SC_METHOD(init);
    595603} // end constructor
     604
     605tmpl(void)::init() {
     606   signal_ram_dspin_cmd_false.write = false;
     607   signal_ram_dspin_cmd_false.read = true;
     608   signal_ram_dspin_rsp_false.write = false;
     609   signal_ram_dspin_rsp_false.read = true;
     610}
    596611
    597612tmpl(/**/)::~TsarIobCluster() {
    598613   if (p_vci_iob_iox_ini)   delete p_vci_iob_iox_ini;
    599614   if (p_vci_iob_iox_tgt)   delete p_vci_iob_iox_tgt;
    600    if (p_dspin_iob_cmd_out) delete p_dspin_iob_cmd_out;
    601    if (p_dspin_iob_rsp_in)  delete p_dspin_iob_rsp_in;
    602615   if (iob)                 delete iob;
    603616   if (iob_ram_wi)          delete iob_ram_wi;
    604 
    605    for (size_t n = 0 ; n < 32 ; n++) {
    606       if (p_irq[n]) delete p_irq[n];
    607    }
    608617
    609618   for (size_t p = 0; p < NB_PROCS; p++) {
     
    627636   delete ram_router_cmd;
    628637   delete ram_router_rsp;
     638   delete ram_xbar_cmd;
     639   delete ram_xbar_rsp;
    629640}
    630641
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