Changeset 717 for branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h

Timestamp:

Jun 23, 2014, 4:02:53 PM (10 years ago)

Author:

cfuguet

Message:

fault_tolerance/tsar_generic_iob:

• introducing the vci_iopic component on the IOX interconnect.

• the input hardware interrupts on cluster(0,0) from the external peripherals have been removed because they are connected to the vci_iopic component.

• Replacing "ad-hoc" dspin_tsar router by standard dspin_router on the RAM interconnect. To do so, in IO clusters (clusters with IOB) two crossbars are implemented:

+ One for commands which interconnects MEMC and IOB to the

local interface of RAM CMD dspin_router.

+ One for responses which interconnects local interface of RAM

RSP dspin_router to MEMC and IOB.

• Considering case of mono cluster platform: Only one IOB must be instantiated.

• Modifying IOX memory segments used by IOX network for routing:

+ bugfix: all segments of IOX interconnect must have

global id = 0.

+ Adding XICU segments with special attribute. This

attribute is used by IOB to determine if a command coming
from external DMA peripheral should be routed
through INT or RAM networks.

+ Using bit 32 of physical address to determine if an

external DMA command should be routed through IOB0
or IOB1.

File:

• branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h (modified) (10 diffs)

branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h

@@ -27 +27 @@
 #include "vci_dspin_initiator_wrapper.h"
 #include "vci_dspin_target_wrapper.h"
-#include "dspin_router_tsar.h"
+#include "dspin_router.h"
 #include "virtual_dspin_router.h"
 #include "vci_multi_dma.h"
@@ -89 +89 @@
       soclib::caba::VciTarget<vci_param_ext>*    p_vci_iob_iox_tgt;
 
-      // These ports are used to connect IOB to RAM network in top cell
-      soclib::caba::DspinOutput<dspin_ram_cmd_width>* p_dspin_iob_cmd_out;
-      soclib::caba::DspinInput<dspin_ram_rsp_width>*  p_dspin_iob_rsp_in;
-
-      // These ports are used to connect hard IRQ from external peripherals to
-      // IOB0
-      sc_in<bool>* p_irq[32];
-
       // These arrays of ports are used to connect the INT & RAM networks in
       // top cell
@@ -111 +103 @@
       // interrupt signals
       sc_signal<bool> signal_false;
-      sc_signal<bool> signal_proc_it[8];
-      sc_signal<bool> signal_irq_mdma[8];
-      sc_signal<bool> signal_irq_mtty[8];
+      sc_signal<bool> signal_proc_it[NB_PROCS*IRQ_PER_PROCESSOR];
+      sc_signal<bool> signal_irq_mdma[NB_DMA_CHANNELS];
+      sc_signal<bool> signal_irq_mtty[NB_DEBUG_TTY_CHANNELS];
       sc_signal<bool> signal_irq_memc;
 
@@ -130 +122 @@
 
       // INT network VCI signals between VCI components and VCI local crossbar
-      VciSignals<vci_param_int> signal_int_vci_ini_proc[8];
+      VciSignals<vci_param_int> signal_int_vci_ini_proc[NB_PROCS];
       VciSignals<vci_param_int> signal_int_vci_ini_mdma;
       VciSignals<vci_param_int> signal_int_vci_ini_iobx;
@@ -149 +141 @@
       DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_memc;
       DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_memc;
-      DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_proc[8];
-      DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_proc[8];
-      DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_proc[8];
+      DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_proc[NB_PROCS];
+      DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_proc[NB_PROCS];
+      DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_proc[NB_PROCS];
 
       // RAM network VCI signals between VCI components and VCI/DSPIN wrappers
@@ -161 +153 @@
       DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_xram_t;
       DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_xram_t;
+
       DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_memc_i;
       DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_memc_i;
+
+      DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_iob_i;
+      DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_iob_i;
+
+      DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_xbar;
+      DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_xbar;
+
+      DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_false;
+      DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_false;
+
 
       //////////////////////////////////////
@@ -213 +216 @@
       VciExtDspinTargetWrapperType* xram_ram_wt;
 
-      DspinRouterTsar<dspin_ram_cmd_width>* ram_router_cmd;
-      DspinRouterTsar<dspin_ram_rsp_width>* ram_router_rsp;
+      DspinRouter<dspin_ram_cmd_width>* ram_router_cmd;
+      DspinRouter<dspin_ram_rsp_width>* ram_router_rsp;
+
+      DspinLocalCrossbar<dspin_ram_cmd_width>* ram_xbar_cmd;
+      DspinLocalCrossbar<dspin_ram_rsp_width>* ram_xbar_rsp;
 
       // IO Network Components (not instanciated in all clusters)
@@ -232 +238 @@
          const soclib::common::MappingTable &mt_ext;
          const soclib::common::MappingTable &mt_iox;
+
+         const bool is_io;
+         const soclib::common::IntTab iox_iob_tgtid;
+         const soclib::common::IntTab iox_iob_srcid;
 
          size_t memc_ways;
@@ -243 +253 @@
          const Loader& loader;
 
+         bool distboot;
+
          uint32_t frozen_cycles;
          uint32_t debug_start_cycle;
@@ -255 +267 @@
       };
 
+
+      SC_HAS_PROCESS(TsarIobCluster);
+
+      void init();
+
       // cluster constructor
       TsarIobCluster(struct ClusterParams& params);