Changeset 742


Ignore:
Timestamp:
Jul 9, 2014, 5:36:08 PM (8 years ago)
Author:
cfuguet
Message:

Merge 'trunk' into 'fault_tolerance'

  • Introducing last bugfixes of trunk into the fault_tolerance branch
Location:
branches/fault_tolerance
Files:
10 edited

Legend:

Unmodified
Added
Removed
  • branches/fault_tolerance/modules/vci_block_device_tsar/caba/source/include/vci_block_device_tsar.h

    r724 r742  
    3333// contain 32 bits words. It supports VCI addresss lartger than 32 bits.
    3434//
    35 // This component can perform data transfers between one single file belonging
    36 // to the host system and a buffer in the memory of the virtual prototype.
    37 // The file name is an argument of the constructor.
     35// This component can perform data transfers between one single file (belonging
     36// to the host system) and a buffer in the memory of the virtual prototype.
     37// The name of the file containing the disk image is a constructor argument.
    3838// This component has a DMA capability, and is both a target and an initiator.
    3939// The block size (bytes), and the burst size (bytes) must be power of 2.
     
    5454// - BLOCK_DEVICE_SIZE          0x18 (read-only)   Number of addressable blocks.
    5555// - BLOCK_DEVICE_BLOCK_SIZE    0x1C (read_only)   Block size in bytes.
    56 // - BLOCK_DEVICE_BUFFER_EXT    0x20 (read_only)   Memory buffer base address (MSB bits)
     56// - BLOCK_DEVICE_BUFFER_EXT    0x20 (read/write)  Memory buffer base address (MSB bits)
    5757//
    5858// The following operations codes are supported:
  • branches/fault_tolerance/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h

    r724 r742  
    342342    bool                                m_debug_dcache_fsm;
    343343    bool                                m_debug_cmd_fsm;
     344    uint32_t                            m_previous_status;
     345
    344346
    345347    ///////////////////////////////
  • branches/fault_tolerance/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp

    r724 r742  
    476476{
    477477    // b0 : write buffer trace
     478    // b1 : dump processor registers
    478479    // b2 : dcache trace
    479480    // b3 : icache trace
    480481    // b4 : dtlb trace
    481482    // b5 : itlb trace
     483    // b6 : SR (ISS register 32)
    482484
    483485    std::cout << std::dec << "PROC " << name() << std::endl;
     
    509511        r_wbuf.printTrace((mode>>1)&1);
    510512    }
     513    if(mode & 0x02)
     514    {
     515        r_iss.dump();
     516    }
    511517    if(mode & 0x04)
    512518    {
     
    528534        std::cout << "  Instruction TLB" << std::endl;
    529535        r_itlb.printTrace();
     536    }
     537    if(mode & 0x40)
     538    {
     539        uint32_t status = r_iss.debugGetRegisterValue( 32 );
     540        std::cout << name();
     541        if ( status != m_previous_status ) std::cout << " NEW ";
     542        std::cout << " status = " << std::hex << status << " " << std::endl;
     543        m_previous_status = status;
    530544    }
    531545}
  • branches/fault_tolerance/modules/vci_io_bridge/caba/source/src/vci_io_bridge.cpp

    r724 r742  
    736736                        {
    737737                            assert( p_vci_tgt_iox.eop.read() and
    738                                    (p_vci_tgt_iox.cmd == vci_param_int::CMD_WRITE) and
     738                                   (p_vci_tgt_iox.cmd.read() == vci_param_int::CMD_WRITE) and
    739739                            "ERROR in VCI_IOB illegal VCI WTI command from IOX network");
    740740
  • branches/fault_tolerance/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp

    r725 r742  
    39403940                    if (m_debug)
    39413941                        std::cout << "  <MEMC " << name() << " WRITE_BC_DIR_INVAL> Inval DIR and register in TRT:"
    3942                             << " address = " << r_write_address.read() << std::endl;
     3942                            << " address = " << std::hex << r_write_address.read() << std::endl;
    39433943#endif
    39443944                    r_write_fsm = WRITE_BC_CC_SEND;
  • branches/fault_tolerance/platforms/tsar_generic_iob/top.cpp

    r738 r742  
    4747// Besides the external peripherals, each cluster contains one XICU component,
    4848// and one multi channels DMA component.
    49 // The XICU component is mainly used to handle WTI IRQs, as only 2 HWI IRQs
     49// The XICU component is mainly used to handle WTI IRQs, as only 5 HWI IRQs
    5050// are connected to XICU in each cluster:
    5151// - IRQ_IN[0] : MMC
  • branches/fault_tolerance/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h

    r724 r742  
    7171    // interrupt signals
    7272    sc_signal<bool>                       signal_false;
    73     sc_signal<bool>                       signal_proc_it[8];
     73    sc_signal<bool>                       signal_proc_it[16];
    7474    sc_signal<bool>                       signal_irq_mdma[8];
    7575    sc_signal<bool>                       signal_irq_memc;
  • branches/fault_tolerance/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp

    r724 r742  
    639639    }
    640640
    641    SC_METHOD(init);
     641    SC_METHOD(init);
     642
    642643} // end constructor
    643644
    644645tmpl(void)::init()
    645646{
    646     signal_ram_dspin_cmd_false.write = false;
    647     signal_ram_dspin_cmd_false.read = true;
    648     signal_ram_dspin_rsp_false.write = false;
    649     signal_ram_dspin_rsp_false.read = true;
     647   signal_ram_dspin_cmd_false.write = false;
     648   signal_ram_dspin_rsp_false.read  = true;
    650649} // end init
    651650
  • branches/fault_tolerance/softs/tsar_boot/conf/platform_tsar_generic_iob/defs_platform.h

    r724 r742  
    1 #define NB_PROCS         1
    2 #define NB_CLUSTERS      4
     1#define NB_PROCS         4
     2#define NB_CLUSTERS      1
     3#define CLUSTER_IO       0
    34
    4 #define IRQ_PER_PROC     1
     5#define IRQ_PER_PROC     4
    56
    67#define USE_IOB          1
  • branches/fault_tolerance/softs/tsar_boot/conf/platform_tsar_generic_iob/ldscript

    r724 r742  
    99seg_reset_code_base     = 0xBFC00000;
    1010
    11 seg_reset_stack_base    = 0x00060000;
    12 seg_reset_stack_size    = 0x00090000;
     11seg_reset_stack_base    = 0x000D0000;
     12seg_reset_stack_size    = 0x00050000;
    1313
    1414/* Grouping sections into segments */
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