Changeset 744 for trunk/softs/giet_tsar/giet.S
- Timestamp:
- Jul 10, 2014, 11:23:57 AM (10 years ago)
- File:
-
- 1 edited
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trunk/softs/giet_tsar/giet.S (modified) (21 diffs)
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trunk/softs/giet_tsar/giet.S
r743 r744 4 4 * Date : 15/01/2014 5 5 ********************************************************************************* 6 * This is a very simple Interrupts/Exception/Traps handler for a generic 6 * This is a very simple Interrupts/Exception/Traps handler for a generic 7 7 * multi-clusters / multi-processors TSAR architecture (up to 256 clusters, 8 * up to 4 processors per cluster). 8 * up to 4 processors per cluster). 9 9 * The physical address is 40 bits, and the 8 MSB bits A[39:32] define the 10 10 * cluster index. … … 15 15 .section .giet,"ax",@progbits 16 16 .align 2 17 .global _interrupt_vector 17 .global _interrupt_vector 18 18 19 19 .extern seg_xcu_base … … 78 78 * System Call Handler 79 79 * 80 * As the GIET_TSAR does not support system calls, 80 * As the GIET_TSAR does not support system calls, 81 81 * an error message is displayed on TTY0, the program is killed. 82 82 ****************************************************************/ … … 97 97 98 98 mfc0 $4, $14 /* $4 <= EPC */ 99 la $5, _itoa_buffer /* $5 <= buffer address */ 99 la $5, _itoa_buffer /* $5 <= buffer address */ 100 100 addiu $5, $5, 2 /* skip the 0x prefix */ 101 101 jal _itoa_hex /* fill the buffer */ … … 108 108 nop 109 109 110 j _exit /* end of program */ 110 j _exit /* end of program */ 111 111 112 112 _itoa_buffer: .ascii "0x00000000" … … 122 122 * It makes the assumption that there is only one interrupt per 123 123 * entry in the interrupt vector (it can be PTI, HWI, or WTI). 124 * In case of a multi-clusters architecture, it exist one XCU 125 * per cluster, and the base address of the ICU segment depends 124 * In case of a multi-clusters architecture, it exist one XCU 125 * per cluster, and the base address of the ICU segment depends 126 126 * on both the cluster_xy and the proc_id: 127 127 * - base_address = seg_xcu_base + (32*local_id) + (4G*cluster_xy) … … 164 164 sw $31, 4*21($29) /* save $31 */ 165 165 mfc0 $27, $14 166 sw $27, 4*22($29) /* save EPC */ 166 sw $27, 4*22($29) /* save EPC */ 167 167 168 168 /* XICU PRIO register address computation */ … … 170 170 /* and we must use the physical address extension */ 171 171 mfc0 $10, $15, 1 /* $10 <= proc_id */ 172 andi $10, $10, 0x3FF /* at most 1024 processors */ 172 andi $10, $10, 0x3FF /* at most 1024 processors */ 173 173 li $11, NB_PROCS_MAX 174 174 divu $10, $11 … … 194 194 andi $27, $15, 0x4 /* test bit W in PRIO register */ 195 195 bne $27, $0, _int_WTI /* branch to WTI handler */ 196 196 197 197 /* exit interrupt handler: restore registers */ 198 198 _int_restore: … … 200 200 lw $1, 4*4($29) 201 201 .set at 202 lw $2, 4*5($29) 203 lw $3, 4*6($29) 202 lw $2, 4*5($29) 203 lw $3, 4*6($29) 204 204 lw $4, 4*7($29) 205 lw $5, 4*8($29) 205 lw $5, 4*8($29) 206 206 lw $6, 4*9($29) 207 lw $7, 4*10($29) 207 lw $7, 4*10($29) 208 208 lw $8, 4*11($29) 209 209 lw $9, 4*12($29) … … 217 217 lw $25, 4*20($29) 218 218 lw $31, 4*21($29) 219 lw $27, 4*22($29) /* get EPC */ 219 lw $27, 4*22($29) /* get EPC */ 220 220 addiu $29, $29, 23*4 /* restore SP */ 221 221 mtc0 $27, $14 /* restore EPC */ … … 233 233 la $27, _interrupt_vector 234 234 addu $26, $26, $27 235 lw $26, ($26) /* read ISR address */ 235 lw $26, ($26) /* read ISR address */ 236 236 jalr $26 /* call ISR */ 237 237 nop … … 246 246 la $27, _interrupt_vector 247 247 addu $26, $26, $27 /* $26 <= &ISR[HWI_INDEX */ 248 lw $26, ($26) /* read ISR address */ 248 lw $26, ($26) /* read ISR address */ 249 249 jalr $26 /* call ISR */ 250 250 nop … … 262 262 la $27, _interrupt_vector 263 263 addu $26, $26, $27 /* $26 <= &ISR[WTI_INDEX] */ 264 lw $26, ($26) /* read ISR address */ 264 lw $26, ($26) /* read ISR address */ 265 265 jalr $26 /* call ISR */ 266 266 nop 267 267 j _int_restore /* return from INT handler */ 268 268 nop 269 269 270 270 /* The default ISR is called when no specific ISR has been installed */ 271 271 /* in the interrupt vector. It simply displays a message on TTY0 */ … … 273 273 isr_default: 274 274 addiu $29, $29, -20 /* get space in stack */ 275 sw $31, 16($29) /* to save the return address */ 275 sw $31, 16($29) /* to save the return address */ 276 276 la $4, _msg_default /* $4 <= string address */ 277 277 addi $5, $0, 36 /* $5 <= string length */ 278 278 li $6, 0 /* $6 <= TTY0 */ 279 jal _tty_write 280 lw $31, 16($29) /* restore return address */ 279 jal _tty_write 280 lw $31, 16($29) /* restore return address */ 281 281 addiu $29, $29, 20 /* free space */ 282 282 jr $31 /* returns to interrupt handler */ … … 284 284 /**************************************************************** 285 285 * Interrupt Vector Table (indexed by interrupt index) 286 * 32 words corresponding to 32 ISR addresses 286 * 32 words corresponding to 32 ISR addresses 287 287 ****************************************************************/ 288 288 _interrupt_vector: … … 355 355 li $5, 36 /* $5 <= message length */ 356 356 li $6, 0 /* $6 <= TTY0 */ 357 jal _tty_write 357 jal _tty_write 358 358 nop 359 359 … … 362 362 li $5, 8 /* $5 <= message length */ 363 363 li $6, 0 /* $6 <= TTY0 */ 364 jal _tty_write 365 nop 366 364 jal _tty_write 365 nop 366 367 367 mfc0 $4, $14 /* $4 <= EPC value */ 368 368 la $5, _itoa_buffer /* $5 <= buffer address */ … … 377 377 nop 378 378 379 /* display BAR value */ 379 /* display BAR value */ 380 380 la $4, _msg_bar /* $4 <= message address */ 381 381 li $5, 8 /* $5 <= message length */ … … 385 385 386 386 mfc0 $4, $8 /* $4 <= BAR value */ 387 la $5, _itoa_buffer /* $5 <= buffer address */ 388 addiu $5, $5, 2 /* skip 0x prefix */ 387 la $5, _itoa_buffer /* $5 <= buffer address */ 388 addiu $5, $5, 2 /* skip 0x prefix */ 389 389 jal _itoa_hex /* fill buffer */ 390 390 nop … … 393 393 li $5, 10 /* $5 <= message length */ 394 394 li $6, 0 /* $6 <= TTY0 */ 395 jal _tty_write 396 nop 397 398 395 jal _tty_write 396 nop 397 398 399 399 /* release the lock on TTY0 */ 400 400 li $4, 0
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