Ignore:
Timestamp:
Jul 10, 2014, 11:42:14 AM (10 years ago)
Author:
cfuguet
Message:

Merge 'trunk' new modifications into 'fault_tolerance'

File:
1 edited

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  • branches/fault_tolerance/softs/giet_tsar/reset.S

    r724 r745  
    11/********************************************************************************
    2 *       File : reset.S
    3 *       Author : Alain Greiner
    4 *       Date : 15/01/2014
     2*   File : reset.S
     3*   Author : Alain Greiner
     4*   Date : 15/01/2014
    55*********************************************************************************
    66* This is a boot code for a generic multi-clusters / multi-processors
    7 * TSAR architecture (up to 256 clusters / up to 4  processors per cluster). 
     7* TSAR architecture (up to 256 clusters / up to 4  processors per cluster).
    88* The physical address is 40 bits, and the 8 MSB bits A[39:32] define the
    99* cluster index.
    1010*
    11 * As we don't want to use the virtual memory, the physical address is 
     11* As we don't want to use the virtual memory, the physical address is
    1212* equal to  the virtual address (identity mapping) and all processors stacks
    13 * and code segments are allocated in the physical memory bank in cluster 0. 
     13* and code segments are allocated in the physical memory bank in cluster 0.
    1414*
    1515* Both the reset base address and the kernel base address must be redefined
     
    2222* There is two sets of peripherals:
    2323*
    24 * 1) A block device and a single channel TTY controller are available 
     24* 1) A block device and a single channel TTY controller are available
    2525*    in cluster(0,0).
    2626*
    27 * 2) Other peripherals (including another Blockdevice, a multi-channels TTY 
     27* 2) Other peripherals (including another Blockdevice, a multi-channels TTY
    2828*    contrÃŽler, a Frame buffer) are located in cluster_io.
    2929*    For those externals peripherals, hardware interrupts (HWI) are translated
     
    3434*   - Each processor initializes the stack pointer ($29) depending on proc_id.
    3535*   - Each processor initializes the CP0 EBASE register
    36 *       - Only processor 0 initializes the Interrupt vector.
     36*   - Only processor 0 initializes the Interrupt vector.
    3737*       - Only processor 0 initializes the IOPIC component.
    3838*   - Each processor initializes its private XCU mask.
    39 *       - Each processor initializes the Status Register (SR)
    40 *       - Each processor jumps to the same main address in kernel mode...
     39*   - Each processor initializes the Status Register (SR)
     40*   - Each processor jumps to the same main address in kernel mode...
    4141********************************************************************************/
    4242
     
    4444#include "mips32_registers.h"
    4545
    46         .section .reset,"ax",@progbits
     46    .section .reset,"ax",@progbits
    4747
    48         .extern seg_stack_base
    49         .extern seg_xcu_base
     48    .extern seg_stack_base
     49    .extern seg_xcu_base
    5050        .extern seg_pic_base
    5151    .extern seg_kcode_base
    52         .extern _interrupt_vector
    53         .extern _ioc_isr
    54         .extern _mmc_isr
     52    .extern _interrupt_vector
     53    .extern _ioc_isr
     54    .extern _mmc_isr
    5555    .extern _tty_isr
    5656    .extern main
    5757
    58         .globl  reset                           
    59         .ent    reset
    60         .align  2
     58    .globl  reset
     59    .ent    reset
     60    .align  2
    6161
    6262reset:
    63         .set noreorder
     63        .set noreorder
    6464
    6565/* each proc computes  proc_id, lpid, cluster_xy */
    6666    mfc0    $26,    CP0_PROCID
    67     andi    $26,    $26,    0x3FF           /* at most 1024 processors */
     67    andi    $26,    $26,    0x3FF       /* at most 1024 processors */
    6868    move    $10,    $26                 /* $10 <= proc_id  */
    6969    li      $27,    NB_PROCS_MAX
     
    7373
    7474/* each proc initializes stack pointer (64K per processor) */
     75    srl     $8,     $12,    Y_WIDTH     /* $8  <= x */
     76    li      $9,     Y_SIZE
     77    mul     $8,     $8,     $9          /* $8  <= x * Y_SIZE */
     78    andi    $13,    $12,    (1<<Y_WIDTH)-1
     79    addu    $8,     $8,     $13         /* $8  <= x * Y_SIZE + y */
     80    mul     $8,     $8,     $27         /* $8  <= (x*Y_SIZE+y)*NB_PROCS_MAX */
     81    addu    $10,    $11,    $8          /* $10 <= (x*Y_SIZE+y)*NB_PROCS_MAX + lpid */
     82
    7583    la      $27,    seg_stack_base
    76     addi    $26,    $10,    1               /* $26 <= (proc_id + 1)           */
     84    addi    $26,    $10,    1           /* $26 <= (proc_id + 1)           */
    7785    sll     $26,    $26,    14          /* $26 <= (proc_id + 1) * 16K     */
    78     addu    $29,    $27,    $26             /* $29 <= seg_stack_base(proc_id) */
     86    addu    $29,    $27,    $26         /* $29 <= seg_stack_base(proc_id) */
    7987
    8088/* each proc initializes CP0 EBASE register */
     
    8391
    8492/* only proc (0,0,0) initializes interrupt vector for IOC, TTY, MMC     */
    85     bne     $10,    $0,    reset_xcu
     93    bne     $10,    $0,    reset_xcu
    8694    nop
    8795
    8896    la      $26,    _interrupt_vector   /* interrupt vector address                */
    89     la      $27,    _mmc_isr 
     97    la      $27,    _mmc_isr
    9098    sw      $27,    32($26)             /* interrupt_vector[8] <= _mmc_isr         */
    91     la      $27,    _ioc_isr 
     99    la      $27,    _ioc_isr
    92100    sw      $27,    36($26)             /* interrupt_vector[9] <= _ioc_isr         */
    93     la      $27,    _tty_isr 
     101    la      $27,    _tty_isr
    94102    sw      $27,    40($26)             /* interrupt_vector[10] <= _tty_isr        */
    95103
    96104/* only proc (0,0,0) initializes IOPIC : IOPIC_ADDRESS[i] <= &XICU[0].WTI_REG[i]   */
    97105
    98     li      $26,    USE_EXT_IO
    99     beq     $26,    $0,     reset_xcu   /* IOPIC not initialised if not USE_EXT_IO */
     106#if USE_IOPIC
    100107
    101108    li      $20,    X_SIZE
     
    120127
    121128    mtc2    $0,     CP2_PADDR_EXT       /* CP2_PADDR_EXT <= zero                   */
    122    
     129
     130#endif
     131
    123132reset_xcu:
    124133
     
    140149
    141150/* initializes SR register */
    142     li      $26,    0x0000FF01         
    143     mtc0    $26,    $12                         /* SR <= kernel mode / IRQ enable */
     151    li      $26,    0x0000FF01
     152    mtc0    $26,    $12                 /* SR <= kernel mode / IRQ enable */
    144153
    145154/* jumps to main in kernel mode */
    146     la      $26,    main
     155    la      $26,    main
    147156    jr      $26
    148157    nop
    149158
    150     .end        reset
     159    .end    reset
    151160
    152161    .set reorder
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