Index: branches/reconfiguration/platforms/tsar_generic_iob/arch.py
===================================================================
--- branches/reconfiguration/platforms/tsar_generic_iob/arch.py	(revision 747)
+++ branches/reconfiguration/platforms/tsar_generic_iob/arch.py	(revision 748)
@@ -8,5 +8,5 @@
 #   author : Alain Greiner
 #######################################################################################
-#  This file contains a mapping generator for the "tsar_generic_iob" platform. 
+#  This file contains a mapping generator for the "tsar_generic_iob" platform.
 #  This includes both the hardware architecture (clusters, processors, peripherals,
 #  physical space segmentation) and the mapping of all kernel objects (global vsegs).
@@ -42,5 +42,5 @@
 
     nb_ttys           = 1
-    nb_nics           = 2 
+    nb_nics           = 2
     fbf_width         = 1024
     x_io              = 0
@@ -53,13 +53,13 @@
     peri_increment    = 0x10000
     distributed_ptabs = True
-                 
+
     ### parameters checking
 
     assert( nb_procs <= 4 )
 
-    assert( (x_size == 1) or (x_size == 2) or (x_size == 4) 
+    assert( (x_size == 1) or (x_size == 2) or (x_size == 4)
              or (y_size == 8) or (x_size == 16) )
 
-    assert( (y_size == 1) or (y_size == 2) or (y_size == 4) 
+    assert( (y_size == 1) or (y_size == 2) or (y_size == 4)
              or (y_size == 8) or (y_size == 16) )
 
@@ -70,18 +70,21 @@
 
     platform_name  = 'tsar_iob_%d_%d_%d' % ( x_size, y_size, nb_procs )
-    
+
     ### define physical segments
 
-    ram_base = 0x0000000000
-    ram_size = 0x4000000                   # 64 Mbytes
-
-    xcu_base = 0x00B0000000 
-    xcu_size = 0x1000                      # 4 Kbytes 
-
-    dma_base = 0x00B1000000
-    dma_size = 0x1000 * nb_procs           # 4 Kbytes * nb_procs
-
-    mmc_base = 0x00B2000000 
-    mmc_size = 0x1000                      # 4 Kbytes
+    ram_base  = 0x0000000000
+    ram_size  = 0x4000000                  # 64 Mbytes
+
+    xcu_base  = 0x00B0000000
+    xcu_size  = 0x1000                     # 4 Kbytes
+
+    dma_base  = 0x00B1000000
+    dma_size  = 0x1000 * nb_procs          # 4 Kbytes * nb_procs
+
+    mmc_base  = 0x00B2000000
+    mmc_size  = 0x1000                     # 4 Kbytes
+
+    rom_base  = 0x00BFC00000
+    rom_size  = 0x8000                     # 32 Kbytes
 
     offset_io = ((x_io << y_width) + y_io) << (paddr_width - x_width - y_width)
@@ -106,8 +109,7 @@
 
     iob_base  = 0x00BE000000 + offset_io
-    iob_size  = 0x1000                     # 4kbytes
-
-    rom_base  = 0x00BFC00000 + offset_io
-    rom_size  = 0x4000                     # 16 Kbytes
+    iob_size  = 0x1000                     # 4 kbytes
+
+    ### GIET_VM specifics virtual segments
 
     ### define  bootloader vsegs base addresses
@@ -117,6 +119,6 @@
 
     boot_code_vbase      = 0x00040000      # ident
-    boot_code_size       = 0x00020000      # 128 Kbytes 
-  
+    boot_code_size       = 0x00020000      # 128 Kbytes
+
     boot_data_vbase      = 0x00060000      # ident
     boot_data_size       = 0x00010000      # 64 Kbytes
@@ -125,10 +127,10 @@
     boot_buffer_size     = 0x00060000      # 384 Kbytes
 
-    boot_stack_vbase     = 0x000D0000      # ident
-    boot_stack_size      = 0x00050000      # 320 Kbytes
+    boot_stack_vbase     = 0x03F00000      # ident
+    boot_stack_size      = 0x00100000      # 1 Mbytes
 
     ### define kernel vsegs base addresses
 
-    kernel_code_vbase    = 0x80000000            
+    kernel_code_vbase    = 0x80000000
     kernel_code_size     = 0x00020000      # 128 Kbytes
 
@@ -147,19 +149,19 @@
     ### create mapping
 
-    mapping = Mapping( name           = platform_name, 
-                       x_size         = x_size,        
-                       y_size         = y_size,        
-                       procs_max      = nb_procs,      
-                       x_width        = x_width,       
-                       y_width        = y_width,       
-                       paddr_width    = paddr_width,   
-                       coherence      = True,          
-                       irq_per_proc   = irq_per_proc,  
-                       use_ramdisk    = use_ramdisk,  
-                       x_io           = x_io,          
+    mapping = Mapping( name           = platform_name,
+                       x_size         = x_size,
+                       y_size         = y_size,
+                       procs_max      = nb_procs,
+                       x_width        = x_width,
+                       y_width        = y_width,
+                       paddr_width    = paddr_width,
+                       coherence      = True,
+                       irq_per_proc   = irq_per_proc,
+                       use_ramdisk    = use_ramdisk,
+                       x_io           = x_io,
                        y_io           = y_io,
-                       peri_increment = peri_increment, 
-                       ram_base       = ram_base, 
-                       ram_size       = ram_size )         
+                       peri_increment = peri_increment,
+                       ram_base       = ram_base,
+                       ram_size       = ram_size )
 
     ###  external peripherals (accessible in cluster[0,0] only for this mapping)
@@ -171,11 +173,9 @@
     tty = mapping.addPeriph( 'TTY', base = tty_base, size = tty_size, ptype = 'TTY', channels = nb_ttys )
 
-    nic = mapping.addPeriph( 'NIC', base = nic_base, size = nic_size, ptype = 'NIC', channels = nb_nics ) 
+    nic = mapping.addPeriph( 'NIC', base = nic_base, size = nic_size, ptype = 'NIC', channels = nb_nics )
 
     cma = mapping.addPeriph( 'CMA', base = cma_base, size = cma_size, ptype = 'CMA', channels = 2*nb_nics )
 
     fbf = mapping.addPeriph( 'FBF', base = fbf_base, size = fbf_size, ptype = 'FBF', arg = fbf_width )
-
-    rom = mapping.addPeriph( 'ROM', base = rom_base, size = rom_size, ptype = 'ROM' )
 
     pic = mapping.addPeriph( 'PIC', base = pic_base, size = pic_size, ptype = 'PIC', channels = 32 )
@@ -196,5 +196,5 @@
     mapping.addIrq( pic, index = 9, isrtype = 'ISR_TTY_RX', channel = 0 )
 
-    ### hardware components replicated in all clusters   
+    ### hardware components replicated in all clusters
 
     for x in xrange( x_size ):
@@ -205,12 +205,15 @@
             ram = mapping.addRam( 'RAM', base = ram_base + offset, size = ram_size )
 
-            mmc = mapping.addPeriph( 'MMC', base = mmc_base + offset, size = mmc_size, 
+            mmc = mapping.addPeriph( 'MMC', base = mmc_base + offset, size = mmc_size,
                                      ptype = 'MMC' )
 
-            dma = mapping.addPeriph( 'DMA', base = dma_base + offset, size = dma_size, 
-                                     ptype = 'DMA', channels = nb_procs ) 
-
-            xcu = mapping.addPeriph( 'XCU', base = xcu_base + offset, size = xcu_size, 
+            dma = mapping.addPeriph( 'DMA', base = dma_base + offset, size = dma_size,
+                                     ptype = 'DMA', channels = nb_procs )
+
+            xcu = mapping.addPeriph( 'XCU', base = xcu_base + offset, size = xcu_size,
                                      ptype = 'XCU', channels = nb_procs * irq_per_proc, arg = 16 )
+
+            rom = mapping.addPeriph( 'ROM', base = rom_base + offset, size = rom_size,
+                                     ptype = 'ROM' )
 
             # MMC IRQ replicated in all clusters
@@ -221,28 +224,22 @@
                 mapping.addProc( x, y, p )
 
-    ### global vsegs for boot_loader / identity mapping 
-
-    mapping.addGlobal( 'seg_boot_mapping', boot_mapping_vbase, boot_mapping_size,
-                       'C_W_', vtype = 'BLOB'  , x = 0, y = 0, pseg = 'RAM',
-                       identity = True )
-
-    mapping.addGlobal( 'seg_boot_code', boot_code_vbase, boot_code_size,
-                       'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM',
-                       identity = True )
-
-    mapping.addGlobal( 'seg_boot_data', boot_data_vbase, boot_data_size,
-                       'C_W_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM',
-                       identity = True )
-
-    mapping.addGlobal( 'seg_boot_buffer', boot_buffer_vbase, boot_buffer_size,
-                       'C_W_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM',
-                       identity = True )
-
-    mapping.addGlobal( 'seg_boot_stack', boot_stack_vbase, boot_stack_size,
-                       'C_W_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM',
-                       identity = True )
-
-    ### the code global vsegs for kernel can be replicated in all clusters 
-    ### if the page tables are distributed in all clusters.
+    ### global vsegs for boot_loader / identity mapping
+
+    mapping.addGlobal( 'seg_boot_mapping'  , boot_mapping_vbase  , boot_mapping_size  , 'C_W_',
+                       vtype = 'BLOB'  , x = 0, y = 0, pseg = 'RAM', identity = True )
+
+    mapping.addGlobal( 'seg_boot_code'     , boot_code_vbase     , boot_code_size     , 'CXW_',
+                       vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True )
+
+    mapping.addGlobal( 'seg_boot_data'     , boot_data_vbase     , boot_data_size     , 'C_W_',
+                       vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True )
+
+    mapping.addGlobal( 'seg_boot_buffer'   , boot_buffer_vbase   , boot_buffer_size   , 'C_W_',
+                       vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True )
+
+    mapping.addGlobal( 'seg_boot_stack'    , boot_stack_vbase    , boot_stack_size    , 'C_W_',
+                       vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True )
+
+    ### global vsegs for kernel
 
     if distributed_ptabs:
@@ -261,55 +258,40 @@
         mapping.addGlobal( 'seg_kernel_code', kernel_code_vbase, kernel_code_size,
                            'CXW_', vtype = 'ELF', x = 0 , y = 0 , pseg = 'RAM',
-                            binpath = 'build/kernel/kernel.elf', local = False )
+                           binpath = 'build/kernel/kernel.elf' )
 
         mapping.addGlobal( 'seg_kernel_init', kernel_init_vbase, kernel_init_size,
                            'CXW_', vtype = 'ELF', x = 0 , y = 0 , pseg = 'RAM',
-                           binpath = 'build/kernel/kernel.elf', local = False )
-
-    ### shared global vsegs for kernel
-
-    mapping.addGlobal( 'seg_kernel_data', kernel_data_vbase, kernel_data_size, 
-                       'C_W_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', 
-                       binpath = 'build/kernel/kernel.elf', local = False )
-
-    mapping.addGlobal( 'seg_kernel_uncdata', kernel_uncdata_vbase, kernel_uncdata_size,
-                       '__W_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', 
-                       binpath = 'build/kernel/kernel.elf', local = False )
+                           binpath = 'build/kernel/kernel.elf' )
+
+    mapping.addGlobal( 'seg_kernel_data'   , kernel_data_vbase   , kernel_data_size   , 'C_W_',
+                       vtype = 'ELF'   , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' )
+
+    mapping.addGlobal( 'seg_kernel_uncdata', kernel_uncdata_vbase, kernel_uncdata_size, '__W_',
+                       vtype = 'ELF'   , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' )
 
     ### global vsegs for external peripherals / identity mapping
 
-    mapping.addGlobal( 'seg_iob', iob_base, iob_size, '__W_', 
-                       vtype = 'PERI', x = 0, y = 0, pseg = 'IOB', 
-                       identity = True )
-
-    mapping.addGlobal( 'seg_bdv', bdv_base, bdv_size, '__W_', 
-                       vtype = 'PERI', x = 0, y = 0, pseg = 'BDV',
-                       identity = True )
-
-    mapping.addGlobal( 'seg_tty', tty_base, tty_size, '__W_', 
-                       vtype = 'PERI', x = 0, y = 0, pseg = 'TTY',
-                       identity = True )
-
-    mapping.addGlobal( 'seg_nic', nic_base, nic_size, '__W_', 
-                       vtype = 'PERI', x = 0, y = 0, pseg = 'NIC',
-                       identity = True )
-
-    mapping.addGlobal( 'seg_cma', cma_base, cma_size, '__W_', 
-                       vtype = 'PERI', x = 0, y = 0, pseg = 'CMA',
-                       identity = True )
-
-    mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size, '__W_', 
-                       vtype = 'PERI', x = 0, y = 0, pseg = 'FBF',
-                       identity = True )
-
-    mapping.addGlobal( 'seg_pic', pic_base, pic_size, '__W_', 
-                       vtype = 'PERI', x = 0, y = 0, pseg = 'PIC',
-                       identity = True )
-
-    mapping.addGlobal( 'seg_rom', rom_base, rom_size, 'CXW_', 
-                       vtype = 'PERI', x = 0, y = 0, pseg = 'ROM',
-                       identity = True )
-
-    ### global vsegs for internal peripherals, and for schedulers 
+    mapping.addGlobal( 'seg_iob', iob_base, iob_size, '__W_',
+                       vtype = 'PERI', x = 0, y = 0, pseg = 'IOB', identity = True )
+
+    mapping.addGlobal( 'seg_bdv', bdv_base, bdv_size, '__W_',
+                       vtype = 'PERI', x = 0, y = 0, pseg = 'BDV', identity = True )
+
+    mapping.addGlobal( 'seg_tty', tty_base, tty_size, '__W_',
+                       vtype = 'PERI', x = 0, y = 0, pseg = 'TTY', identity = True )
+
+    mapping.addGlobal( 'seg_nic', nic_base, nic_size, '__W_',
+                       vtype = 'PERI', x = 0, y = 0, pseg = 'NIC', identity = True )
+
+    mapping.addGlobal( 'seg_cma', cma_base, cma_size, '__W_',
+                       vtype = 'PERI', x = 0, y = 0, pseg = 'CMA', identity = True )
+
+    mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size, '__W_',
+                       vtype = 'PERI', x = 0, y = 0, pseg = 'FBF', identity = True )
+
+    mapping.addGlobal( 'seg_pic', pic_base, pic_size, '__W_',
+                       vtype = 'PERI', x = 0, y = 0, pseg = 'PIC', identity = True )
+
+    ### global vsegs for internal peripherals, and for schedulers
     ### name is indexed by (x,y) / vbase address is incremented by (cluster_xy * peri_increment)
 
@@ -319,4 +301,7 @@
             offset     = cluster_xy * peri_increment
 
+            mapping.addGlobal( 'seg_rom_%d_%d' %(x,y), rom_base + offset, rom_size,
+                               'CX__', vtype = 'PERI' , x = x , y = y , pseg = 'ROM' )
+
             mapping.addGlobal( 'seg_xcu_%d_%d' %(x,y), xcu_base + offset, xcu_size,
                                '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'XCU' )
@@ -348,5 +333,5 @@
 
 #   print mapping.giet_vsegs()
-                     
+
 
 # Local Variables:
