Ignore:
Timestamp:
Jul 18, 2014, 11:38:54 AM (10 years ago)
Author:
meunier
Message:
  • Added initialization to some components in order to avoid valgrind errors
  • Corrected two bugs which caused the simulations to be non-deterministic:
    • one in the memcache (possibly uninitialized paddr variable used for cache access, modifying LRU bits)
    • one in the run_simus.py script (replacing a file with an identical file in a hdd image does modify its size)
File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/platforms/almos-tsar-mipsel/top.cpp

    r614 r752  
    201201/////////////////////////////////////////////////////////
    202202// There is 3 segments replicated in all clusters
    203 // and 5 specific segments in the "IO" cluster 
     203// and 5 specific segments in the "IO" cluster
    204204// (containing address 0xBF000000)
    205205/////////////////////////////////////////////////////////
    206206// Physical Address Decoding: 8 GID + 8 LID + 16 offset.
    207207/////////////////////////////////////////////////////////
    208 #define RAM_BASE        0x00000000     
     208#define RAM_BASE        0x00000000
    209209#define RAM_SIZE        0x00C00000
    210210
    211 #define BROM_BASE       0xBFC00000     
     211#define BROM_BASE       0xBFC00000
    212212#define BROM_SIZE       0x00100000
    213213
    214 #define FBUF_BASE       0xBFD00000     
     214#define FBUF_BASE       0xBFD00000
    215215#define FBUF_SIZE       0x00200000
    216216
    217 #define XICU_BASE       0x00F00000     
     217#define XICU_BASE       0x00F00000
    218218#define XICU_SIZE       0x00002000
    219219
     
    221221#define BDEV_SIZE       0x00000100
    222222
    223 #define MTTY_BASE       0xBFF20000     
     223#define MTTY_BASE       0xBFF20000
    224224#define MTTY_SIZE       0x00000100
    225225
     
    227227#define MDMA_SIZE       0x00001000 * NB_DMA_CHANNELS  // 4 Kbytes per channel
    228228
    229 #define MEMC_BASE       0x00F40000     
     229#define MEMC_BASE       0x00F40000
    230230#define MEMC_SIZE       0x00001000
    231231
     
    233233#define SIMH_SIZE       0x00001000
    234234
    235 #define CDMA_BASE       0xBFF60000     
     235#define CDMA_BASE       0xBFF60000
    236236#define CDMA_SIZE       0x00000100
    237237
     
    255255   bool     debug_ok         = false;              // trace activated
    256256   size_t   debug_period     = 1;                  // trace period
    257    size_t   debug_memc_id    = 0;                  // index of memc to be traced 
     257   size_t   debug_memc_id    = 0;                  // index of memc to be traced
    258258   size_t   debug_proc_id    = 0;                  // index of proc to be traced
    259259   uint32_t debug_from       = 0;                  // trace start cycle
     
    596596   {
    597597      for (size_t y = 0; y < ymax ; y++)
    598       { 
     598      {
    599599
    600600         sc_uint<vci_address_width> offset;
     
    781781      }
    782782   }
    783    std::cout << std::endl << "Horizontal connections established" << std::endl;   
     783   std::cout << std::endl << "Horizontal connections established" << std::endl;
    784784
    785785   // Inter Clusters vertical connections
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