Changeset 767 for branches/RWT/lib

Aug 25, 2014, 5:58:16 PM (9 years ago)

RWT commit :

  • Merge with trunk.
  • Cosmetic
  • Bugfix in state WRITE_IVT_LOCK_HIT_WB.

MemCache? records invalidation in IVT in this state but we do not check that
the IVT was full. Thus invalidation was issued without actually recorded in the
query IVT ...

  • Bugfix :

When a NCC line owned by a L1 cache with srcid != 0 was removed from MemCache?,
the owner field was reset to 0. If this same L1 cache was sending a read to
retrieve this line the MemCache? sent this line on CC mode.

  • Bugfix :

The MemCache? reset the 'inst' field to 0 when solving a
invalidation due to a change of state of line (NCC to CC).
But a line can be NCC (ie contained in a DATA cache) then asked by INST cache,
this read triggers a transition NCC to CC but we must save the nature of this read.
Now this information is stored in a register (r_read_to_cleanup_inst).

  • Add a counter for the number of minimum inputs available

in the heap. This counter indicates whether the heap size of 4096 is relevant.

1 edited


  • branches/RWT/lib/generic_cache_tsar/include/generic_cache.h

    r477 r767  
    586586                      data_t    data)
    587587    {
    588        /**/ //std::cout << "write cache : way = "<<way<<" | set = "<<set<<" | word = "<<word<<" | data = "<<(uint32_t)data << std::endl;
    589588        cache_data(way, set, word) = data;
    590589        cache_set_lru(way, set);
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