Index: branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
===================================================================
--- branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 646)
+++ branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 767)
@@ -346,7 +346,4 @@
       r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
       r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
-//     r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
-//     r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
-//     r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
       r_dcache_tlb_way("r_dcache_tlb_way"),
       r_dcache_tlb_set("r_dcache_tlb_set"),
@@ -425,8 +422,8 @@
 
     assert( (itlb_sets == dtlb_sets) and
-             "itlb_sets and dtlb_sets parameters must be etqual");
+             "itlb_sets and dtlb_sets parameters must be equal");
 
     assert( (itlb_ways == dtlb_ways) and
-             "itlb_ways and dtlb_ways parameters must be etqual");
+             "itlb_ways and dtlb_ways parameters must be equal");
 
     r_mmu_params = (uint32_log2(m_dtlb_ways)   << 29)   | (uint32_log2(m_dtlb_sets)   << 25) |
@@ -470,12 +467,9 @@
 /////////////////////////////////////
 {
-    ////////////MODIFIED/////////////
-    //delete [] r_dcache_in_tlb;
-    //delete [] r_dcache_contains_ptd;
     delete [] r_dcache_content_state;
     delete [] r_dcache_dirty_word;
     delete [] r_dcache_zombi_ncc;
     /////////////////////////////////
-    print_stats();
+    //print_stats();
 }
 
@@ -783,7 +777,4 @@
         for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++)
         {
-            // MODIFIED
-            //r_dcache_in_tlb[i]        = false;
-            //r_dcache_contains_ptd[i]  = false;
             r_dcache_content_state[i] = LINE_CACHE_DATA_NOT_DIRTY;
             r_dcache_dirty_word[i]    = 0;
@@ -2246,5 +2237,4 @@
     m_drsp.error = false;
     m_drsp.rdata = 0;
-    //if(m_cpt_total_cycles % 1000000 == 0 ) r_dcache.printTrace();
 
     switch ( r_dcache_fsm.read() )
@@ -2381,7 +2371,5 @@
             size_t way = r_dcache_save_cache_way.read();
             size_t set = r_dcache_save_cache_set.read();
-            // MODIFIED
-            //if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
-            //{
+
             if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB )
             {
@@ -2390,17 +2378,12 @@
 	            r_dcache_tlb_inval_line  = r_dcache_save_paddr.read()>>
                                            (uint32_log2(m_dcache_words<<2));
-                // MODIFIED RWT: DIRTY
-	            //r_dcache_in_tlb[way*m_dcache_sets+set] = false;
+
                 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY;
             }
-            // MODIFIED
-            //else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
-            //{
             else if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD )
             {
                 r_itlb.reset();
                 r_dtlb.reset();
-                // MODIFIED
-	            //r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
+
                 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY;
             }
@@ -2802,6 +2785,4 @@
 m_cpt_data_miss++;
 #endif
-                                /*ODCCP*/
-                                //std::cout << "\t\t\t\t\tCACHE MISS NEED READ for : " << name() << std::endl;
                                 // request a VCI DMISS transaction
                                 r_dcache_vci_paddr    = paddr;
@@ -2832,12 +2813,4 @@
 m_cpt_data_read++;
 #endif
-                                /*if ((tlb_flags.s == 0) and (r_mmu_mode.read() & DATA_TLB_MASK) and (cache_state == CACHE_SLOT_STATE_VALID_CC))
-                                {
-                                    //ODCCP
-                                    std::cout << "READ NO COHERENCE on " << name() << " | paddr = " << std::hex << paddr << std::dec << " | way = " << cache_way << " | set = " << cache_set << " | at cycle : "<< m_cpt_total_cycles << std::endl;
-                                    r_dcache.write_dir(cache_way,
-                                                       cache_set,
-                                                       CACHE_SLOT_STATE_VALID_NCC);
-                                }*/
                                 // returns data to processor
                                 m_drsp.valid   = true;
@@ -2883,6 +2856,4 @@
                         r_dcache_ll_rsp_count = 0;
                         r_dcache_fsm          = DCACHE_LL_WAIT;
-                        /*ODCCP*/
-                        //std::cout << "LL on " << name() << " | paddr = " << std::hex << paddr << std::dec << " | at cycle : " << m_cpt_total_cycles << std::endl;
 
                     }// end LL
@@ -2973,11 +2944,10 @@
                                 m_cpt_data_write_on_zombi++;
                             }
-                            else
+                            else // Miss in DCACHE
                             {
-                               m_cpt_data_write_miss++;
-                               
-                               m_drsp.valid = true;
-                               wbuf_request = true;
-                               updt_request = false;
+                                m_drsp.valid = true;
+                                wbuf_request = true;
+                                updt_request = false;
+                                m_cpt_data_write_miss++;
                             }
                         }
@@ -3155,11 +3125,10 @@
                        &word,
                        &cache_state );
+
 #ifdef INSTRUMENTATION
 m_cpt_dcache_data_read++;
 m_cpt_dcache_dir_read++;
 #endif
-        /*ODCCP*/
-//        assert((cache_state != CACHE_SLOT_STATE_VALID_NCC) and "DCACHE_TLB_PTE1_GET : IMPOSSIBLE NCC HERE");
-//        if ( cache_state == CACHE_SLOT_STATE_VALID_CC )   // hit in dcache
+
         if (( cache_state == CACHE_SLOT_STATE_VALID_NCC ) or ( cache_state == CACHE_SLOT_STATE_VALID_CC ))
         {
@@ -3199,6 +3168,4 @@
             {
                 // mark the cache line ac containing a PTD
-                //MODIFIED
-                //r_dcache_contains_ptd[m_dcache_sets*way+set] = true;
                 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_CONTAINS_PTD;
 
@@ -3236,11 +3203,6 @@
             else			//  PTE1 :  we must update the TLB
             {
-                // MODIFIED
-                //r_dcache_in_tlb[m_icache_sets*way+set] = true;
                 r_dcache_content_state[m_icache_sets*way+set] = LINE_CACHE_IN_TLB;
                 r_dcache_tlb_pte_flags  = entry;
-               //r_dcache_tlb_cache_way  = way;
-               //r_dcache_tlb_cache_set  = set;
-               //r_dcache_tlb_cache_word = word;
                 r_dcache_fsm            = DCACHE_TLB_PTE1_SELECT;
 
@@ -3479,7 +3441,4 @@
 m_cpt_dcache_dir_read++;
 #endif
-        /*ODCCP*/
-//        assert((cache_state != CACHE_SLOT_STATE_VALID_NCC) and "DCACHE_TLB_PTE2_GET : IMPOSSIBLE NCC HERE");
-//        if (cache_state == CACHE_SLOT_STATE_VALID_CC)    // hit in dcache
         if ((cache_state == CACHE_SLOT_STATE_VALID_CC) or (cache_state == CACHE_SLOT_STATE_VALID_NCC))
         {
@@ -3514,12 +3473,7 @@
             else				// mapped : we must update the TLB
             {
-                // MODIFIED
-                //r_dcache_in_tlb[m_dcache_sets*way+set] = true;
                 r_dcache_content_state[m_dcache_sets*way+set] = LINE_CACHE_IN_TLB;
                 r_dcache_tlb_pte_flags  = pte_flags;
                 r_dcache_tlb_pte_ppn    = pte_ppn;
-               //r_dcache_tlb_cache_way  = way;
-               //r_dcache_tlb_cache_set  = set;
-               //r_dcache_tlb_cache_word = word;
                 r_dcache_fsm            = DCACHE_TLB_PTE2_SELECT;
 
@@ -4002,5 +3956,4 @@
                                &tag,
                                &state );
-            /*ODCCP*/
 
             if ( state == CACHE_SLOT_STATE_VALID_CC )         // inval required
@@ -4031,6 +3984,6 @@
                 r_dcache_miss_set     = set;
                 r_dcache_cc_cleanup_line_ncc = true;
+
                 if (r_dcache_content_state[m_dcache_sets*way+set] != LINE_CACHE_DATA_NOT_DIRTY)//Must send data in the cleanup
-                //if (true)//Must send data in the cleanup
                 {
                     r_dcache_xtn_flush_addr_data = (tag * m_dcache_sets + set) * m_dcache_words * 4;
@@ -4092,10 +4045,4 @@
             }
         }
-//       else if ( r_dcache_clack_req.read() )
-//       {
-//           r_dcache_fsm = DCACHE_CC_CHECK;
-//           r_dcache_fsm_cc_save = r_dcache_fsm.read();
-//           break;
-//       }
         break;
     }
@@ -4109,7 +4056,4 @@
         size_t set = r_dcache_miss_set.read();
 
-        // MODIFIED
-        //r_dcache_in_tlb[m_dcache_sets*way+set]       = false;
-        //r_dcache_contains_ptd[m_dcache_sets*way+set] = false;
         r_dcache_content_state[m_dcache_sets*way+set]  = LINE_CACHE_DATA_DIRTY;
 
@@ -4215,6 +4159,5 @@
                            &set,
                            &word );
-        /*ODCCP*/
-        //assert((state != CACHE_SLOT_STATE_VALID_NCC) and "NOT YET DONE");
+
         if ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC))	// inval to be done
         {
@@ -4266,5 +4209,5 @@
 m_cpt_dcache_dir_write++;
 #endif
-            // MODIFIER POUR DIRTY BIT //
+
             if ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC))// request cleanup
             {
@@ -4284,5 +4227,4 @@
                     r_dcache_cc_cleanup_line_ncc = true;
                     if ((r_dcache_content_state[way*m_dcache_sets+set] != LINE_CACHE_DATA_NOT_DIRTY)) //must send data
-                    //if (true) //must send data
                     {
                         r_dcache_cc_cleanup_updt_data = true;
@@ -4305,10 +4247,6 @@
                 }
             }
-            /*ODCCP*/
 
             // possible itlb & dtlb invalidate
-            // MODIFIED
-            //if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
-            //{
             if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB )
             {
@@ -4317,17 +4255,10 @@
                 r_dcache_fsm_scan_save  = DCACHE_XTN_DC_INVAL_END;
                 r_dcache_fsm            = DCACHE_INVAL_TLB_SCAN;
-                // MODIFIED
-                //r_dcache_in_tlb[way*m_dcache_sets+set] = false;
                 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY;
             }
-            // MODIFIED
-            //else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
-            //{
             else if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD)
             {
                 r_itlb.reset();
                 r_dtlb.reset();
-                // MODIFIED
-                //r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
                 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY;
                 r_dcache_fsm = DCACHE_IDLE;
@@ -4354,5 +4285,5 @@
     /*ODCCP*/
     //////////////////////////////
-    case DCACHE_XTN_DC_INVAL_DATA:  	//A verifier
+    case DCACHE_XTN_DC_INVAL_DATA:
     {
 
@@ -4420,12 +4351,12 @@
         }
 
-            bool     found = false;
-            bool     cleanup = false;
-            size_t   way = 0;
-            size_t   set = 0;
-            paddr_t  victim = 0;
-            int state;
-            bool     s_cleanup_updt_data = false;
-            bool     s_cleanup_line_ncc = false;
+            bool    found = false;
+            bool    cleanup = false;
+            size_t  way = 0;
+            size_t  set = 0;
+            paddr_t victim = 0;
+            int     state;
+            bool    s_cleanup_updt_data = false;
+            bool    s_cleanup_line_ncc = false;
 
 #ifdef INSTRUMENTATION
@@ -4449,11 +4380,9 @@
                     r_dcache_miss_clack   = true;
                     r_dcache_fsm          = DCACHE_MISS_CLEAN;
-                    if( (state == CACHE_SLOT_STATE_VALID_NCC) )//and (r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_DATA_DIRTY) )
+                    if( (state == CACHE_SLOT_STATE_VALID_NCC) )
                     {
-                        //MODIFIER POUR DIRTY BIT //
                         s_cleanup_line_ncc = true;
                         r_dcache_miss_data_addr = (victim*m_dcache_words)*4;
                         if ((r_dcache_content_state[way*m_dcache_sets+set] != LINE_CACHE_DATA_NOT_DIRTY))//must send data
-                        //if (true)//must send data
                         {
                             s_cleanup_updt_data = true;
@@ -4472,5 +4401,4 @@
                             m_cpt_cleanup_data_not_dirty ++;
                     }
-                        
                     else
                     {
@@ -4555,10 +4483,4 @@
             }
         }
-//       else if ( r_dcache_clack_req.read() )
-//       {
-//           r_dcache_fsm = DCACHE_CC_CHECK;
-//           r_dcache_fsm_cc_save = r_dcache_fsm.read();
-//           break;
-//       }
 
         break;
@@ -4590,11 +4512,6 @@
         // if selective itlb & dtlb invalidate are required
         // the miss response is not handled before invalidate completed
-        // MODIFIED
-        //if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
-        //{
         if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB )
         {
-            //MODIFIED
-            //r_dcache_in_tlb[way*m_dcache_sets+set] = false;
             r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY;
             if( not r_dcache_cleanup_victim_req.read() )
@@ -4610,13 +4527,8 @@
             r_dcache_fsm             = DCACHE_INVAL_TLB_SCAN;
         }
-        // MODIFIED
-        //else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
-        //{
         else if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD )
         {
             r_itlb.reset();
             r_dtlb.reset();
-            // MODIFIED
-            //r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
             r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY;
             r_dcache_fsm = DCACHE_MISS_WAIT;
@@ -4846,5 +4758,5 @@
                 if (r_dcache_read_state.read())
                 {
-                  r_dcache.write_dir( r_dcache_save_paddr.read(),
+                    r_dcache.write_dir( r_dcache_save_paddr.read(),
                                         r_dcache_miss_way.read(),
                                         r_dcache_miss_set.read(),
@@ -4856,5 +4768,5 @@
                 else
                 {
-                  r_dcache.write_dir( r_dcache_save_paddr.read(),
+                    r_dcache.write_dir( r_dcache_save_paddr.read(),
                                         r_dcache_miss_way.read(),
                                         r_dcache_miss_set.read(),
@@ -4878,9 +4790,4 @@
           << " / SET = "   << r_dcache_miss_set.read() << std::endl;
 #endif
-                // reset directory extension
-
-                // MODIFIED
-                //r_dcache_in_tlb[way*m_dcache_sets+set] = false;
-                //r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
             }
             if      (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
@@ -5157,5 +5064,5 @@
                            word,
                            r_dcache_vci_cas_new.read());
-            //std::cout << "CAS local" << std::endl;
+
             if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB )
             {
@@ -5317,8 +5224,8 @@
         r_dcache_cc_way = way;
         r_dcache_cc_set = set;
-            /*RWT / ODCCP*/
-        if ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC))             // hit
-        {
-          // need to update the cache state
+
+        if ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC))  // hit
+        {
+            // need to update the cache state
             r_dcache_cc_need_write = true;
             r_dcache_cc_cleanup_line_ncc = false;
@@ -5424,43 +5331,43 @@
             }
         }
-            assert (not r_dcache_cc_send_req.read() &&
+        assert (not r_dcache_cc_send_req.read() &&
                     "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req "
                     "must not be set");
-            // coherence request completed
-                r_cc_receive_dcache_req = false;
-            // request multicast acknowledgement
-                r_dcache_cc_send_req = true;
-                r_dcache_cc_send_way = way;
-                r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
-                r_dcache_cc_send_type = CC_TYPE_CLEANUP;
-                // MODIFIER POUR DIRTY BIT //
-                if (cache_state == CACHE_SLOT_STATE_VALID_NCC and not r_cc_receive_dcache_inval_is_config.read())
+        // coherence request completed
+        r_cc_receive_dcache_req = false;
+        // request multicast acknowledgement
+        r_dcache_cc_send_req = true;
+        r_dcache_cc_send_way = way;
+        r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
+        r_dcache_cc_send_type = CC_TYPE_CLEANUP;
+
+        if (cache_state == CACHE_SLOT_STATE_VALID_NCC and not r_cc_receive_dcache_inval_is_config.read())
+        {
+            r_dcache_cc_cleanup_line_ncc = true; 
+            if ((r_dcache_content_state[way*m_dcache_sets+set] != LINE_CACHE_DATA_NOT_DIRTY) or r_dcache_dirty_save.read() or dirty_save) //must send data
+            {
+                r_dcache_cc_cleanup_updt_data = true;
+                for (size_t w = 0; w< m_dcache_words; w++)
                 {
-                    r_dcache_cc_cleanup_line_ncc = true; 
-                    if ((r_dcache_content_state[way*m_dcache_sets+set] != LINE_CACHE_DATA_NOT_DIRTY) or r_dcache_dirty_save.read() or dirty_save) //must send data
-                    {
-                        r_dcache_cc_cleanup_updt_data = true;
-                        for (size_t w = 0; w< m_dcache_words; w++)
-                        {
-                            m_cpt_cleanup_data_dirty_word += r_dcache_dirty_word[(m_dcache_sets*way+set)*m_dcache_words + w];
-                        }
-
-                        r_dcache_fsm          = DCACHE_CC_INVAL_DATA;
-                    }
-                    else
-                    {
-                        r_dcache.write_dir( way,
-                                            set,
-                                            CACHE_SLOT_STATE_ZOMBI );
+                    m_cpt_cleanup_data_dirty_word += r_dcache_dirty_word[(m_dcache_sets*way+set)*m_dcache_words + w];
+                }
+
+                r_dcache_fsm          = DCACHE_CC_INVAL_DATA;
+            }
+            else
+            {
+                r_dcache.write_dir( way,
+                                    set,
+                                    CACHE_SLOT_STATE_ZOMBI );
  
-                        r_dcache_cc_cleanup_updt_data = false;
-                        r_dcache_fsm = r_dcache_fsm_cc_save.read();
-                    }
-                }
-                else
-                {
-                    r_dcache_cc_cleanup_updt_data = false;
-                    r_dcache_fsm = r_dcache_fsm_cc_save.read();
-                }
+                r_dcache_cc_cleanup_updt_data = false;
+                r_dcache_fsm = r_dcache_fsm_cc_save.read();
+            }
+        }
+        else
+        {
+            r_dcache_cc_cleanup_updt_data = false;
+            r_dcache_fsm = r_dcache_fsm_cc_save.read();
+        }
 
         break;
@@ -6220,7 +6127,7 @@
             if (p_dspin_p2m.read.read())
             {
-                //std::cout << "CLEANUP send on line " << r_dcache_cc_send_nline.read() << std::endl;
+
                 if(r_dcache_cc_cleanup_updt_data.read() and (r_cc_send_last_client.read() == 0))//dcache request with data
-               {
+                {
                     r_cc_send_fsm = CC_SEND_CLEANUP_DATA_UPDT;
                 }
@@ -6248,5 +6155,4 @@
                 if(r_cc_send_data_fifo.rok())
                 {
-                    /*ODCCP*///std::cout<<"CLEANUP_DATA_UPDT" << std::endl;
                     m_cpt_data_cleanup++;
                     cleanup_data_updt_fifo_dcache_get = true;
@@ -6254,7 +6160,4 @@
                     if (r_cc_send_cpt_word.read() == m_dcache_words-1)
                     {
-                        //std::cout << "L1 paddr CLEANUP DATA | paddr = " << std::hex << (r_dcache_cc_send_nline.read()*m_dcache_words)*4 << std::dec << std::endl;
-                        /*ODCCP*/
-                        //std::cout << "CLEANUP with DATA finished by " << name() << std::endl;
                         r_dcache_cc_send_req = false;
                         r_dcache_cc_cleanup_updt_data = false;
@@ -6583,5 +6486,5 @@
                                  vci_rsp_fifo_dcache_put,
                                  vci_rsp_fifo_dcache_data);
-    //BUG pktid
+
     r_vci_rsp_fifo_rpktid.update(vci_rsp_fifo_rpktid_get,
                                  vci_rsp_fifo_rpktid_put,
@@ -6798,7 +6701,4 @@
         {
             // initialize dspin send data
-//            DspinDhccpParam::dspin_set(dspin_send_data,
-//                                       0,
-//                                       DspinDhccpParam::P2M_EOP);
             DspinDhccpParam::dspin_set(dspin_send_data,
                                        m_cc_global_id,
@@ -6892,16 +6792,4 @@
         case CC_SEND_CLEANUP_DATA_UPDT:
         {
-            /*if (r_cc_send_cpt_word.read() == m_dcache_words-1)
-            {
-                DspinDhccpParam::dspin_set(dspin_send_data,
-                                           1,
-                                           DspinDhccpParam::FROM_L1_EOP);
-            }
-            else
-            {
-                DspinDhccpParam::dspin_set(dspin_send_data,
-                                           0,
-                                           DspinDhccpParam::FROM_L1_EOP);
-            }*/
 
             DspinDhccpParam::dspin_set(dspin_send_data,
@@ -6910,5 +6798,4 @@
             
             p_dspin_p2m.data = dspin_send_data;
-            //std::cout << "genmoore CLEANUP DATA UPDT : dspin_send_data = " << std::hex << dspin_send_data << std::dec << std::endl;
             p_dspin_p2m.write = true;
             p_dspin_p2m.eop = (r_cc_send_cpt_word.read() == m_dcache_words-1);
@@ -6919,7 +6806,4 @@
         {
             // initialize dspin send data
-//            DspinDhccpParam::dspin_set(dspin_send_data,
-//                                       1,
-//                                       DspinDhccpParam::P2M_EOP);
             DspinDhccpParam::dspin_set(dspin_send_data,
                                        0,
