- Timestamp:
- Sep 17, 2014, 1:17:56 PM (10 years ago)
- Location:
- branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source
- Files:
-
- 2 edited
-
include/tsar_iob_cluster.h (modified) (15 diffs)
-
src/tsar_iob_cluster.cpp (modified) (22 diffs)
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branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h
r748 r806 1 1 ////////////////////////////////////////////////////////////////////////////// 2 2 // File: tsar_iob_cluster.h 3 // Author: Alain Greiner 3 // Author: Alain Greiner 4 4 // Copyright: UPMC/LIP6 5 5 // Date : april 2013 … … 37 37 38 38 /////////////////////////////////////////////////////////////////////////// 39 template<typename vci_param_int, 39 template<typename vci_param_int, 40 40 typename vci_param_ext, 41 size_t dspin_int_cmd_width, 41 size_t dspin_int_cmd_width, 42 42 size_t dspin_int_rsp_width, 43 43 size_t dspin_ram_cmd_width, 44 44 size_t dspin_ram_rsp_width> 45 class TsarIobCluster 45 class TsarIobCluster 46 46 /////////////////////////////////////////////////////////////////////////// 47 47 : public soclib::caba::BaseModule … … 56 56 // Thes two ports are used to connect IOB to IOX nework in top cell 57 57 soclib::caba::VciInitiator<vci_param_ext>* p_vci_iob_iox_ini; 58 soclib::caba::VciTarget<vci_param_ext>* p_vci_iob_iox_tgt; 58 soclib::caba::VciTarget<vci_param_ext>* p_vci_iob_iox_tgt; 59 59 60 60 // These arrays of ports are used to connect the INT & RAM networks in top cell … … 74 74 sc_signal<bool> signal_irq_mdma[8]; 75 75 sc_signal<bool> signal_irq_memc; 76 76 77 77 // INT network DSPIN signals between DSPIN routers and DSPIN local_crossbars 78 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_l2g_d; 79 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_g2l_d; 78 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_l2g_d; 79 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_g2l_d; 80 80 DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_l2g_c; 81 DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_g2l_c; 81 DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_g2l_c; 82 82 DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_l2g_c; 83 83 DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_g2l_c; 84 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_l2g_d; 85 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_g2l_d; 84 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_l2g_d; 85 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_g2l_d; 86 86 DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_l2g_c; 87 87 DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_g2l_c; 88 88 89 89 // INT network VCI signals between VCI components and VCI local crossbar 90 VciSignals<vci_param_int> signal_int_vci_ini_proc[8]; 91 VciSignals<vci_param_int> signal_int_vci_ini_mdma; 92 VciSignals<vci_param_int> signal_int_vci_ini_iobx; 90 VciSignals<vci_param_int> signal_int_vci_ini_proc[8]; 91 VciSignals<vci_param_int> signal_int_vci_ini_mdma; 92 VciSignals<vci_param_int> signal_int_vci_ini_iobx; 93 93 94 94 VciSignals<vci_param_int> signal_int_vci_tgt_memc; … … 101 101 VciSignals<vci_param_int> signal_int_vci_g2l; 102 102 103 // Coherence DSPIN signals between DSPIN local crossbars and CC components 103 // Coherence DSPIN signals between DSPIN local crossbars and CC components 104 104 DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_memc; 105 105 DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_memc; … … 115 115 116 116 // RAM network DSPIN signals between VCI/DSPIN wrappers, RAM dspin crossbar 117 // and routers 117 // and routers 118 118 DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_xram_t; 119 119 DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_xram_t; … … 126 126 DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_false; 127 127 DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_false; 128 128 129 129 ////////////////////////////////////// 130 130 // Hardwate Components (pointers) 131 131 ////////////////////////////////////// 132 VciCcVCacheWrapper<vci_param_int, 132 VciCcVCacheWrapper<vci_param_int, 133 133 dspin_int_cmd_width, 134 134 dspin_int_rsp_width, … … 136 136 137 137 VciMemCache<vci_param_int, 138 vci_param_ext, 139 dspin_int_rsp_width, 138 vci_param_ext, 139 dspin_int_rsp_width, 140 140 dspin_int_cmd_width>* memc; 141 141 … … 151 151 152 152 VciLocalCrossbar<vci_param_int>* int_xbar_d; 153 153 154 154 VciDspinInitiatorWrapper<vci_param_int, 155 155 dspin_int_cmd_width, … … 172 172 dspin_ram_cmd_width, 173 173 dspin_ram_rsp_width>* xram_ram_wt; 174 174 175 175 DspinRouter<dspin_ram_cmd_width>* ram_router_cmd; 176 176 DspinRouter<dspin_ram_rsp_width>* ram_router_rsp; … … 178 178 DspinLocalCrossbar<dspin_ram_cmd_width>* ram_xbar_cmd; 179 179 DspinLocalCrossbar<dspin_ram_rsp_width>* ram_xbar_rsp; 180 180 181 181 182 182 // IO Network Components (not instanciated in all clusters) … … 191 191 // cluster constructor 192 192 TsarIobCluster( sc_module_name insname, 193 size_t nb_procs, 194 size_t nb_dmas, 193 size_t nb_procs, 194 size_t nb_dmas, 195 195 size_t x, // x coordinate 196 196 size_t y, // y coordinate 197 size_t xmax, 198 size_t ymax, 197 size_t x_size, 198 size_t y_size, 199 200 size_t p_width, // pid field bits 199 201 200 202 const soclib::common::MappingTable &mt_int, … … 226 228 size_t memc_sets, 227 229 size_t l1_i_ways, 228 size_t l1_i_sets, 230 size_t l1_i_sets, 229 231 size_t l1_d_ways, 230 size_t l1_d_sets, 231 size_t xram_latency, 232 size_t l1_d_sets, 233 size_t xram_latency, 232 234 size_t xcu_nb_inputs, 233 235 … … 236 238 const Loader &loader, // loader for XRAM 237 239 238 uint32_t frozen_cycles, 240 uint32_t frozen_cycles, 239 241 uint32_t start_debug_cycle, 240 bool memc_debug_ok, 241 bool proc_debug_ok, 242 bool iob0_debug_ok ); 242 bool memc_debug_ok, 243 bool proc_debug_ok, 244 bool iob0_debug_ok ); 243 245 244 246 protected: … … 247 249 248 250 void init(); 249 251 250 252 251 253 }; -
branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp
r748 r806 1 1 ////////////////////////////////////////////////////////////////////////////// 2 2 // File: tsar_iob_cluster.cpp 3 // Author: Alain Greiner 3 // Author: Alain Greiner 4 4 // Copyright: UPMC/LIP6 5 5 // Date : april 2013 6 6 // This program is released under the GNU public license 7 7 ////////////////////////////////////////////////////////////////////////////// 8 // Cluster(0,0) & Cluster(x max-1,ymax-1) contains the IOB0 & IOB1 components.8 // Cluster(0,0) & Cluster(x_size-1,y_size-1) contains the IOB0 & IOB1 components. 9 9 // These two clusters contain 6 extra components: 10 10 // - 1 vci_io_bridge (connected to the 3 networks. 11 11 // - 3 vci_dspin_wrapper for the IOB. 12 // - 2 dspin_local_crossbar for commands and responses. 12 // - 2 dspin_local_crossbar for commands and responses. 13 13 ////////////////////////////////////////////////////////////////////////////// 14 14 … … 30 30 ////////////////////////////////////////////////////////////////////////// 31 31 tmpl(/**/)::TsarIobCluster( 32 ////////////////////////////////////////////////////////////////////////// 33 sc_module_name insname, 34 size_t nb_procs, 35 size_t nb_dmas, 36 size_t x_id, 37 size_t y_id, 38 size_t xmax, 39 size_t ymax, 40 41 const soclib::common::MappingTable &mt_int, 42 const soclib::common::MappingTable &mt_ram, 43 const soclib::common::MappingTable &mt_iox, 44 45 size_t x_width, 46 size_t y_width, 47 size_t l_width, 48 49 size_t int_memc_tgt_id, // local index 50 size_t int_xicu_tgt_id, // local index 51 size_t int_mdma_tgt_id, // local index 52 size_t int_brom_tgt_id, // local index 53 size_t int_iobx_tgt_id, // local index 54 55 size_t int_proc_ini_id, // local index 56 size_t int_mdma_ini_id, // local index 57 size_t int_iobx_ini_id, // local index 58 59 size_t ram_xram_tgt_id, // local index 60 size_t ram_memc_ini_id, // local index 61 size_t ram_iobx_ini_id, // local index 62 63 bool is_io, // is IO cluster (IOB)? 64 size_t iox_iobx_tgt_id, // local_index 65 size_t iox_iobx_ini_id, // local index 66 67 size_t memc_ways, 68 size_t memc_sets, 69 size_t l1_i_ways, 70 size_t l1_i_sets, 71 size_t l1_d_ways, 72 size_t l1_d_sets, 73 size_t xram_latency, 74 size_t xcu_nb_inputs, 75 76 bool distboot, 77 78 const Loader &loader, 79 80 uint32_t frozen_cycles, 81 uint32_t debug_start_cycle, 82 bool memc_debug_ok, 83 bool proc_debug_ok, 84 bool iob_debug_ok ) 85 : soclib::caba::BaseModule(insname), 86 p_clk("clk"), 87 p_resetn("resetn") 32 sc_module_name insname, 33 size_t nb_procs, 34 size_t nb_dmas, 35 size_t x_id, 36 size_t y_id, 37 size_t x_size, 38 size_t y_size, 39 40 size_t p_width, 41 42 const soclib::common::MappingTable &mt_int, 43 const soclib::common::MappingTable &mt_ram, 44 const soclib::common::MappingTable &mt_iox, 45 46 size_t x_width, 47 size_t y_width, 48 size_t l_width, 49 50 size_t int_memc_tgt_id, // local index 51 size_t int_xicu_tgt_id, // local index 52 size_t int_mdma_tgt_id, // local index 53 size_t int_brom_tgt_id, // local index 54 size_t int_iobx_tgt_id, // local index 55 56 size_t int_proc_ini_id, // local index 57 size_t int_mdma_ini_id, // local index 58 size_t int_iobx_ini_id, // local index 59 60 size_t ram_xram_tgt_id, // local index 61 size_t ram_memc_ini_id, // local index 62 size_t ram_iobx_ini_id, // local index 63 64 bool is_io, // is IO cluster (IOB)? 65 size_t iox_iobx_tgt_id, // local_index 66 size_t iox_iobx_ini_id, // local index 67 68 size_t memc_ways, 69 size_t memc_sets, 70 size_t l1_i_ways, 71 size_t l1_i_sets, 72 size_t l1_d_ways, 73 size_t l1_d_sets, 74 size_t xram_latency, 75 size_t xcu_nb_inputs, 76 77 bool distboot, 78 79 const Loader &loader, 80 81 uint32_t frozen_cycles, 82 uint32_t debug_start_cycle, 83 bool memc_debug_ok, 84 bool proc_debug_ok, 85 bool iob_debug_ok ) : 86 87 // constructor initialization list 88 89 soclib::caba::BaseModule(insname), 90 p_clk("clk"), 91 p_resetn("resetn") 88 92 { 89 assert( (x_id < xmax) and (y_id < ymax) and "Illegal cluster coordinates"); 90 91 size_t cluster_id = (x_id<<4) + y_id; 93 94 assert( (x_id < x_size) and (y_id < y_size) and "Illegal cluster coordinates"); 95 96 size_t cluster_id = (x_id << x_width) | y_id; 92 97 93 98 // Vectors of DSPIN ports for inter-cluster communications … … 103 108 104 109 // VCI ports from IOB to IOX network (only in IO clusters) 105 if ( is_io)110 if (is_io) 106 111 { 107 112 p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>; 108 p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>; 113 p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>; 109 114 } 110 115 … … 115 120 //////////// PROCS 116 121 for (size_t p = 0; p < nb_procs; p++) 117 { 122 { 118 123 std::ostringstream s_proc; 119 124 s_proc << "proc_" << x_id << "_" << y_id << "_" << p; … … 123 128 GdbServer<Mips32ElIss> >( 124 129 s_proc.str().c_str(), 125 cluster_id*nb_procs + p,// GLOBAL PROC_ID130 (cluster_id << p_width) | p, // GLOBAL PROC_ID 126 131 mt_int, // Mapping Table INT network 127 132 IntTab(cluster_id,p), // SRCID 128 (cluster_id << l_width) +p, // CC_GLOBAL_ID133 (cluster_id << l_width) | p, // CC_GLOBAL_ID 129 134 8, // ITLB ways 130 135 8, // ITLB sets … … 135 140 4, // WBUF nlines 136 141 4, // WBUF nwords 137 x_width, 138 y_width, 142 x_width, // number of bits for x coordinate 143 y_width, // number of bits for y coordinate 139 144 frozen_cycles, // max frozen cycles 140 145 debug_start_cycle, … … 150 155 } 151 156 152 /////////// MEMC 157 /////////// MEMC 153 158 std::ostringstream s_memc; 154 159 s_memc << "memc_" << x_id << "_" << y_id; … … 225 230 cluster_id, // cluster id 226 231 nb_direct_initiators, // number of local initiators 227 nb_direct_targets, // number of local targets 232 nb_direct_targets, // number of local targets 228 233 0 ); // default target 229 234 … … 255 260 x_width, y_width, l_width, // several dests 256 261 1, // number of local sources 257 nb_procs, // number of local dests 258 2, 2, // fifo depths 262 nb_procs, // number of local dests 263 2, 2, // fifo depths 259 264 true, // pseudo CMD 260 265 false, // no routing table … … 270 275 nb_procs, // number of local sources 271 276 1, // number of local dests 272 2, 2, // fifo depths 277 2, 2, // fifo depths 273 278 false, // pseudo RSP 274 279 false, // no routing table 275 false ); // no broacast 280 false ); // no broacast 276 281 277 282 std::ostringstream s_int_xbar_clack_c; … … 283 288 x_width, y_width, l_width, 284 289 1, // number of local sources 285 nb_procs, // number of local targets 290 nb_procs, // number of local targets 286 291 1, 1, // fifo depths 287 292 true, // CMD … … 297 302 x_width, y_width, // x & y fields width 298 303 3, // nb virtual channels 299 4, 4);// input & output fifo depths304 4, 4); // input & output fifo depths 300 305 301 306 std::ostringstream s_int_router_rsp; … … 306 311 x_width, y_width, // x & y fields width 307 312 2, // nb virtual channels 308 4, 4);// input & output fifo depths313 4, 4); // input & output fifo depths 309 314 310 315 ////////////// XRAM … … 351 356 /////////// IO_BRIDGE 352 357 std::ostringstream s_iob; 353 s_iob << "iob_" << x_id << "_" << y_id; 358 s_iob << "iob_" << x_id << "_" << y_id; 354 359 iob = new VciIoBridge<vci_param_int, 355 vci_param_ext>( 360 vci_param_ext>( 356 361 s_iob.str().c_str(), 357 362 mt_ram, // EXT network maptab … … 367 372 debug_start_cycle, 368 373 iob_debug_ok ); 369 374 370 375 std::ostringstream s_iob_ram_wi; 371 s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id; 376 s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id; 372 377 iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext, 373 378 dspin_ram_cmd_width, … … 409 414 // on coherence network : local srcid[proc] in [0...nb_procs-1] 410 415 // : local srcid[memc] = nb_procs 411 416 412 417 //////////////////////// internal CMD & RSP routers 413 418 int_router_cmd->p_clk (this->p_clk); … … 438 443 int_router_cmd->p_in[4][1] (signal_int_dspin_m2p_l2g_c); 439 444 int_router_cmd->p_in[4][2] (signal_int_dspin_clack_l2g_c); 440 445 441 446 int_router_rsp->p_out[4][0] (signal_int_dspin_rsp_g2l_d); 442 447 int_router_rsp->p_out[4][1] (signal_int_dspin_p2m_g2l_c); … … 475 480 int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d); 476 481 int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d); 477 482 478 483 ////////////////////// M2P DSPIN local crossbar coherence 479 484 int_xbar_m2p_c->p_clk (this->p_clk); … … 482 487 int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c); 483 488 int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc); 484 for (size_t p = 0; p < nb_procs; p++) 489 for (size_t p = 0; p < nb_procs; p++) 485 490 int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]); 486 491 … … 491 496 int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c); 492 497 int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc); 493 for (size_t p = 0; p < nb_procs; p++) 498 for (size_t p = 0; p < nb_procs; p++) 494 499 int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]); 495 500 … … 533 538 else if ( i <= nb_dmas ) xicu->p_hwi[i] (signal_irq_mdma[i-1]); 534 539 else xicu->p_hwi[i] (signal_false); 535 } 540 } 536 541 537 542 ///////////////////////////////////// MEMC … … 603 608 ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i); 604 609 } 605 606 ///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1. 610 611 ///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1. 607 612 if ( is_io ) 608 613 {
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