- Timestamp:
- Sep 24, 2014, 3:48:50 PM (10 years ago)
- Location:
- branches/RWT/modules/vci_mem_cache
- Files:
-
- 3 edited
-
. (modified) (1 prop)
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caba/source/include (modified) (1 prop)
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caba/source/include/vci_mem_cache.h (modified) (21 diffs)
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branches/RWT/modules/vci_mem_cache
- Property svn:mergeinfo changed
/trunk/modules/vci_mem_cache (added) merged: 597,599,601,603,605,617
- Property svn:mergeinfo changed
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branches/RWT/modules/vci_mem_cache/caba/source/include
- Property svn:mergeinfo changed
/trunk/modules/vci_mem_cache/caba/source/include (added) merged: 597,599,601,605
- Property svn:mergeinfo changed
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branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r787 r814 25 25 * SOCLIB_LGPL_HEADER_END 26 26 * 27 * Maintainers: alain.greiner@lip6.fr 27 * Maintainers: alain.greiner@lip6.fr 28 28 * eric.guthmuller@polytechnique.edu 29 29 * cesar.fuguet-tortolero@lip6.fr … … 62 62 using namespace sc_core; 63 63 64 template<typename vci_param_int, 64 template<typename vci_param_int, 65 65 typename vci_param_ext, 66 66 size_t dspin_in_width, … … 416 416 }; 417 417 418 // debug variables 418 // debug variables 419 419 bool m_debug; 420 420 bool m_debug_previous_valid; … … 479 479 uint32_t m_cpt_heap_unused; // NB cycles HEAP LOCK unused 480 480 uint32_t m_cpt_heap_slot_available; // NB HEAP slot available refresh at each cycles 481 uint32_t m_cpt_heap_min_slot_available; // NB HEAP : Min of slot available 481 uint32_t m_cpt_heap_min_slot_available; // NB HEAP : Min of slot available 482 482 483 483 uint32_t m_cpt_ncc_to_cc_read; // NB change from NCC to CC caused by a READ … … 525 525 526 526 #if MONITOR_MEMCACHE_FSM == 1 527 sc_out<int> p_read_fsm; 528 sc_out<int> p_write_fsm; 529 sc_out<int> p_xram_rsp_fsm; 530 sc_out<int> p_cas_fsm; 531 sc_out<int> p_cleanup_fsm; 532 sc_out<int> p_config_fsm; 533 sc_out<int> p_alloc_heap_fsm; 534 sc_out<int> p_alloc_dir_fsm; 535 sc_out<int> p_alloc_trt_fsm; 536 sc_out<int> p_alloc_upt_fsm; 537 sc_out<int> p_alloc_ivt_fsm; 538 sc_out<int> p_tgt_cmd_fsm; 539 sc_out<int> p_tgt_rsp_fsm; 540 sc_out<int> p_ixr_cmd_fsm; 541 sc_out<int> p_ixr_rsp_fsm; 542 sc_out<int> p_cc_send_fsm; 543 sc_out<int> p_cc_receive_fsm; 544 sc_out<int> p_multi_ack_fsm; 527 sc_out<int> p_read_fsm; 528 sc_out<int> p_write_fsm; 529 sc_out<int> p_xram_rsp_fsm; 530 sc_out<int> p_cas_fsm; 531 sc_out<int> p_cleanup_fsm; 532 sc_out<int> p_config_fsm; 533 sc_out<int> p_alloc_heap_fsm; 534 sc_out<int> p_alloc_dir_fsm; 535 sc_out<int> p_alloc_trt_fsm; 536 sc_out<int> p_alloc_upt_fsm; 537 sc_out<int> p_alloc_ivt_fsm; 538 sc_out<int> p_tgt_cmd_fsm; 539 sc_out<int> p_tgt_rsp_fsm; 540 sc_out<int> p_ixr_cmd_fsm; 541 sc_out<int> p_ixr_rsp_fsm; 542 sc_out<int> p_cc_send_fsm; 543 sc_out<int> p_cc_receive_fsm; 544 sc_out<int> p_multi_ack_fsm; 545 545 #endif 546 546 … … 558 558 const size_t max_copies, // max number of copies 559 559 const size_t heap_size=HEAP_ENTRIES, 560 const size_t trt_lines=TRT_ENTRIES, 561 const size_t upt_lines=UPT_ENTRIES, 562 const size_t ivt_lines=IVT_ENTRIES, 560 const size_t trt_lines=TRT_ENTRIES, 561 const size_t upt_lines=UPT_ENTRIES, 562 const size_t ivt_lines=IVT_ENTRIES, 563 563 const size_t debug_start_cycle=0, 564 564 const bool debug_ok=false ); … … 584 584 585 585 // Component attributes 586 std::list<soclib::common::Segment> m_seglist; // segments allocated 586 std::list<soclib::common::Segment> m_seglist; // segments allocated 587 587 size_t m_nseg; // number of segments 588 588 soclib::common::Segment **m_seg; // array of segments pointers … … 657 657 // Fifo between CC_RECEIVE fsm and CLEANUP fsm 658 658 GenericFifo<uint64_t> m_cc_receive_to_cleanup_fifo; 659 659 660 660 // Fifo between CC_RECEIVE fsm and MULTI_ACK fsm 661 661 GenericFifo<uint64_t> m_cc_receive_to_multi_ack_fifo; … … 686 686 sc_signal<int> r_config_fsm; // FSM state 687 687 sc_signal<bool> r_config_lock; // lock protecting exclusive access 688 sc_signal<int> r_config_cmd; // config request type 688 sc_signal<int> r_config_cmd; // config request type 689 689 sc_signal<addr_t> r_config_address; // target buffer physical address 690 690 sc_signal<size_t> r_config_srcid; // config request srcid … … 702 702 sc_signal<size_t> r_config_heap_next; // current pointer to scan HEAP 703 703 sc_signal<size_t> r_config_trt_index; // selected entry in TRT 704 sc_signal<size_t> r_config_ivt_index; // selected entry in IVT 704 sc_signal<size_t> r_config_ivt_index; // selected entry in IVT 705 705 706 706 // Buffer between CONFIG fsm and IXR_CMD fsm … … 744 744 sc_signal<addr_t> r_read_ll_key; // LL key from llsc_global_table 745 745 746 // Buffer between READ fsm and IXR_CMD fsm 746 // Buffer between READ fsm and IXR_CMD fsm 747 747 sc_signal<bool> r_read_to_ixr_cmd_req; // valid request 748 748 sc_signal<size_t> r_read_to_ixr_cmd_index; // TRT index … … 764 764 sc_signal<bool> r_read_to_cc_send_inst; 765 765 766 //RWT: Buffer between READ fsm and CLEANUP fsm (wait for the data coming from L1 cache) 766 //RWT: Buffer between READ fsm and CLEANUP fsm (wait for the data coming from L1 cache) 767 767 sc_signal<bool> r_read_to_cleanup_req; // valid request 768 768 sc_signal<addr_t> r_read_to_cleanup_nline; // cache line index … … 771 771 sc_signal<size_t> r_read_to_cleanup_length; 772 772 sc_signal<size_t> r_read_to_cleanup_first_word; 773 sc_signal<bool> r_read_to_cleanup_cached_read; 773 sc_signal<bool> r_read_to_cleanup_cached_read; 774 774 sc_signal<bool> r_read_to_cleanup_is_ll; 775 775 sc_signal<addr_t> r_read_to_cleanup_addr; … … 810 810 sc_signal<data_t> r_write_sc_key; // sc command key 811 811 sc_signal<bool> r_write_bc_data_we; // Write enable for data buffer 812 812 813 813 // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1) 814 814 sc_signal<bool> r_write_to_tgt_rsp_req; // valid request … … 818 818 sc_signal<bool> r_write_to_tgt_rsp_sc_fail; // sc command failed 819 819 820 // Buffer between WRITE fsm and IXR_CMD fsm 820 // Buffer between WRITE fsm and IXR_CMD fsm 821 821 sc_signal<bool> r_write_to_ixr_cmd_req; // valid request 822 sc_signal<size_t> r_write_to_ixr_cmd_index; // TRT index 822 sc_signal<size_t> r_write_to_ixr_cmd_index; // TRT index 823 823 824 824 // Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches) … … 908 908 sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid 909 909 sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid 910 sc_signal<addr_t> 910 sc_signal<addr_t> r_cleanup_to_tgt_rsp_ll_key; 911 911 912 912 //RWT … … 948 948 // Buffer between CAS fsm and IXR_CMD fsm (XRAM write) 949 949 sc_signal<bool> r_cas_to_ixr_cmd_req; // valid request 950 sc_signal<size_t> r_cas_to_ixr_cmd_index; // TRT index 950 sc_signal<size_t> r_cas_to_ixr_cmd_index; // TRT index 951 951 952 952 // Buffer between CAS fsm and TGT_RSP fsm … … 978 978 979 979 // Buffer between IXR_RSP fsm and CONFIG fsm (response from the XRAM) 980 sc_signal<bool> r_ixr_rsp_to_config_ack; // one single bit 980 sc_signal<bool> r_ixr_rsp_to_config_ack; // one single bit 981 981 982 982 // Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM) … … 1028 1028 GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo; // fifo for srcids 1029 1029 1030 // Buffer between XRAM_RSP fsm and IXR_CMD fsm 1030 // Buffer between XRAM_RSP fsm and IXR_CMD fsm 1031 1031 sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request 1032 sc_signal<size_t> r_xram_rsp_to_ixr_cmd_index; // TRT index 1032 sc_signal<size_t> r_xram_rsp_to_ixr_cmd_index; // TRT index 1033 1033 1034 1034 //RWT … … 1041 1041 sc_signal<int> r_ixr_cmd_fsm; 1042 1042 sc_signal<size_t> r_ixr_cmd_word; // word index for a put 1043 sc_signal<size_t> r_ixr_cmd_trdid; // TRT index value 1043 sc_signal<size_t> r_ixr_cmd_trdid; // TRT index value 1044 1044 sc_signal<addr_t> r_ixr_cmd_address; // address to XRAM 1045 1045 sc_signal<data_t> * r_ixr_cmd_wdata; // cache line buffer … … 1112 1112 sc_signal<data_t> *r_cleanup_old_data; 1113 1113 sc_signal<bool> r_cleanup_contains_data; 1114 1114 1115 1115 sc_signal<bool> r_cleanup_ncc; 1116 1116 sc_signal<bool> r_cleanup_to_ixr_cmd_ncc_l1_dirty; 1117 1117 sc_signal<bool> r_xram_rsp_to_ixr_cmd_inval_ncc_pending; 1118 1118 1119 1119 sc_signal<bool> r_cleanup_to_ixr_cmd_req; 1120 1120 sc_signal<data_t> *r_cleanup_to_ixr_cmd_data;
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