- Timestamp:
- Sep 30, 2014, 3:32:13 PM (10 years ago)
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branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r814 r823 69 69 : public soclib::caba::BaseModule 70 70 { 71 typedef typename vci_param_int::fast_addr_t 72 typedef typename sc_dt::sc_uint<64> 73 typedef uint32_t 74 typedef uint32_t 75 typedef uint32_t 76 typedef uint32_t 71 typedef typename vci_param_int::fast_addr_t addr_t; 72 typedef typename sc_dt::sc_uint<64> wide_data_t; 73 typedef uint32_t data_t; 74 typedef uint32_t tag_t; 75 typedef uint32_t be_t; 76 typedef uint32_t copy_t; 77 77 78 78 /* States of the TGT_CMD fsm */ … … 113 113 CC_RECEIVE_IDLE, 114 114 CC_RECEIVE_CLEANUP, 115 CC_RECEIVE_CLEANUP_EOP,116 115 CC_RECEIVE_MULTI_ACK 117 116 }; … … 232 231 { 233 232 IXR_RSP_IDLE, 234 IXR_RSP_ACK,235 233 IXR_RSP_TRT_ERASE, 236 234 IXR_RSP_TRT_READ … … 399 397 // b1 accÚs table llsc type SW / other 400 398 // b2 WRITE/CAS/LL/SC 401 TYPE_READ_DATA_UNC 402 TYPE_READ_DATA_MISS 403 TYPE_READ_INS_UNC 404 TYPE_READ_INS_MISS 405 TYPE_WRITE 406 TYPE_CAS 407 TYPE_LL 408 TYPE_SC 399 TYPE_READ_DATA_UNC = 0x0, 400 TYPE_READ_DATA_MISS = 0x1, 401 TYPE_READ_INS_UNC = 0x2, 402 TYPE_READ_INS_MISS = 0x3, 403 TYPE_WRITE = 0x4, 404 TYPE_CAS = 0x5, 405 TYPE_LL = 0x6, 406 TYPE_SC = 0x7 409 407 }; 410 408 … … 425 423 426 424 // instrumentation counters 427 uint32_t m_cpt_cycles; // Counter of cycles425 uint32_t m_cpt_cycles; // Counter of cycles 428 426 429 427 // Counters accessible in software (not yet but eventually) and tagged 430 uint32_t m_cpt_reset_count; // Last cycle at which counters have been reset431 uint32_t m_cpt_read_local; // Number of local READ transactions432 uint32_t m_cpt_read_remote; // number of remote READ transactions433 uint32_t m_cpt_read_cost; // Number of (flits * distance) for READs434 435 uint32_t m_cpt_write_local; // Number of local WRITE transactions436 uint32_t m_cpt_write_remote; // number of remote WRITE transactions437 uint32_t m_cpt_write_flits_local; // number of flits for local WRITEs438 uint32_t m_cpt_write_flits_remote; // number of flits for remote WRITEs439 uint32_t m_cpt_write_cost; // Number of (flits * distance) for WRITEs440 uint32_t m_cpt_write_ncc_miss; // Number of write on ncc line441 442 uint32_t m_cpt_ll_local; // Number of local LL transactions443 uint32_t m_cpt_ll_remote; // number of remote LL transactions444 uint32_t m_cpt_ll_cost; // Number of (flits * distance) for LLs445 446 uint32_t m_cpt_sc_local; // Number of local SC transactions447 uint32_t m_cpt_sc_remote; // number of remote SC transactions448 uint32_t m_cpt_sc_cost; // Number of (flits * distance) for SCs449 450 uint32_t m_cpt_cas_local; // Number of local SC transactions451 uint32_t m_cpt_cas_remote; // number of remote SC transactions452 uint32_t m_cpt_cas_cost; // Number of (flits * distance) for SCs453 454 uint32_t m_cpt_update; // Number of requests causing an UPDATE455 uint32_t m_cpt_update_local; // Number of local UPDATE transactions456 uint32_t m_cpt_update_remote; // Number of remote UPDATE transactions457 uint32_t m_cpt_update_cost; // Number of (flits * distance) for UPDT458 459 uint32_t m_cpt_minval; // Number of requests causing M_INV460 uint32_t m_cpt_minval_local; // Number of local M_INV transactions461 uint32_t m_cpt_minval_remote; // Number of remote M_INV transactions462 uint32_t m_cpt_minval_cost; // Number of (flits * distance) for M_INV463 464 uint32_t m_cpt_binval; // Number of BROADCAST INVAL465 466 uint32_t m_cpt_cleanup_local; // Number of local CLEANUP transactions (all cleanup types)467 uint32_t m_cpt_cleanup_remote; // Number of remote CLEANUP transactions (all cleanup types)468 uint32_t m_cpt_cleanup_cost; // Number of (flits * distance) for CLEANUPs (all types)428 uint32_t m_cpt_reset_count; // Last cycle at which counters have been reset 429 uint32_t m_cpt_read_local; // Number of local READ transactions 430 uint32_t m_cpt_read_remote; // number of remote READ transactions 431 uint32_t m_cpt_read_cost; // Number of (flits * distance) for READs 432 433 uint32_t m_cpt_write_local; // Number of local WRITE transactions 434 uint32_t m_cpt_write_remote; // number of remote WRITE transactions 435 uint32_t m_cpt_write_flits_local; // number of flits for local WRITEs 436 uint32_t m_cpt_write_flits_remote; // number of flits for remote WRITEs 437 uint32_t m_cpt_write_cost; // Number of (flits * distance) for WRITEs 438 uint32_t m_cpt_write_ncc_miss; // Number of write on ncc line 439 440 uint32_t m_cpt_ll_local; // Number of local LL transactions 441 uint32_t m_cpt_ll_remote; // number of remote LL transactions 442 uint32_t m_cpt_ll_cost; // Number of (flits * distance) for LLs 443 444 uint32_t m_cpt_sc_local; // Number of local SC transactions 445 uint32_t m_cpt_sc_remote; // number of remote SC transactions 446 uint32_t m_cpt_sc_cost; // Number of (flits * distance) for SCs 447 448 uint32_t m_cpt_cas_local; // Number of local SC transactions 449 uint32_t m_cpt_cas_remote; // number of remote SC transactions 450 uint32_t m_cpt_cas_cost; // Number of (flits * distance) for SCs 451 452 uint32_t m_cpt_update; // Number of requests causing an UPDATE 453 uint32_t m_cpt_update_local; // Number of local UPDATE transactions 454 uint32_t m_cpt_update_remote; // Number of remote UPDATE transactions 455 uint32_t m_cpt_update_cost; // Number of (flits * distance) for UPDT 456 457 uint32_t m_cpt_minval; // Number of requests causing M_INV 458 uint32_t m_cpt_minval_local; // Number of local M_INV transactions 459 uint32_t m_cpt_minval_remote; // Number of remote M_INV transactions 460 uint32_t m_cpt_minval_cost; // Number of (flits * distance) for M_INV 461 462 uint32_t m_cpt_binval; // Number of BROADCAST INVAL 463 464 uint32_t m_cpt_cleanup_local; // Number of local CLEANUP transactions (all cleanup types) 465 uint32_t m_cpt_cleanup_remote; // Number of remote CLEANUP transactions (all cleanup types) 466 uint32_t m_cpt_cleanup_cost; // Number of (flits * distance) for CLEANUPs (all types) 469 467 470 468 // Counters not accessible by software, but tagged 471 uint32_t m_cpt_read_miss; // Number of MISS READ472 uint32_t m_cpt_write_miss; // Number of MISS WRITE473 uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions474 uint32_t m_cpt_write_broadcast; // Number of BROADCAST INVAL because write475 476 uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt477 uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt469 uint32_t m_cpt_read_miss; // Number of MISS READ 470 uint32_t m_cpt_write_miss; // Number of MISS WRITE 471 uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions 472 uint32_t m_cpt_write_broadcast; // Number of BROADCAST INVAL because write 473 474 uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt 475 uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt 478 476 479 477 uint32_t m_cpt_heap_unused; // NB cycles HEAP LOCK unused … … 481 479 uint32_t m_cpt_heap_min_slot_available; // NB HEAP : Min of slot available 482 480 483 uint32_t m_cpt_ncc_to_cc_read; // NB change from NCC to CC caused by a READ484 uint32_t m_cpt_ncc_to_cc_write; // NB change from NCC to CC caused by a WRITE485 486 uint32_t m_cpt_cleanup_data_local; // Number of local cleanups with data487 uint32_t m_cpt_cleanup_data_remote; // Number of remote cleanups with data488 uint32_t m_cpt_cleanup_data_cost; // Cost for cleanups with data489 490 uint32_t m_cpt_update_flits; // Number of flits for UPDATEs491 uint32_t m_cpt_inval_cost; // Number of (flits * distance) for INVALs481 uint32_t m_cpt_ncc_to_cc_read; // NB change from NCC to CC caused by a READ 482 uint32_t m_cpt_ncc_to_cc_write; // NB change from NCC to CC caused by a WRITE 483 484 uint32_t m_cpt_cleanup_data_local; // Number of local cleanups with data 485 uint32_t m_cpt_cleanup_data_remote; // Number of remote cleanups with data 486 uint32_t m_cpt_cleanup_data_cost; // Cost for cleanups with data 487 488 uint32_t m_cpt_update_flits; // Number of flits for UPDATEs 489 uint32_t m_cpt_inval_cost; // Number of (flits * distance) for INVALs 492 490 493 491 uint32_t m_cpt_get; … … 499 497 uint32_t m_cpt_upt_unused; // NB cycles UPT LOCK unused 500 498 501 // Unused502 uint32_t m_cpt_read_data_unc;503 uint32_t m_cpt_read_data_miss_CC;504 uint32_t m_cpt_read_ins_unc;505 uint32_t m_cpt_read_ins_miss;506 uint32_t m_cpt_read_ll_CC;507 uint32_t m_cpt_read_data_miss_NCC;508 uint32_t m_cpt_read_ll_NCC;509 510 499 size_t m_prev_count; 511 500 … … 515 504 516 505 public: 517 sc_in<bool> 518 sc_in<bool> 519 sc_out<bool> 520 soclib::caba::VciTarget<vci_param_int> 521 soclib::caba::VciInitiator<vci_param_ext> 522 soclib::caba::DspinInput<dspin_in_width> 523 soclib::caba::DspinOutput<dspin_out_width> 524 soclib::caba::DspinOutput<dspin_out_width> 506 sc_in<bool> p_clk; 507 sc_in<bool> p_resetn; 508 sc_out<bool> p_irq; 509 soclib::caba::VciTarget<vci_param_int> p_vci_tgt; 510 soclib::caba::VciInitiator<vci_param_ext> p_vci_ixr; 511 soclib::caba::DspinInput<dspin_in_width> p_dspin_p2m; 512 soclib::caba::DspinOutput<dspin_out_width> p_dspin_m2p; 513 soclib::caba::DspinOutput<dspin_out_width> p_dspin_clack; 525 514 526 515 #if MONITOR_MEMCACHE_FSM == 1 … … 557 546 const size_t nwords, // Number of words per line 558 547 const size_t max_copies, // max number of copies 559 const size_t heap_size =HEAP_ENTRIES,560 const size_t trt_lines =TRT_ENTRIES,561 const size_t upt_lines =UPT_ENTRIES,562 const size_t ivt_lines =IVT_ENTRIES,563 const size_t debug_start_cycle =0,564 const bool debug_ok =false );548 const size_t heap_size = HEAP_ENTRIES, 549 const size_t trt_lines = TRT_ENTRIES, 550 const size_t upt_lines = UPT_ENTRIES, 551 const size_t ivt_lines = IVT_ENTRIES, 552 const size_t debug_start_cycle = 0, 553 const bool debug_ok = false ); 565 554 566 555 ~VciMemCache(); … … 568 557 void reset_counters(); 569 558 void print_stats(bool activity_counters = true, bool stats = false); 570 void print_trace( size_t detailled = 0);559 void print_trace(size_t detailled = 0); 571 560 void cache_monitor(addr_t addr); 572 561 void start_monitor(addr_t addr, addr_t length); … … 581 570 uint32_t min_value(uint32_t old_value, uint32_t new_value); 582 571 bool is_local_req(uint32_t req_srcid); 583 int 572 int read_instrumentation(uint32_t regr, uint32_t & rdata); 584 573 585 574 // Component attributes … … 616 605 617 606 // adress masks 618 const soclib::common::AddressMaskingTable<addr_t> 619 const soclib::common::AddressMaskingTable<addr_t> 620 const soclib::common::AddressMaskingTable<addr_t> 621 const soclib::common::AddressMaskingTable<addr_t> 607 const soclib::common::AddressMaskingTable<addr_t> m_x; 608 const soclib::common::AddressMaskingTable<addr_t> m_y; 609 const soclib::common::AddressMaskingTable<addr_t> m_z; 610 const soclib::common::AddressMaskingTable<addr_t> m_nline; 622 611 623 612 // broadcast address 624 uint32_t 613 uint32_t m_broadcast_boundaries; 625 614 626 615 // configuration interface constants … … 632 621 633 622 // Fifo between TGT_CMD fsm and READ fsm 634 GenericFifo<addr_t> 635 GenericFifo<size_t> 636 GenericFifo<size_t> 637 GenericFifo<size_t> 638 GenericFifo<size_t> 623 GenericFifo<addr_t> m_cmd_read_addr_fifo; 624 GenericFifo<size_t> m_cmd_read_length_fifo; 625 GenericFifo<size_t> m_cmd_read_srcid_fifo; 626 GenericFifo<size_t> m_cmd_read_trdid_fifo; 627 GenericFifo<size_t> m_cmd_read_pktid_fifo; 639 628 640 629 // Fifo between TGT_CMD fsm and WRITE fsm 641 GenericFifo<addr_t> 642 GenericFifo<bool> 643 GenericFifo<size_t> 644 GenericFifo<size_t> 645 GenericFifo<size_t> 646 GenericFifo<data_t> 647 GenericFifo<be_t> 630 GenericFifo<addr_t> m_cmd_write_addr_fifo; 631 GenericFifo<bool> m_cmd_write_eop_fifo; 632 GenericFifo<size_t> m_cmd_write_srcid_fifo; 633 GenericFifo<size_t> m_cmd_write_trdid_fifo; 634 GenericFifo<size_t> m_cmd_write_pktid_fifo; 635 GenericFifo<data_t> m_cmd_write_data_fifo; 636 GenericFifo<be_t> m_cmd_write_be_fifo; 648 637 649 638 // Fifo between TGT_CMD fsm and CAS fsm 650 GenericFifo<addr_t> 651 GenericFifo<bool> 652 GenericFifo<size_t> 653 GenericFifo<size_t> 654 GenericFifo<size_t> 655 GenericFifo<data_t> 639 GenericFifo<addr_t> m_cmd_cas_addr_fifo; 640 GenericFifo<bool> m_cmd_cas_eop_fifo; 641 GenericFifo<size_t> m_cmd_cas_srcid_fifo; 642 GenericFifo<size_t> m_cmd_cas_trdid_fifo; 643 GenericFifo<size_t> m_cmd_cas_pktid_fifo; 644 GenericFifo<data_t> m_cmd_cas_wdata_fifo; 656 645 657 646 // Fifo between CC_RECEIVE fsm and CLEANUP fsm 658 GenericFifo<uint64_t> 647 GenericFifo<uint64_t> m_cc_receive_to_cleanup_fifo; 659 648 660 649 // Fifo between CC_RECEIVE fsm and MULTI_ACK fsm 661 GenericFifo<uint64_t> 650 GenericFifo<uint64_t> m_cc_receive_to_multi_ack_fifo; 662 651 663 652 // Buffer between TGT_CMD fsm and TGT_RSP fsm … … 678 667 ////////////////////////////////////////////////// 679 668 680 sc_signal<int> 669 sc_signal<int> r_tgt_cmd_fsm; 681 670 682 671 /////////////////////////////////////////////////////// … … 684 673 /////////////////////////////////////////////////////// 685 674 686 sc_signal<int> r_config_fsm;// FSM state687 sc_signal<bool> r_config_lock;// lock protecting exclusive access688 sc_signal<int> r_config_cmd;// config request type689 sc_signal<addr_t> r_config_address;// target buffer physical address690 sc_signal<size_t> r_config_srcid;// config request srcid691 sc_signal<size_t> r_config_trdid;// config request trdid692 sc_signal<size_t> r_config_pktid;// config request pktid693 sc_signal<size_t> r_config_cmd_lines;// number of lines to be handled694 sc_signal<size_t> r_config_rsp_lines;// number of lines not completed695 sc_signal<size_t> r_config_dir_way;// DIR: selected way696 sc_signal<bool> r_config_dir_lock;// DIR: locked entry697 sc_signal<size_t> r_config_dir_count;// DIR: number of copies698 sc_signal<bool> r_config_dir_is_cnt;// DIR: counter mode (broadcast)699 sc_signal<size_t> r_config_dir_copy_srcid;// DIR: first copy SRCID700 sc_signal<bool> r_config_dir_copy_inst;// DIR: first copy L1 type701 sc_signal<size_t> r_config_dir_ptr;// DIR: index of next copy in HEAP702 sc_signal<size_t> r_config_heap_next;// current pointer to scan HEAP703 sc_signal<size_t> r_config_trt_index;// selected entry in TRT704 sc_signal<size_t> r_config_ivt_index;// selected entry in IVT675 sc_signal<int> r_config_fsm; // FSM state 676 sc_signal<bool> r_config_lock; // lock protecting exclusive access 677 sc_signal<int> r_config_cmd; // config request type 678 sc_signal<addr_t> r_config_address; // target buffer physical address 679 sc_signal<size_t> r_config_srcid; // config request srcid 680 sc_signal<size_t> r_config_trdid; // config request trdid 681 sc_signal<size_t> r_config_pktid; // config request pktid 682 sc_signal<size_t> r_config_cmd_lines; // number of lines to be handled 683 sc_signal<size_t> r_config_rsp_lines; // number of lines not completed 684 sc_signal<size_t> r_config_dir_way; // DIR: selected way 685 sc_signal<bool> r_config_dir_lock; // DIR: locked entry 686 sc_signal<size_t> r_config_dir_count; // DIR: number of copies 687 sc_signal<bool> r_config_dir_is_cnt; // DIR: counter mode (broadcast) 688 sc_signal<size_t> r_config_dir_copy_srcid; // DIR: first copy SRCID 689 sc_signal<bool> r_config_dir_copy_inst; // DIR: first copy L1 type 690 sc_signal<size_t> r_config_dir_ptr; // DIR: index of next copy in HEAP 691 sc_signal<size_t> r_config_heap_next; // current pointer to scan HEAP 692 sc_signal<size_t> r_config_trt_index; // selected entry in TRT 693 sc_signal<size_t> r_config_ivt_index; // selected entry in IVT 705 694 706 695 // Buffer between CONFIG fsm and IXR_CMD fsm 707 sc_signal<bool> r_config_to_ixr_cmd_req;// valid request708 sc_signal<size_t> r_config_to_ixr_cmd_index;// TRT index696 sc_signal<bool> r_config_to_ixr_cmd_req; // valid request 697 sc_signal<size_t> r_config_to_ixr_cmd_index; // TRT index 709 698 710 699 // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache) 711 sc_signal<bool> r_config_to_tgt_rsp_req;// valid request712 sc_signal<bool> r_config_to_tgt_rsp_error;// error response713 sc_signal<size_t> r_config_to_tgt_rsp_srcid;// Transaction srcid714 sc_signal<size_t> r_config_to_tgt_rsp_trdid;// Transaction trdid715 sc_signal<size_t> r_config_to_tgt_rsp_pktid;// Transaction pktid700 sc_signal<bool> r_config_to_tgt_rsp_req; // valid request 701 sc_signal<bool> r_config_to_tgt_rsp_error; // error response 702 sc_signal<size_t> r_config_to_tgt_rsp_srcid; // Transaction srcid 703 sc_signal<size_t> r_config_to_tgt_rsp_trdid; // Transaction trdid 704 sc_signal<size_t> r_config_to_tgt_rsp_pktid; // Transaction pktid 716 705 717 706 // Buffer between CONFIG fsm and CC_SEND fsm (multi-inval / broadcast-inval) 718 sc_signal<bool> r_config_to_cc_send_multi_req; 719 sc_signal<bool> r_config_to_cc_send_brdcast_req; 720 sc_signal<addr_t> r_config_to_cc_send_nline; 721 sc_signal<size_t> r_config_to_cc_send_trdid; 722 GenericFifo<bool> m_config_to_cc_send_inst_fifo; 723 GenericFifo<size_t> m_config_to_cc_send_srcid_fifo; 707 sc_signal<bool> r_config_to_cc_send_multi_req; // multi-inval request 708 sc_signal<bool> r_config_to_cc_send_brdcast_req; // broadcast-inval request 709 sc_signal<addr_t> r_config_to_cc_send_nline; // line index 710 sc_signal<size_t> r_config_to_cc_send_trdid; // UPT index 711 GenericFifo<bool> m_config_to_cc_send_inst_fifo; // fifo for the L1 type 712 GenericFifo<size_t> m_config_to_cc_send_srcid_fifo; // fifo for owners srcid 724 713 725 714 /////////////////////////////////////////////////////// … … 727 716 /////////////////////////////////////////////////////// 728 717 729 sc_signal<int> r_read_fsm; 730 sc_signal<size_t> r_read_copy; 731 sc_signal<size_t> r_read_copy_cache; 732 sc_signal<bool> r_read_copy_inst; 733 sc_signal<tag_t> r_read_tag; 734 sc_signal<bool> r_read_is_cnt; 735 sc_signal<bool> r_read_lock; 736 sc_signal<bool> r_read_dirty; 737 sc_signal<size_t> r_read_count; 738 sc_signal<size_t> r_read_ptr; 739 sc_signal<data_t> * r_read_data; 740 sc_signal<size_t> r_read_way; 741 sc_signal<size_t> r_read_trt_index; 742 sc_signal<size_t> r_read_next_ptr; 743 sc_signal<bool> r_read_last_free; 744 sc_signal<addr_t> r_read_ll_key; 718 sc_signal<int> r_read_fsm; // FSM state 719 sc_signal<size_t> r_read_copy; // Srcid of the first copy 720 sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy 721 sc_signal<bool> r_read_copy_inst; // Type of the first copy 722 sc_signal<tag_t> r_read_tag; // cache line tag (in directory) 723 sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory) 724 sc_signal<bool> r_read_lock; // lock bit (in directory) 725 sc_signal<bool> r_read_dirty; // dirty bit (in directory) 726 sc_signal<size_t> r_read_count; // number of copies 727 sc_signal<size_t> r_read_ptr; // pointer to the heap 728 sc_signal<data_t> * r_read_data; // data (one cache line) 729 sc_signal<size_t> r_read_way; // associative way (in cache) 730 sc_signal<size_t> r_read_trt_index; // Transaction Table index 731 sc_signal<size_t> r_read_next_ptr; // Next entry to point to 732 sc_signal<bool> r_read_last_free; // Last free entry 733 sc_signal<addr_t> r_read_ll_key; // LL key from llsc_global_table 745 734 746 735 // Buffer between READ fsm and IXR_CMD fsm 747 sc_signal<bool> r_read_to_ixr_cmd_req; 748 sc_signal<size_t> r_read_to_ixr_cmd_index; 736 sc_signal<bool> r_read_to_ixr_cmd_req; // valid request 737 sc_signal<size_t> r_read_to_ixr_cmd_index; // TRT index 749 738 750 739 // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache) 751 sc_signal<bool> r_read_to_tgt_rsp_req; 752 sc_signal<size_t> r_read_to_tgt_rsp_srcid; 753 sc_signal<size_t> r_read_to_tgt_rsp_trdid; 754 sc_signal<size_t> r_read_to_tgt_rsp_pktid; 755 sc_signal<data_t> * r_read_to_tgt_rsp_data; 756 sc_signal<size_t> r_read_to_tgt_rsp_word; 757 sc_signal<size_t> r_read_to_tgt_rsp_length; 758 sc_signal<addr_t> r_read_to_tgt_rsp_ll_key; 740 sc_signal<bool> r_read_to_tgt_rsp_req; // valid request 741 sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid 742 sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid 743 sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid 744 sc_signal<data_t> * r_read_to_tgt_rsp_data; // data (one cache line) 745 sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response 746 sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response 747 sc_signal<addr_t> r_read_to_tgt_rsp_ll_key; // LL key from llsc_global_table 759 748 760 749 //RWT: Buffer between READ fsm and CC_SEND fsm (send inval) … … 777 766 778 767 //RWT: 779 sc_signal<bool> r_read_coherent; 768 sc_signal<bool> r_read_coherent; // State of the cache slot after transaction 780 769 sc_signal<bool> r_read_ll_done; 781 770 … … 839 828 840 829 // RWT: Buffer between WRITE fsm and CLEANUP fsm (change slot state) 841 sc_signal<bool> r_write_to_cleanup_req; 842 sc_signal<addr_t> r_write_to_cleanup_nline; 830 sc_signal<bool> r_write_to_cleanup_req; // valid request 831 sc_signal<addr_t> r_write_to_cleanup_nline; // cache line index 843 832 844 833 // RWT 845 sc_signal<bool> r_write_coherent; 834 sc_signal<bool> r_write_coherent; // cache slot state after transaction 846 835 847 836 //Buffer between WRITE fsm and CC_SEND fsm (INVAL for RWT) … … 1114 1103 1115 1104 sc_signal<bool> r_cleanup_ncc; 1116 sc_signal<bool> r_cleanup_to_ixr_cmd_ncc_l1_dirty;1117 sc_signal<bool> r_xram_rsp_to_ixr_cmd_inval_ncc_pending;1118 1105 1119 1106 sc_signal<bool> r_cleanup_to_ixr_cmd_req;
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